Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16260277	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

139766560

1

T1

74867

T2

1661

T3

9797

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	76791887	1			T1	41052		T2	4787		T3	3304
values[0x0]	37995765	1			T1	19638		T2	1500		T3	3327
values[0x1]	41239185	1			T1	21601		T2	3134		T3	3449

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8265401	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147761436

1

T1

78621

T2

5643

T3

9951

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	514637	1			T1	2573		T2	40		T4	19
valid_sources[0x01]	511475	1			T2	40		T4	7		T5	954
valid_sources[0x02]	560029	1			T2	36		T4	9		T5	988
valid_sources[0x03]	536587	1			T2	23		T4	10		T5	976
valid_sources[0x04]	499891	1			T2	48		T4	20		T5	931
valid_sources[0x05]	512779	1			T2	23		T4	6		T5	1008
valid_sources[0x06]	515804	1			T2	51		T4	35		T5	1099
valid_sources[0x07]	499539	1			T2	29		T3	60		T4	19
valid_sources[0x08]	500424	1			T2	37		T4	29		T5	966
valid_sources[0x09]	522636	1			T2	32		T4	23		T5	1003
valid_sources[0x0a]	550352	1			T1	3808		T2	49		T4	3
valid_sources[0x0b]	529533	1			T2	23		T4	5		T5	877
valid_sources[0x0c]	524633	1			T2	46		T4	13		T5	1045
valid_sources[0x0d]	586375	1			T2	30		T4	9		T5	978
valid_sources[0x0e]	539274	1			T2	40		T4	8		T5	986
valid_sources[0x0f]	506719	1			T2	45		T4	7		T5	920
valid_sources[0x10]	503001	1			T2	36		T4	20		T5	1047
valid_sources[0x11]	565750	1			T2	34		T3	914		T4	17
valid_sources[0x12]	521863	1			T2	49		T4	25		T5	956
valid_sources[0x13]	1292443	1			T2	42		T4	22		T5	999
valid_sources[0x14]	572020	1			T2	31		T4	18		T5	947
valid_sources[0x15]	507894	1			T2	39		T4	6		T5	1058
valid_sources[0x16]	534842	1			T2	48		T4	9		T5	970
valid_sources[0x17]	495860	1			T2	52		T4	18		T5	936
valid_sources[0x18]	532178	1			T2	45		T4	25		T5	1013
valid_sources[0x19]	517874	1			T2	44		T3	848		T4	16
valid_sources[0x1a]	2145952	1			T2	50		T4	16		T5	1016
valid_sources[0x1b]	497768	1			T2	38		T3	248		T4	17
valid_sources[0x1c]	580478	1			T2	35		T4	4		T5	1036
valid_sources[0x1d]	537815	1			T2	34		T4	8		T5	1048
valid_sources[0x1e]	509004	1			T2	52		T3	404		T4	17
valid_sources[0x1f]	488883	1			T2	32		T4	11		T5	982
valid_sources[0x20]	534166	1			T2	53		T4	14		T5	1015
valid_sources[0x21]	560269	1			T2	34		T4	7		T5	993
valid_sources[0x22]	529043	1			T2	48		T4	6		T5	1021
valid_sources[0x23]	518633	1			T2	31		T4	20		T5	988
valid_sources[0x24]	558564	1			T1	32393		T2	38		T4	27
valid_sources[0x25]	530119	1			T1	16298		T2	34		T4	19
valid_sources[0x26]	510018	1			T2	38		T4	31		T5	1056
valid_sources[0x27]	519671	1			T2	32		T4	1		T5	1008
valid_sources[0x28]	510527	1			T2	24		T4	30		T5	1027
valid_sources[0x29]	536487	1			T2	35		T4	9		T5	990
valid_sources[0x2a]	493368	1			T2	45		T4	8		T5	1049
valid_sources[0x2b]	504049	1			T2	35		T4	6		T5	1024
valid_sources[0x2c]	494766	1			T2	38		T4	6		T5	1050
valid_sources[0x2d]	538694	1			T2	23		T4	6		T5	1038
valid_sources[0x2e]	492910	1			T2	36		T3	269		T4	19
valid_sources[0x2f]	544395	1			T1	9122		T2	36		T4	7
valid_sources[0x30]	613311	1			T2	38		T4	26		T5	938
valid_sources[0x31]	495319	1			T2	31		T4	11		T5	978
valid_sources[0x32]	556046	1			T2	27		T4	17		T5	973
valid_sources[0x33]	544819	1			T2	34		T4	24		T5	927
valid_sources[0x34]	513160	1			T2	31		T4	4		T5	986
valid_sources[0x35]	515511	1			T2	45		T4	17		T5	947
valid_sources[0x36]	535083	1			T2	45		T4	15		T5	960
valid_sources[0x37]	560362	1			T2	28		T4	4		T5	1002
valid_sources[0x38]	497695	1			T2	28		T4	15		T5	1046
valid_sources[0x39]	502428	1			T2	40		T4	7		T5	1035
valid_sources[0x3a]	506614	1			T2	43		T4	26		T5	1099
valid_sources[0x3b]	528063	1			T2	37		T4	11		T5	1000
valid_sources[0x3c]	571659	1			T2	43		T4	11		T5	967
valid_sources[0x3d]	523792	1			T2	23		T4	15		T5	973
valid_sources[0x3e]	556880	1			T2	33		T3	654		T4	8
valid_sources[0x3f]	506608	1			T2	45		T4	17		T5	987
valid_sources[0x40]	541226	1			T2	33		T4	15		T5	1045
valid_sources[0x41]	531203	1			T2	34		T4	5		T5	998
valid_sources[0x42]	1676316	1			T2	34		T4	4		T5	1038
valid_sources[0x43]	529708	1			T2	41		T4	11		T5	1061
valid_sources[0x44]	1636640	1			T2	52		T4	12		T5	1016
valid_sources[0x45]	583583	1			T2	33		T4	21		T5	950
valid_sources[0x46]	540383	1			T2	24		T4	12		T5	960
valid_sources[0x47]	492413	1			T2	28		T4	8		T5	949
valid_sources[0x48]	1953305	1			T2	39		T3	247		T4	11
valid_sources[0x49]	548166	1			T2	40		T4	29		T5	981
valid_sources[0x4a]	525908	1			T2	27		T4	7		T5	1056
valid_sources[0x4b]	521412	1			T2	33		T4	16		T5	1021
valid_sources[0x4c]	504172	1			T2	35		T4	17		T5	1042
valid_sources[0x4d]	504411	1			T2	31		T4	13		T5	959
valid_sources[0x4e]	529467	1			T2	36		T4	1		T5	949
valid_sources[0x4f]	503115	1			T2	32		T4	15		T5	1068
valid_sources[0x50]	632974	1			T2	53		T4	6		T5	973
valid_sources[0x51]	492241	1			T2	28		T4	6		T5	951
valid_sources[0x52]	527147	1			T2	52		T4	17		T5	937
valid_sources[0x53]	522024	1			T2	40		T4	5		T5	960
valid_sources[0x54]	494716	1			T2	31		T4	11		T5	975
valid_sources[0x55]	522231	1			T2	42		T4	10		T5	1017
valid_sources[0x56]	492730	1			T2	41		T4	8		T5	972
valid_sources[0x57]	496727	1			T2	41		T4	12		T5	944
valid_sources[0x58]	522362	1			T2	50		T4	6		T5	1002
valid_sources[0x59]	524441	1			T2	32		T4	30		T5	942
valid_sources[0x5a]	504925	1			T2	32		T4	3		T5	1016
valid_sources[0x5b]	498616	1			T2	42		T4	7		T5	987
valid_sources[0x5c]	538921	1			T2	42		T4	4		T5	984
valid_sources[0x5d]	542766	1			T2	43		T4	20		T5	992
valid_sources[0x5e]	537469	1			T2	43		T4	15		T5	978
valid_sources[0x5f]	516616	1			T2	38		T4	13		T5	1006
valid_sources[0x60]	548484	1			T2	43		T4	3		T5	982
valid_sources[0x61]	573078	1			T2	43		T4	23		T5	1034
valid_sources[0x62]	578585	1			T2	33		T4	11		T5	995
valid_sources[0x63]	501064	1			T2	60		T4	7		T5	988
valid_sources[0x64]	532362	1			T2	32		T4	10		T5	960
valid_sources[0x65]	510142	1			T2	22		T4	15		T5	1009
valid_sources[0x66]	567620	1			T2	26		T4	9		T5	964
valid_sources[0x67]	505133	1			T2	32		T4	32		T5	958
valid_sources[0x68]	526801	1			T2	35		T3	141		T4	11
valid_sources[0x69]	553557	1			T2	40		T4	28		T5	1011
valid_sources[0x6a]	556953	1			T2	37		T4	20		T5	978
valid_sources[0x6b]	515436	1			T2	18		T4	33		T5	911
valid_sources[0x6c]	519776	1			T2	29		T4	7		T5	1030
valid_sources[0x6d]	496962	1			T2	34		T3	303		T4	6
valid_sources[0x6e]	531961	1			T2	40		T4	5		T5	967
valid_sources[0x6f]	544850	1			T2	46		T4	27		T5	1032
valid_sources[0x70]	511275	1			T2	45		T4	19		T5	1020
valid_sources[0x71]	532725	1			T2	61		T4	14		T5	968
valid_sources[0x72]	569611	1			T2	37		T4	15		T5	1013
valid_sources[0x73]	507577	1			T2	32		T4	9		T5	1029
valid_sources[0x74]	584663	1			T2	39		T4	25		T5	1050
valid_sources[0x75]	511721	1			T2	28		T4	9		T5	1050
valid_sources[0x76]	498781	1			T2	48		T4	8		T5	975
valid_sources[0x77]	518177	1			T2	30		T4	12		T5	1011
valid_sources[0x78]	518488	1			T2	32		T4	28		T5	940
valid_sources[0x79]	586566	1			T1	5047		T2	40		T4	19
valid_sources[0x7a]	491358	1			T2	38		T4	14		T5	986
valid_sources[0x7b]	498001	1			T2	35		T4	19		T5	999
valid_sources[0x7c]	560942	1			T2	29		T4	12		T5	984
valid_sources[0x7d]	574665	1			T2	41		T4	17		T5	937
valid_sources[0x7e]	497731	1			T2	32		T4	26		T5	922
valid_sources[0x7f]	1640202	1			T2	38		T4	10		T5	995
valid_sources[0x80]	525463	1			T2	37		T4	15		T5	1015

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68619288

1

T1

37318

T2

849

T3

3152

values[0x0]

all_enables

biggest_size

35572024

1

T1

18551

T2

394

T3

3297

values[0x1]

all_enables

biggest_size

35575248

1

T1

18998

T2

418

T3

3348

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152239

1

T1

1

T3

3453

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53978	1			T3	955		T6	22		T22	24
values[0x0]	68361	1			T1	5		T2	1		T3	1284
values[0x1]	73646	1			T1	5		T3	1436		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33593	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162392

1

T1

1

T3

3557

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	670	1			T3	11		T21	16		T54	2
valid_sources[0x01]	1053	1			T3	11		T21	5		T149	1
valid_sources[0x02]	893	1			T3	12		T21	11		T24	2
valid_sources[0x03]	774	1			T3	11		T10	1		T21	9
valid_sources[0x04]	669	1			T3	20		T10	5		T21	15
valid_sources[0x05]	833	1			T3	12		T10	4		T21	17
valid_sources[0x06]	643	1			T3	9		T5	1		T10	2
valid_sources[0x07]	675	1			T3	18		T21	6		T55	13
valid_sources[0x08]	773	1			T3	12		T10	3		T21	13
valid_sources[0x09]	880	1			T3	11		T21	17		T43	1
valid_sources[0x0a]	617	1			T3	20		T10	2		T21	11
valid_sources[0x0b]	762	1			T3	9		T6	2		T22	1
valid_sources[0x0c]	672	1			T3	10		T21	15		T18	4
valid_sources[0x0d]	851	1			T3	17		T12	5		T22	3
valid_sources[0x0e]	693	1			T3	10		T22	19		T21	17
valid_sources[0x0f]	582	1			T3	18		T21	6		T24	2
valid_sources[0x10]	646	1			T3	18		T21	8		T18	4
valid_sources[0x11]	620	1			T3	9		T10	3		T21	6
valid_sources[0x12]	992	1			T3	18		T21	8		T54	5
valid_sources[0x13]	819	1			T3	9		T6	3		T10	1
valid_sources[0x14]	645	1			T3	8		T10	1		T21	13
valid_sources[0x15]	655	1			T3	10		T21	13		T45	1
valid_sources[0x16]	601	1			T3	16		T41	3		T21	10
valid_sources[0x17]	726	1			T3	14		T21	15		T42	1
valid_sources[0x18]	901	1			T3	20		T21	6		T43	1
valid_sources[0x19]	763	1			T3	8		T21	9		T18	4
valid_sources[0x1a]	554	1			T3	14		T10	3		T21	7
valid_sources[0x1b]	680	1			T3	10		T22	5		T21	5
valid_sources[0x1c]	774	1			T3	25		T10	1		T21	11
valid_sources[0x1d]	807	1			T3	13		T10	3		T21	14
valid_sources[0x1e]	636	1			T3	15		T10	3		T21	17
valid_sources[0x1f]	831	1			T3	16		T21	7		T45	10
valid_sources[0x20]	881	1			T3	18		T22	2		T21	15
valid_sources[0x21]	644	1			T3	25		T21	9		T24	6
valid_sources[0x22]	1005	1			T3	11		T21	11		T149	1
valid_sources[0x23]	764	1			T3	11		T21	14		T24	1
valid_sources[0x24]	754	1			T3	11		T21	6		T56	2
valid_sources[0x25]	593	1			T3	7		T21	9		T150	1
valid_sources[0x26]	559	1			T3	19		T6	1		T21	10
valid_sources[0x27]	651	1			T3	16		T21	11		T24	1
valid_sources[0x28]	695	1			T3	22		T21	7		T18	1
valid_sources[0x29]	770	1			T3	25		T6	1		T10	5
valid_sources[0x2a]	797	1			T3	14		T12	4		T21	10
valid_sources[0x2b]	1031	1			T3	9		T10	1		T21	5
valid_sources[0x2c]	824	1			T3	14		T6	1		T21	14
valid_sources[0x2d]	958	1			T3	6		T6	3		T21	12
valid_sources[0x2e]	601	1			T3	17		T21	11		T18	2
valid_sources[0x2f]	947	1			T3	14		T6	1		T21	8
valid_sources[0x30]	696	1			T3	13		T5	1		T21	8
valid_sources[0x31]	541	1			T3	15		T22	3		T21	13
valid_sources[0x32]	829	1			T1	1		T3	9		T21	9
valid_sources[0x33]	592	1			T3	14		T21	4		T56	6
valid_sources[0x34]	698	1			T3	19		T21	16		T18	1
valid_sources[0x35]	822	1			T3	21		T21	11		T42	1
valid_sources[0x36]	773	1			T3	11		T21	13		T151	1
valid_sources[0x37]	619	1			T3	9		T10	1		T21	14
valid_sources[0x38]	993	1			T3	14		T21	9		T56	1
valid_sources[0x39]	916	1			T3	19		T10	3		T48	1
valid_sources[0x3a]	581	1			T3	13		T21	11		T54	1
valid_sources[0x3b]	589	1			T3	19		T21	13		T24	1
valid_sources[0x3c]	668	1			T3	10		T21	19		T56	1
valid_sources[0x3d]	737	1			T3	16		T21	8		T55	38
valid_sources[0x3e]	871	1			T3	14		T41	1		T21	9
valid_sources[0x3f]	958	1			T3	11		T21	17		T152	1
valid_sources[0x40]	564	1			T3	22		T21	10		T18	1
valid_sources[0x41]	819	1			T3	15		T21	8		T24	1
valid_sources[0x42]	832	1			T1	1		T3	12		T22	2
valid_sources[0x43]	631	1			T3	13		T10	3		T21	10
valid_sources[0x44]	995	1			T3	17		T21	12		T18	1
valid_sources[0x45]	601	1			T3	18		T21	6		T18	1
valid_sources[0x46]	1035	1			T3	9		T21	12		T24	2
valid_sources[0x47]	872	1			T3	11		T9	1		T21	12
valid_sources[0x48]	766	1			T3	19		T25	1		T21	12
valid_sources[0x49]	656	1			T3	15		T21	9		T42	2
valid_sources[0x4a]	715	1			T3	15		T22	6		T21	12
valid_sources[0x4b]	559	1			T3	16		T21	12		T18	2
valid_sources[0x4c]	896	1			T3	17		T21	11		T54	1
valid_sources[0x4d]	643	1			T3	11		T10	4		T21	16
valid_sources[0x4e]	642	1			T3	18		T21	10		T43	1
valid_sources[0x4f]	913	1			T3	13		T10	5		T21	9
valid_sources[0x50]	957	1			T3	19		T6	1		T21	15
valid_sources[0x51]	612	1			T1	1		T3	23		T6	1
valid_sources[0x52]	756	1			T3	10		T21	9		T153	2
valid_sources[0x53]	537	1			T3	14		T10	4		T21	5
valid_sources[0x54]	1060	1			T3	13		T21	13		T18	2
valid_sources[0x55]	997	1			T3	15		T10	1		T21	15
valid_sources[0x56]	925	1			T3	13		T21	6		T18	1
valid_sources[0x57]	741	1			T3	12		T21	18		T18	3
valid_sources[0x58]	629	1			T3	12		T10	7		T21	10
valid_sources[0x59]	741	1			T3	12		T21	14		T18	2
valid_sources[0x5a]	786	1			T3	11		T22	1		T21	7
valid_sources[0x5b]	744	1			T3	14		T10	1		T21	12
valid_sources[0x5c]	854	1			T3	18		T4	1		T21	19
valid_sources[0x5d]	805	1			T3	19		T10	1		T21	11
valid_sources[0x5e]	911	1			T3	7		T9	1		T21	14
valid_sources[0x5f]	692	1			T3	6		T21	18		T24	3
valid_sources[0x60]	553	1			T3	15		T21	10		T45	1
valid_sources[0x61]	699	1			T3	18		T21	12		T18	1
valid_sources[0x62]	845	1			T3	11		T21	7		T24	2
valid_sources[0x63]	719	1			T3	12		T21	11		T42	1
valid_sources[0x64]	767	1			T1	1		T3	14		T21	15
valid_sources[0x65]	750	1			T3	12		T21	7		T56	1
valid_sources[0x66]	611	1			T3	12		T10	2		T22	4
valid_sources[0x67]	594	1			T3	18		T21	13		T42	1
valid_sources[0x68]	689	1			T3	20		T10	2		T21	9
valid_sources[0x69]	929	1			T3	14		T41	14		T21	13
valid_sources[0x6a]	699	1			T3	15		T4	1		T10	7
valid_sources[0x6b]	722	1			T3	10		T21	13		T43	1
valid_sources[0x6c]	561	1			T3	13		T6	2		T21	10
valid_sources[0x6d]	740	1			T3	21		T6	3		T21	14
valid_sources[0x6e]	676	1			T3	15		T10	6		T21	10
valid_sources[0x6f]	675	1			T3	9		T9	2		T21	18
valid_sources[0x70]	716	1			T3	11		T6	1		T21	13
valid_sources[0x71]	719	1			T3	16		T21	6		T56	1
valid_sources[0x72]	953	1			T3	13		T22	5		T21	6
valid_sources[0x73]	707	1			T3	22		T21	10		T145	1
valid_sources[0x74]	932	1			T3	12		T21	9		T139	1
valid_sources[0x75]	722	1			T3	20		T21	16		T18	1
valid_sources[0x76]	671	1			T3	11		T21	4		T45	1
valid_sources[0x77]	667	1			T3	16		T5	1		T6	1
valid_sources[0x78]	661	1			T3	10		T21	13		T18	2
valid_sources[0x79]	952	1			T3	19		T6	2		T22	11
valid_sources[0x7a]	919	1			T3	18		T10	7		T21	6
valid_sources[0x7b]	801	1			T3	21		T21	12		T18	2
valid_sources[0x7c]	763	1			T3	8		T21	14		T54	3
valid_sources[0x7d]	634	1			T3	16		T6	2		T21	10
valid_sources[0x7e]	739	1			T3	14		T41	1		T21	12
valid_sources[0x7f]	1048	1			T3	20		T21	7		T55	74
valid_sources[0x80]	737	1			T3	16		T21	5		T18	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40982

1

T3

890

T6

11

T22

13

values[0x0]

all_enables

biggest_size

56925

1

T1

1

T3

1265

T5

1

values[0x1]

all_enables

biggest_size

54332

1

T3

1298

T6

2

T10

20