Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16158306

1

T1

7424

T2

7760

T3

6354

full_word

136646153

1

T1

74867

T2

1661

T3

10016

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	152804169	1			T1	82291		T2	9421		T3	16370
auto[TlIntgErrCmd]	104	1			T64	5		T65	3		T66	10
auto[TlIntgErrData]	92	1			T64	8		T65	3		T66	4
auto[TlIntgErrBoth]	94	1			T64	7		T65	4		T66	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73496739

1

T1

41052

T2

4787

T3

4097

auto[1]

79307720

1

T1

41239

T2

4634

T3

12273

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7911662	1			T1	3734		T2	3938		T3	1309
auto[TlIntgErrNone]	partial	auto[1]	8246381	1			T1	3690		T2	3822		T3	5045
auto[TlIntgErrNone]	full_word	auto[0]	65584954	1			T1	37318		T2	849		T3	2788
auto[TlIntgErrNone]	full_word	auto[1]	71061172	1			T1	37549		T2	812		T3	7228
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T64	3		T65	1		T66	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T64	2		T65	2		T66	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T129	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T66	2		T128	1		T129	2
auto[TlIntgErrData]	partial	auto[0]	39	1			T64	2		T66	3		T126	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T64	6		T65	2		T126	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T65	1		T66	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T134	2		T130	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T64	1		T66	1		T128	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T64	5		T65	4		T66	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T66	1		T132	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T64	1		T66	2		T136	1