Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	771143	1			T6	9		T21	19		T40	4343
auto[1]	10872779	1			T1	25181		T5	106713		T6	8
auto[2]	584745	1			T6	5		T21	14		T40	4088
auto[3]	10611987	1			T1	25433		T5	106661		T6	6

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13815697	1			T1	42358		T5	176421		T6	20
auto[1]	2226000	1			T1	3912		T5	17608		T6	3
auto[2]	2248969	1			T1	3959		T5	17555		T6	3
auto[3]	4549988	1			T1	385		T5	1790		T6	2

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8755589

1

T1

50614

T6

28

T39

2493

auto[1]

14085065

1

T5

213374

T9

71069

T48

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	288798	1			T6	7		T21	15		T85	1092
auto[0]	auto[0]	auto[1]	30221	1			T6	1		T21	2		T40	36
auto[0]	auto[0]	auto[2]	30068	1			T6	1		T21	2		T40	29
auto[0]	auto[0]	auto[3]	39878	1			T40	4275		T85	15		T8	1
auto[0]	auto[1]	auto[0]	3228693	1			T1	21039		T6	5		T39	1020
auto[0]	auto[1]	auto[1]	339471	1			T1	1843		T6	2		T39	85
auto[0]	auto[1]	auto[2]	343115	1			T1	2099		T39	95		T22	730
auto[0]	auto[1]	auto[3]	230032	1			T1	200		T6	1		T39	13
auto[0]	auto[2]	auto[0]	200282	1			T6	4		T40	2		T85	914
auto[0]	auto[2]	auto[1]	23060	1			T40	260		T85	118		T139	860
auto[0]	auto[2]	auto[2]	25702	1			T6	1		T21	10		T40	38
auto[0]	auto[2]	auto[3]	28772	1			T21	4		T40	3788		T85	10
auto[0]	auto[3]	auto[0]	3072975	1			T1	21319		T6	4		T39	1067
auto[0]	auto[3]	auto[1]	325455	1			T1	2069		T39	103		T22	392
auto[0]	auto[3]	auto[2]	340309	1			T1	1860		T6	1		T39	103
auto[0]	auto[3]	auto[3]	208758	1			T1	185		T6	1		T39	7
auto[1]	auto[0]	auto[0]	12551	1			T139	1		T120	638		T138	101
auto[1]	auto[0]	auto[1]	56703	1			T120	2695		T138	520		T140	3188
auto[1]	auto[0]	auto[2]	57040	1			T120	2756		T138	524		T140	3212
auto[1]	auto[0]	auto[3]	255884	1			T40	3		T120	12666		T138	2285
auto[1]	auto[1]	auto[0]	3500133	1			T5	88168		T9	29258		T18	1
auto[1]	auto[1]	auto[1]	718418	1			T5	8866		T9	3026		T116	4299
auto[1]	auto[1]	auto[2]	699380	1			T5	8799		T9	2922		T116	4591
auto[1]	auto[1]	auto[3]	1813537	1			T5	880		T9	311		T141	1
auto[1]	auto[2]	auto[0]	9980	1			T120	606		T140	679		T142	1
auto[1]	auto[2]	auto[1]	45056	1			T120	2577		T140	2934		T143	1504
auto[1]	auto[2]	auto[2]	45508	1			T120	1966		T138	443		T140	2095
auto[1]	auto[2]	auto[3]	206385	1			T120	8675		T138	2089		T140	9468
auto[1]	auto[3]	auto[0]	3502285	1			T5	88253		T9	29518		T48	1
auto[1]	auto[3]	auto[1]	687616	1			T5	8742		T9	2859		T116	4672
auto[1]	auto[3]	auto[2]	707847	1			T5	8756		T9	2881		T116	4207
auto[1]	auto[3]	auto[3]	1766742	1			T5	910		T9	294		T116	438