Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1110358121	220103	0	0
ctrl_regwen_rd_A	1110358121	5339	0	0
exec_rd_A	1110358121	4746	0	0
exec_regwen_rd_A	1110358121	5402	0	0
readback_rd_A	1110358121	3855	0	0
readback_regwen_rd_A	1110358121	3791	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110358121	220103	0	0
T3	164665	5058	0	0
T4	105990	0	0	0
T5	533204	0	0	0
T6	576864	0	0	0
T9	296420	0	0	0
T10	103437	0	0	0
T11	108202	0	0	0
T12	1616	0	0	0
T21	0	4373	0	0
T23	0	2924	0	0
T39	36369	0	0	0
T48	75555	0	0	0
T49	0	5144	0	0
T59	0	4352	0	0
T61	0	5863	0	0
T70	0	1425	0	0
T71	0	6062	0	0
T72	0	1437	0	0
T73	0	4051	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110358121	5339	0	0
T7	370957	0	0	0
T13	1671	0	0	0
T18	482591	0	0	0
T21	143987	302	0	0
T26	35983	0	0	0
T27	33738	0	0	0
T40	456384	0	0	0
T42	299182	0	0	0
T49	0	432	0	0
T50	0	566	0	0
T61	0	424	0	0
T62	0	267	0	0
T71	0	589	0	0
T72	0	124	0	0
T85	103925	0	0	0
T86	239417	0	0	0
T122	0	164	0	0
T123	0	62	0	0
T124	0	209	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110358121	4746	0	0
T7	370957	0	0	0
T13	1671	0	0	0
T18	482591	0	0	0
T21	143987	281	0	0
T26	35983	0	0	0
T27	33738	0	0	0
T40	456384	0	0	0
T42	299182	0	0	0
T49	0	399	0	0
T50	0	547	0	0
T61	0	368	0	0
T62	0	149	0	0
T71	0	381	0	0
T72	0	163	0	0
T85	103925	0	0	0
T86	239417	0	0	0
T122	0	135	0	0
T123	0	63	0	0
T124	0	233	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110358121	5402	0	0
T7	370957	0	0	0
T13	1671	0	0	0
T18	482591	0	0	0
T21	143987	251	0	0
T26	35983	0	0	0
T27	33738	0	0	0
T40	456384	0	0	0
T42	299182	0	0	0
T49	0	396	0	0
T50	0	628	0	0
T61	0	394	0	0
T62	0	245	0	0
T71	0	463	0	0
T72	0	101	0	0
T85	103925	0	0	0
T86	239417	0	0	0
T122	0	134	0	0
T123	0	73	0	0
T124	0	272	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110358121	3855	0	0
T7	370957	0	0	0
T13	1671	0	0	0
T18	482591	0	0	0
T21	143987	219	0	0
T26	35983	0	0	0
T27	33738	0	0	0
T40	456384	0	0	0
T42	299182	0	0	0
T49	0	358	0	0
T50	0	512	0	0
T61	0	329	0	0
T62	0	192	0	0
T71	0	359	0	0
T72	0	117	0	0
T85	103925	0	0	0
T86	239417	0	0	0
T122	0	115	0	0
T123	0	83	0	0
T124	0	266	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110358121	3791	0	0
T7	370957	0	0	0
T13	1671	0	0	0
T18	482591	0	0	0
T21	143987	246	0	0
T26	35983	0	0	0
T27	33738	0	0	0
T40	456384	0	0	0
T42	299182	0	0	0
T49	0	313	0	0
T50	0	552	0	0
T61	0	422	0	0
T62	0	195	0	0
T71	0	438	0	0
T72	0	153	0	0
T85	103925	0	0	0
T86	239417	0	0	0
T122	0	106	0	0
T123	0	58	0	0
T124	0	273	0	0