Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	333937508	1			T1	862		T2	25174		T3	10232
instr_valid_dis	286450326	1			T1	862		T2	25174		T3	10232
instr_en	30922811	1			T31	284128		T32	115340		T6	248358

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15403306	1			T31	82380		T32	118336		T23	128478
sram_ifetch_valid_disable	290348584	1			T1	862		T2	25174		T3	10232
sram_ifetch_enable	28185618	1			T31	108050		T32	32282		T33	20036

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	333937508	1			T1	862		T2	25174		T3	10232
hw_debug_en_valid_off	289658322	1			T1	862		T2	25174		T3	10232
hw_debug_en_on	29046262	1			T31	157080		T32	46808		T6	60624

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	290348584	1			T1	862		T2	25174		T3	10232
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	272593480	1			T1	862		T2	25174		T3	10232
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11326107	1			T31	93798		T32	47770		T6	248358
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6458606	1			T31	51504		T32	91806		T23	42286
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2041708	1			T32	73096		T26	7666		T139	27522
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3472896	1			T31	51504		T32	18710		T26	62762
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6748002	1			T31	30876		T32	26530		T23	86192
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1800490	1			T138	16260		T25	20324		T26	39104
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1856926	1			T31	30876		T32	26530		T25	31752
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11553288	1			T31	43814		T32	20278		T6	60624
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5275830	1			T32	11860		T138	38684		T25	156222
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5115876	1			T31	43814		T32	8418		T6	60624

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13390102	1			T31	107950		T32	22330		T138	91344
lc_exec_en	10744972	1			T31	82390		T33	20036		T23	42960
valid_exec_dis	280831420	1			T1	862		T2	25174		T3	10232
invalid_exec_dis	43588924	1			T31	190430		T32	150618		T33	20036