Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Total tests in report: 1038

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
76.60	76.60	92.31	92.31	79.74	79.74	90.74	90.74	23.81	23.81	82.23	82.23	93.86	93.86	73.49	73.49	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1254941275
85.90	9.31	96.16	3.84	83.53	3.79	91.63	0.90	71.43	47.62	88.63	6.40	95.18	1.32	74.77	1.28	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3334178652
89.72	3.82	97.47	1.31	87.44	3.91	92.94	1.31	80.95	9.52	92.18	3.55	95.18	0.00	81.90	7.13	/workspace/coverage/default/37.sram_ctrl_stress_all.3452742683
92.88	3.16	98.45	0.98	87.56	0.12	93.01	0.07	100.00	19.05	94.08	1.90	95.18	0.00	81.90	0.00	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3259667864
93.98	1.10	98.77	0.33	87.56	0.00	94.18	1.17	100.00	0.00	94.55	0.47	95.61	0.44	87.20	5.30	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.443720958
94.87	0.89	98.94	0.16	88.15	0.59	94.39	0.21	100.00	0.00	95.26	0.71	95.61	0.00	91.77	4.57	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2112545371
95.58	0.70	99.10	0.16	89.93	1.78	95.14	0.76	100.00	0.00	95.97	0.71	96.20	0.58	92.69	0.91	/workspace/coverage/default/1.sram_ctrl_sec_cm.514734231
96.20	0.62	99.10	0.00	89.93	0.00	96.38	1.24	100.00	0.00	95.97	0.00	96.93	0.73	95.06	2.38	/workspace/coverage/default/33.sram_ctrl_regwen.1034738694
96.50	0.31	99.10	0.00	90.28	0.36	97.76	1.38	100.00	0.00	96.21	0.24	96.93	0.00	95.25	0.18	/workspace/coverage/default/47.sram_ctrl_lc_escalation.3462029407
96.74	0.23	99.10	0.00	90.52	0.24	97.83	0.07	100.00	0.00	96.21	0.00	98.25	1.32	95.25	0.00	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3996358403
96.92	0.19	99.10	0.00	90.64	0.12	98.28	0.45	100.00	0.00	96.21	0.00	98.98	0.73	95.25	0.00	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3384058125
97.08	0.16	99.10	0.00	90.64	0.00	98.28	0.00	100.00	0.00	96.21	0.00	98.98	0.00	96.34	1.10	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.92391511
97.21	0.13	99.18	0.08	90.64	0.00	99.10	0.83	100.00	0.00	96.21	0.00	98.98	0.00	96.34	0.00	/workspace/coverage/default/1.sram_ctrl_ram_cfg.1914337035
97.29	0.08	99.18	0.00	90.64	0.00	99.48	0.38	100.00	0.00	96.21	0.00	98.98	0.00	96.53	0.18	/workspace/coverage/default/7.sram_ctrl_lc_escalation.2206100450
97.35	0.06	99.18	0.00	91.00	0.36	99.55	0.07	100.00	0.00	96.21	0.00	98.98	0.00	96.53	0.00	/workspace/coverage/default/20.sram_ctrl_alert_test.2247968301
97.40	0.05	99.18	0.00	91.00	0.00	99.55	0.00	100.00	0.00	96.21	0.00	98.98	0.00	96.89	0.37	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1740951507
97.45	0.05	99.18	0.00	91.00	0.00	99.55	0.00	100.00	0.00	96.21	0.00	98.98	0.00	97.26	0.37	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3340114465
97.48	0.03	99.18	0.00	91.00	0.00	99.55	0.00	100.00	0.00	96.21	0.00	98.98	0.00	97.44	0.18	/workspace/coverage/default/13.sram_ctrl_regwen.4094617717
97.50	0.02	99.18	0.00	91.00	0.00	99.72	0.17	100.00	0.00	96.21	0.00	98.98	0.00	97.44	0.00	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1101458527
97.52	0.02	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	99.12	0.15	97.44	0.00	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.930538569

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3868782585
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1109221495
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3846063223
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.689809905
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3833075703
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.57125862
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4171803508
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.247342577
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4007818855
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2662168375
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.394669562
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1949974711
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2312635811
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.436851800
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1314971850
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.703019979
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3122381758
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3014441010
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2103590932
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1829561730
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1876128582
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1369949452
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1461107954
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2681334872
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.760545941
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.973594369
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3778693187
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.693219056
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1769833260
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.739903816
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.360161888
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2173630408
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2695930223
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2764741257
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3958650427
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1085788742
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.138535828
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.292307790
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1048205032
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.801854310
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.35641636
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3000980047
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1057829016
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.609281197
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2974809014
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3493736032
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3249651593
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3295065195
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3936351824
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1945814941
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3266759563
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3239007560
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3267201101
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3308201269
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4106818438
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1635871524
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.496203291
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.563846935
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2419700134
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.934339148
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2079456361
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3996966466
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.334678251
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2973848236
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1728156091
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.523929798
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2827458715
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4134163
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1723429306
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4147711433
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4126579990
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2159000007
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3447216985
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3166340099
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.617426932
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.591425240
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3616379207
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3628832136
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1195499837
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3537638357
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3163520753
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1960295755
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1049655356
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1247792415
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1866576627
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.293485908
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3679445123
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1689953827
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3740343202
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4016471462
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1923266728
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1354105362
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3024492977
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1085583690
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2164421741
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3035798656
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4059599000
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3690212767
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1326197031
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1556855850
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2916970032
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3955976888
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.385726930
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1934165152
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1290623269
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.200346428
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1906319000
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2692024539
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3304026754
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.622538956
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2927293381
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3845632656
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3005831459
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1242773078
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4186583712
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.464627160
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1697607179
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3874497064
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3057821120
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2211021544
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1713343150
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1951964159
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4060569292
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2927784998
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1969643124
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3348872314
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2741951055
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3023548104
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2598066357
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2421889454
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1058630818
/workspace/coverage/default/0.sram_ctrl_alert_test.2967196685
/workspace/coverage/default/0.sram_ctrl_bijection.1664149572
/workspace/coverage/default/0.sram_ctrl_executable.3580633643
/workspace/coverage/default/0.sram_ctrl_lc_escalation.4101046070
/workspace/coverage/default/0.sram_ctrl_max_throughput.2197778910
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.495918611
/workspace/coverage/default/0.sram_ctrl_mem_walk.4073165231
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3304216495
/workspace/coverage/default/0.sram_ctrl_partial_access.3098964258
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4276969637
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1475569879
/workspace/coverage/default/0.sram_ctrl_regwen.3755611426
/workspace/coverage/default/0.sram_ctrl_sec_cm.3674845853
/workspace/coverage/default/0.sram_ctrl_smoke.2798690907
/workspace/coverage/default/0.sram_ctrl_stress_all.487774039
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.116963700
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1639373180
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.963507751
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3834045038
/workspace/coverage/default/1.sram_ctrl_alert_test.614390561
/workspace/coverage/default/1.sram_ctrl_bijection.404242114
/workspace/coverage/default/1.sram_ctrl_executable.2057282078
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1156791152
/workspace/coverage/default/1.sram_ctrl_max_throughput.2634306316
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3920489886
/workspace/coverage/default/1.sram_ctrl_mem_walk.4207833728
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1120399175
/workspace/coverage/default/1.sram_ctrl_partial_access.4125092163
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4259187298
/workspace/coverage/default/1.sram_ctrl_regwen.2390664911
/workspace/coverage/default/1.sram_ctrl_smoke.2494686823
/workspace/coverage/default/1.sram_ctrl_stress_all.2442049982
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3806128671
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1315178352
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3334751907
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2705493735
/workspace/coverage/default/10.sram_ctrl_alert_test.151514933
/workspace/coverage/default/10.sram_ctrl_bijection.1338252491
/workspace/coverage/default/10.sram_ctrl_executable.1525378356
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2138011046
/workspace/coverage/default/10.sram_ctrl_max_throughput.1277450705
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3270706313
/workspace/coverage/default/10.sram_ctrl_mem_walk.3874560127
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2060279409
/workspace/coverage/default/10.sram_ctrl_partial_access.1130765514
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.995254364
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1632544777
/workspace/coverage/default/10.sram_ctrl_regwen.3583383881
/workspace/coverage/default/10.sram_ctrl_smoke.478007940
/workspace/coverage/default/10.sram_ctrl_stress_all.3807715409
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4202278220
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.904528145
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3089057873
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.598456620
/workspace/coverage/default/11.sram_ctrl_alert_test.3977650176
/workspace/coverage/default/11.sram_ctrl_bijection.1443875958
/workspace/coverage/default/11.sram_ctrl_executable.3122641733
/workspace/coverage/default/11.sram_ctrl_lc_escalation.356582024
/workspace/coverage/default/11.sram_ctrl_max_throughput.3425747705
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/workspace/coverage/default/41.sram_ctrl_stress_pipeline.871466931
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.4197510772
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1067498987
/workspace/coverage/default/42.sram_ctrl_alert_test.1130319825
/workspace/coverage/default/42.sram_ctrl_bijection.1348696004
/workspace/coverage/default/42.sram_ctrl_executable.2638759007
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1176223878
/workspace/coverage/default/42.sram_ctrl_max_throughput.2183284812
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2031649043
/workspace/coverage/default/42.sram_ctrl_mem_walk.772327065
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2885214972
/workspace/coverage/default/42.sram_ctrl_partial_access.4151473251
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1296291483
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1767418863
/workspace/coverage/default/42.sram_ctrl_regwen.860645188
/workspace/coverage/default/42.sram_ctrl_smoke.2506549615
/workspace/coverage/default/42.sram_ctrl_stress_all.489508017
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1359559312
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3085055404
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1102970982
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1432206646
/workspace/coverage/default/43.sram_ctrl_alert_test.139274390
/workspace/coverage/default/43.sram_ctrl_bijection.579141730
/workspace/coverage/default/43.sram_ctrl_executable.848913510
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2001165225
/workspace/coverage/default/43.sram_ctrl_max_throughput.1521374330
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2510314142
/workspace/coverage/default/43.sram_ctrl_mem_walk.2920027375
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2231548187
/workspace/coverage/default/43.sram_ctrl_partial_access.2803866205
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1584009451
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2239498906
/workspace/coverage/default/43.sram_ctrl_regwen.132137082
/workspace/coverage/default/43.sram_ctrl_smoke.1634132929
/workspace/coverage/default/43.sram_ctrl_stress_all.2979015196
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2702346382
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4216800940
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.403795645
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2458891287
/workspace/coverage/default/44.sram_ctrl_alert_test.2933114112
/workspace/coverage/default/44.sram_ctrl_bijection.879775537
/workspace/coverage/default/44.sram_ctrl_executable.3988892387
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2983325790
/workspace/coverage/default/44.sram_ctrl_max_throughput.2141136631
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.765513985
/workspace/coverage/default/44.sram_ctrl_mem_walk.1288973568
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2924538543
/workspace/coverage/default/44.sram_ctrl_partial_access.467316180
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1538906925
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3124732494
/workspace/coverage/default/44.sram_ctrl_regwen.1679020177
/workspace/coverage/default/44.sram_ctrl_smoke.2089102666
/workspace/coverage/default/44.sram_ctrl_stress_all.2769501411
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4036661441
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.4113784823
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2574933829
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1881775699
/workspace/coverage/default/45.sram_ctrl_alert_test.934812272
/workspace/coverage/default/45.sram_ctrl_bijection.4136307761
/workspace/coverage/default/45.sram_ctrl_executable.984958378
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1266777270
/workspace/coverage/default/45.sram_ctrl_max_throughput.119676231
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.308924695
/workspace/coverage/default/45.sram_ctrl_mem_walk.3331391134
/workspace/coverage/default/45.sram_ctrl_multiple_keys.587526048
/workspace/coverage/default/45.sram_ctrl_partial_access.483937903
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3366201935
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2977921241
/workspace/coverage/default/45.sram_ctrl_regwen.1996167233
/workspace/coverage/default/45.sram_ctrl_smoke.4128605534
/workspace/coverage/default/45.sram_ctrl_stress_all.780239945
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3187036234
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.810476864
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2814383256
/workspace/coverage/default/46.sram_ctrl_alert_test.134707117
/workspace/coverage/default/46.sram_ctrl_bijection.2104248352
/workspace/coverage/default/46.sram_ctrl_executable.3267578632
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3913659196
/workspace/coverage/default/46.sram_ctrl_max_throughput.368708666
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3817958846
/workspace/coverage/default/46.sram_ctrl_mem_walk.4264998255
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2077732976
/workspace/coverage/default/46.sram_ctrl_partial_access.3318903467
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3198423060
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3776290657
/workspace/coverage/default/46.sram_ctrl_regwen.3876491597
/workspace/coverage/default/46.sram_ctrl_smoke.3452645008
/workspace/coverage/default/46.sram_ctrl_stress_all.1948576965
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1785127289
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3237922828
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2777124451
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1856760125
/workspace/coverage/default/47.sram_ctrl_alert_test.1169954678
/workspace/coverage/default/47.sram_ctrl_bijection.2959072391
/workspace/coverage/default/47.sram_ctrl_executable.561205265
/workspace/coverage/default/47.sram_ctrl_max_throughput.511634715
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3925737185
/workspace/coverage/default/47.sram_ctrl_mem_walk.3956166103
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2368576583
/workspace/coverage/default/47.sram_ctrl_partial_access.417992975
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.617696112
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3928637751
/workspace/coverage/default/47.sram_ctrl_regwen.2283220969
/workspace/coverage/default/47.sram_ctrl_smoke.2468373232
/workspace/coverage/default/47.sram_ctrl_stress_all.583622657
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3870119916
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.14449193
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4129872786
/workspace/coverage/default/48.sram_ctrl_alert_test.1007365860
/workspace/coverage/default/48.sram_ctrl_bijection.1013146223
/workspace/coverage/default/48.sram_ctrl_executable.255341346
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3921309508
/workspace/coverage/default/48.sram_ctrl_max_throughput.2103432728
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2418263693
/workspace/coverage/default/48.sram_ctrl_mem_walk.2472607756
/workspace/coverage/default/48.sram_ctrl_multiple_keys.878988611
/workspace/coverage/default/48.sram_ctrl_partial_access.688340092
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3025991793
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1414137563
/workspace/coverage/default/48.sram_ctrl_regwen.3735653580
/workspace/coverage/default/48.sram_ctrl_smoke.2290145087
/workspace/coverage/default/48.sram_ctrl_stress_all.1768598952
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1175577266
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1503074261
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2075518672
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.840844017
/workspace/coverage/default/49.sram_ctrl_alert_test.2615258886
/workspace/coverage/default/49.sram_ctrl_bijection.4226145903
/workspace/coverage/default/49.sram_ctrl_executable.1068837780
/workspace/coverage/default/49.sram_ctrl_lc_escalation.709687369
/workspace/coverage/default/49.sram_ctrl_max_throughput.3790317055
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2165896278
/workspace/coverage/default/49.sram_ctrl_mem_walk.873033038
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2907192817
/workspace/coverage/default/49.sram_ctrl_partial_access.1653435594
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3892123050
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3618432075
/workspace/coverage/default/49.sram_ctrl_regwen.2846744975
/workspace/coverage/default/49.sram_ctrl_smoke.520141811
/workspace/coverage/default/49.sram_ctrl_stress_all.1365589372
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.540718119
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3640341892
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3400293656
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3479092162
/workspace/coverage/default/5.sram_ctrl_alert_test.4053902229
/workspace/coverage/default/5.sram_ctrl_bijection.1467654321
/workspace/coverage/default/5.sram_ctrl_executable.2238571841
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2957271485
/workspace/coverage/default/5.sram_ctrl_max_throughput.1781612224
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1135652009
/workspace/coverage/default/5.sram_ctrl_mem_walk.1670860350
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1599300599
/workspace/coverage/default/5.sram_ctrl_partial_access.3045538969
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1625626393
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3976426088
/workspace/coverage/default/5.sram_ctrl_regwen.579969769
/workspace/coverage/default/5.sram_ctrl_smoke.945021470
/workspace/coverage/default/5.sram_ctrl_stress_all.2636745814
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3433724678
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2450968399
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2287464925
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.849109724
/workspace/coverage/default/6.sram_ctrl_alert_test.4172588235
/workspace/coverage/default/6.sram_ctrl_bijection.390171121
/workspace/coverage/default/6.sram_ctrl_executable.139258905
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4048563904
/workspace/coverage/default/6.sram_ctrl_max_throughput.2368677882
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3105281870
/workspace/coverage/default/6.sram_ctrl_mem_walk.1506045361
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2126004639
/workspace/coverage/default/6.sram_ctrl_partial_access.3801811777
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3272791010
/workspace/coverage/default/6.sram_ctrl_ram_cfg.4146598354
/workspace/coverage/default/6.sram_ctrl_regwen.4230941314
/workspace/coverage/default/6.sram_ctrl_smoke.1984241231
/workspace/coverage/default/6.sram_ctrl_stress_all.3766344168
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2788767948
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1817192555
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.35122082
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2084380243
/workspace/coverage/default/7.sram_ctrl_alert_test.3716607504
/workspace/coverage/default/7.sram_ctrl_bijection.1542254493
/workspace/coverage/default/7.sram_ctrl_executable.2071676166
/workspace/coverage/default/7.sram_ctrl_max_throughput.2407868236
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.704588998
/workspace/coverage/default/7.sram_ctrl_mem_walk.2060399228
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3390609796
/workspace/coverage/default/7.sram_ctrl_partial_access.2530374919
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.817307785
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2004062189
/workspace/coverage/default/7.sram_ctrl_regwen.3099493192
/workspace/coverage/default/7.sram_ctrl_smoke.70624224
/workspace/coverage/default/7.sram_ctrl_stress_all.71133126
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2116920680
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3884407549
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3638977563
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1870862928
/workspace/coverage/default/8.sram_ctrl_alert_test.3317866507
/workspace/coverage/default/8.sram_ctrl_bijection.3442372007
/workspace/coverage/default/8.sram_ctrl_executable.3468661729
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4131894545
/workspace/coverage/default/8.sram_ctrl_max_throughput.3827392856
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2618287269
/workspace/coverage/default/8.sram_ctrl_mem_walk.421905344
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2655421012
/workspace/coverage/default/8.sram_ctrl_partial_access.1820564909
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1267935339
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4053275294
/workspace/coverage/default/8.sram_ctrl_regwen.3033067087
/workspace/coverage/default/8.sram_ctrl_smoke.967270057
/workspace/coverage/default/8.sram_ctrl_stress_all.2250845865
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4208338462
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3156475877
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3025415594
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.643538419
/workspace/coverage/default/9.sram_ctrl_alert_test.3330314651
/workspace/coverage/default/9.sram_ctrl_bijection.1498979453
/workspace/coverage/default/9.sram_ctrl_executable.2541502358
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2435305341
/workspace/coverage/default/9.sram_ctrl_max_throughput.532863896
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2650771803
/workspace/coverage/default/9.sram_ctrl_mem_walk.2432886147
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3725760175
/workspace/coverage/default/9.sram_ctrl_partial_access.989693733
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3313470974
/workspace/coverage/default/9.sram_ctrl_ram_cfg.685851103
/workspace/coverage/default/9.sram_ctrl_regwen.2818303121
/workspace/coverage/default/9.sram_ctrl_smoke.2232285210
/workspace/coverage/default/9.sram_ctrl_stress_all.1720819270
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.921273319
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.610741334
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2731255789

Total test records in report: 1038

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/36.sram_ctrl_partial_access.4242428526	Aug 08 05:35:45 PM PDT 24	Aug 08 05:35:50 PM PDT 24	1562616542 ps
T2	/workspace/coverage/default/0.sram_ctrl_multiple_keys.3304216495	Aug 08 05:32:00 PM PDT 24	Aug 08 05:34:30 PM PDT 24	1962416711 ps
T3	/workspace/coverage/default/4.sram_ctrl_smoke.2055014426	Aug 08 05:32:15 PM PDT 24	Aug 08 05:32:27 PM PDT 24	1852345129 ps
T4	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1254941275	Aug 08 05:32:45 PM PDT 24	Aug 08 05:33:09 PM PDT 24	1889139637 ps
T8	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4199818317	Aug 08 05:32:35 PM PDT 24	Aug 08 05:33:03 PM PDT 24	1074941924 ps
T9	/workspace/coverage/default/34.sram_ctrl_smoke.1884729436	Aug 08 05:35:14 PM PDT 24	Aug 08 05:35:26 PM PDT 24	8238437080 ps
T10	/workspace/coverage/default/23.sram_ctrl_max_throughput.2294730431	Aug 08 05:33:40 PM PDT 24	Aug 08 05:34:22 PM PDT 24	5160509821 ps
T11	/workspace/coverage/default/40.sram_ctrl_alert_test.4143616799	Aug 08 05:36:36 PM PDT 24	Aug 08 05:36:37 PM PDT 24	59958145 ps
T12	/workspace/coverage/default/12.sram_ctrl_mem_walk.654083731	Aug 08 05:32:34 PM PDT 24	Aug 08 05:36:53 PM PDT 24	3988742369 ps
T13	/workspace/coverage/default/16.sram_ctrl_bijection.3891098917	Aug 08 05:32:45 PM PDT 24	Aug 08 05:53:51 PM PDT 24	76042829784 ps
T30	/workspace/coverage/default/31.sram_ctrl_max_throughput.2195897079	Aug 08 05:34:46 PM PDT 24	Aug 08 05:36:34 PM PDT 24	1565324278 ps
T29	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1101458527	Aug 08 05:37:53 PM PDT 24	Aug 08 05:38:24 PM PDT 24	3695502471 ps
T68	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.941884827	Aug 08 05:36:22 PM PDT 24	Aug 08 05:36:31 PM PDT 24	247502303 ps
T34	/workspace/coverage/default/45.sram_ctrl_ram_cfg.2977921241	Aug 08 05:37:19 PM PDT 24	Aug 08 05:37:22 PM PDT 24	1404212977 ps
T20	/workspace/coverage/default/34.sram_ctrl_bijection.2105904916	Aug 08 05:35:15 PM PDT 24	Aug 08 06:15:41 PM PDT 24	552159838378 ps
T35	/workspace/coverage/default/22.sram_ctrl_ram_cfg.1128897472	Aug 08 05:33:31 PM PDT 24	Aug 08 05:33:35 PM PDT 24	1254165038 ps
T84	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.116963700	Aug 08 05:32:02 PM PDT 24	Aug 08 05:32:25 PM PDT 24	3236708596 ps
T31	/workspace/coverage/default/33.sram_ctrl_regwen.1034738694	Aug 08 05:35:14 PM PDT 24	Aug 08 05:48:46 PM PDT 24	70540174604 ps
T48	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.443720958	Aug 08 05:35:01 PM PDT 24	Aug 08 05:39:26 PM PDT 24	12014396294 ps
T49	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2075518672	Aug 08 05:37:58 PM PDT 24	Aug 08 05:40:26 PM PDT 24	1590927849 ps
T21	/workspace/coverage/default/31.sram_ctrl_bijection.2800461724	Aug 08 05:34:46 PM PDT 24	Aug 08 05:47:21 PM PDT 24	11283368027 ps
T50	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.106489548	Aug 08 05:32:34 PM PDT 24	Aug 08 05:35:04 PM PDT 24	2553339585 ps
T64	/workspace/coverage/default/49.sram_ctrl_smoke.520141811	Aug 08 05:38:02 PM PDT 24	Aug 08 05:38:36 PM PDT 24	1794160360 ps
T71	/workspace/coverage/default/33.sram_ctrl_partial_access.2540150596	Aug 08 05:35:02 PM PDT 24	Aug 08 05:35:08 PM PDT 24	700555287 ps
T5	/workspace/coverage/default/47.sram_ctrl_lc_escalation.3462029407	Aug 08 05:37:37 PM PDT 24	Aug 08 05:37:53 PM PDT 24	8524757395 ps
T32	/workspace/coverage/default/2.sram_ctrl_executable.3447246842	Aug 08 05:32:00 PM PDT 24	Aug 08 05:45:45 PM PDT 24	25844700724 ps
T72	/workspace/coverage/default/3.sram_ctrl_max_throughput.1548342825	Aug 08 05:32:04 PM PDT 24	Aug 08 05:32:22 PM PDT 24	6909907025 ps
T54	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3305268869	Aug 08 05:35:35 PM PDT 24	Aug 08 05:36:18 PM PDT 24	10515199710 ps
T73	/workspace/coverage/default/17.sram_ctrl_smoke.3270648165	Aug 08 05:32:50 PM PDT 24	Aug 08 05:33:05 PM PDT 24	914482406 ps
T74	/workspace/coverage/default/1.sram_ctrl_max_throughput.2634306316	Aug 08 05:32:04 PM PDT 24	Aug 08 05:34:02 PM PDT 24	1547247497 ps
T75	/workspace/coverage/default/48.sram_ctrl_smoke.2290145087	Aug 08 05:37:59 PM PDT 24	Aug 08 05:38:03 PM PDT 24	1393782141 ps
T144	/workspace/coverage/default/42.sram_ctrl_multiple_keys.2885214972	Aug 08 05:36:50 PM PDT 24	Aug 08 05:41:56 PM PDT 24	18482821203 ps
T55	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.930538569	Aug 08 05:32:22 PM PDT 24	Aug 08 05:35:08 PM PDT 24	10451178392 ps
T14	/workspace/coverage/default/42.sram_ctrl_alert_test.1130319825	Aug 08 05:36:52 PM PDT 24	Aug 08 05:36:53 PM PDT 24	28338429 ps
T76	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3334260922	Aug 08 05:34:22 PM PDT 24	Aug 08 05:36:29 PM PDT 24	6358032376 ps
T77	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2833475277	Aug 08 05:36:15 PM PDT 24	Aug 08 05:41:11 PM PDT 24	9582237540 ps
T36	/workspace/coverage/default/19.sram_ctrl_ram_cfg.4018713562	Aug 08 05:33:08 PM PDT 24	Aug 08 05:33:11 PM PDT 24	367386078 ps
T145	/workspace/coverage/default/2.sram_ctrl_bijection.835873150	Aug 08 05:32:04 PM PDT 24	Aug 08 06:12:40 PM PDT 24	216019548117 ps
T98	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4216800940	Aug 08 05:37:05 PM PDT 24	Aug 08 05:41:02 PM PDT 24	7818617351 ps
T146	/workspace/coverage/default/6.sram_ctrl_ram_cfg.4146598354	Aug 08 05:32:14 PM PDT 24	Aug 08 05:32:17 PM PDT 24	349507630 ps
T51	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2269106974	Aug 08 05:35:45 PM PDT 24	Aug 08 05:56:19 PM PDT 24	61879701651 ps
T147	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.35122082	Aug 08 05:32:13 PM PDT 24	Aug 08 05:33:45 PM PDT 24	3995465548 ps
T6	/workspace/coverage/default/1.sram_ctrl_stress_all.2442049982	Aug 08 05:31:59 PM PDT 24	Aug 08 06:14:04 PM PDT 24	199375698579 ps
T114	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3285052797	Aug 08 05:32:55 PM PDT 24	Aug 08 05:35:34 PM PDT 24	3040860819 ps
T148	/workspace/coverage/default/41.sram_ctrl_bijection.3872517357	Aug 08 05:36:35 PM PDT 24	Aug 08 05:57:28 PM PDT 24	72421158246 ps
T7	/workspace/coverage/default/7.sram_ctrl_lc_escalation.2206100450	Aug 08 05:32:14 PM PDT 24	Aug 08 05:32:44 PM PDT 24	4328067926 ps
T33	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1321200224	Aug 08 05:35:14 PM PDT 24	Aug 08 05:37:43 PM PDT 24	2180870043 ps
T149	/workspace/coverage/default/1.sram_ctrl_ram_cfg.1914337035	Aug 08 05:32:06 PM PDT 24	Aug 08 05:32:09 PM PDT 24	2412685446 ps
T23	/workspace/coverage/default/8.sram_ctrl_regwen.3033067087	Aug 08 05:32:13 PM PDT 24	Aug 08 05:55:00 PM PDT 24	68578873626 ps
T63	/workspace/coverage/default/10.sram_ctrl_mem_walk.3874560127	Aug 08 05:32:33 PM PDT 24	Aug 08 05:38:00 PM PDT 24	14279033136 ps
T22	/workspace/coverage/default/23.sram_ctrl_lc_escalation.291570617	Aug 08 05:33:38 PM PDT 24	Aug 08 05:34:51 PM PDT 24	11618435379 ps
T150	/workspace/coverage/default/7.sram_ctrl_partial_access.2530374919	Aug 08 05:32:14 PM PDT 24	Aug 08 05:32:54 PM PDT 24	1046305616 ps
T151	/workspace/coverage/default/15.sram_ctrl_bijection.3616959589	Aug 08 05:32:34 PM PDT 24	Aug 08 05:56:06 PM PDT 24	249957496755 ps
T87	/workspace/coverage/default/38.sram_ctrl_lc_escalation.909079131	Aug 08 05:36:05 PM PDT 24	Aug 08 05:37:00 PM PDT 24	8876672865 ps
T52	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2290803871	Aug 08 05:35:03 PM PDT 24	Aug 08 05:49:13 PM PDT 24	40182141581 ps
T152	/workspace/coverage/default/5.sram_ctrl_max_throughput.1781612224	Aug 08 05:32:10 PM PDT 24	Aug 08 05:33:00 PM PDT 24	3312793652 ps
T115	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3724142854	Aug 08 05:36:13 PM PDT 24	Aug 08 05:43:28 PM PDT 24	36716878197 ps
T88	/workspace/coverage/default/4.sram_ctrl_lc_escalation.1009472197	Aug 08 05:32:12 PM PDT 24	Aug 08 05:33:01 PM PDT 24	25109670490 ps
T116	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3640341892	Aug 08 05:37:59 PM PDT 24	Aug 08 05:43:23 PM PDT 24	20082726572 ps
T153	/workspace/coverage/default/35.sram_ctrl_max_throughput.1467381590	Aug 08 05:35:34 PM PDT 24	Aug 08 05:35:49 PM PDT 24	1440505416 ps
T138	/workspace/coverage/default/48.sram_ctrl_executable.255341346	Aug 08 05:38:00 PM PDT 24	Aug 08 05:55:51 PM PDT 24	6997350394 ps
T89	/workspace/coverage/default/42.sram_ctrl_lc_escalation.1176223878	Aug 08 05:36:50 PM PDT 24	Aug 08 05:38:35 PM PDT 24	15996922531 ps
T53	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3384058125	Aug 08 05:37:28 PM PDT 24	Aug 08 05:45:55 PM PDT 24	30060890073 ps
T117	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2093228063	Aug 08 05:36:33 PM PDT 24	Aug 08 05:40:47 PM PDT 24	16246299362 ps
T154	/workspace/coverage/default/42.sram_ctrl_smoke.2506549615	Aug 08 05:36:43 PM PDT 24	Aug 08 05:36:58 PM PDT 24	853225823 ps
T155	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.403795645	Aug 08 05:37:05 PM PDT 24	Aug 08 05:37:13 PM PDT 24	5584895082 ps
T102	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1120821746	Aug 08 05:36:13 PM PDT 24	Aug 08 05:45:26 PM PDT 24	9862775266 ps
T156	/workspace/coverage/default/49.sram_ctrl_partial_access.1653435594	Aug 08 05:38:10 PM PDT 24	Aug 08 05:40:21 PM PDT 24	1220284632 ps
T24	/workspace/coverage/default/32.sram_ctrl_regwen.411524682	Aug 08 05:34:54 PM PDT 24	Aug 08 05:44:27 PM PDT 24	159663478618 ps
T157	/workspace/coverage/default/18.sram_ctrl_lc_escalation.557520567	Aug 08 05:32:55 PM PDT 24	Aug 08 05:34:20 PM PDT 24	52354648980 ps
T158	/workspace/coverage/default/40.sram_ctrl_smoke.493620692	Aug 08 05:36:23 PM PDT 24	Aug 08 05:36:36 PM PDT 24	997296458 ps
T103	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.63726863	Aug 08 05:32:03 PM PDT 24	Aug 08 05:34:50 PM PDT 24	11455577462 ps
T159	/workspace/coverage/default/16.sram_ctrl_smoke.600306774	Aug 08 05:32:43 PM PDT 24	Aug 08 05:33:01 PM PDT 24	1710064856 ps
T160	/workspace/coverage/default/39.sram_ctrl_bijection.3285558592	Aug 08 05:36:14 PM PDT 24	Aug 08 05:47:33 PM PDT 24	10470572633 ps
T59	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3334178652	Aug 08 05:35:44 PM PDT 24	Aug 08 05:36:23 PM PDT 24	4742654637 ps
T161	/workspace/coverage/default/2.sram_ctrl_multiple_keys.718173637	Aug 08 05:32:02 PM PDT 24	Aug 08 05:40:57 PM PDT 24	89287783370 ps
T162	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3638977563	Aug 08 05:32:15 PM PDT 24	Aug 08 05:32:49 PM PDT 24	3012913538 ps
T163	/workspace/coverage/default/11.sram_ctrl_max_throughput.3425747705	Aug 08 05:32:21 PM PDT 24	Aug 08 05:34:04 PM PDT 24	3589438998 ps
T164	/workspace/coverage/default/5.sram_ctrl_mem_walk.1670860350	Aug 08 05:32:09 PM PDT 24	Aug 08 05:34:17 PM PDT 24	8222579538 ps
T25	/workspace/coverage/default/5.sram_ctrl_stress_all.2636745814	Aug 08 05:32:10 PM PDT 24	Aug 08 06:17:45 PM PDT 24	15026331429 ps
T118	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3366201935	Aug 08 05:37:21 PM PDT 24	Aug 08 05:42:02 PM PDT 24	12903954362 ps
T85	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.461205970	Aug 08 05:32:51 PM PDT 24	Aug 08 05:35:02 PM PDT 24	1582203462 ps
T26	/workspace/coverage/default/37.sram_ctrl_stress_all.3452742683	Aug 08 05:36:02 PM PDT 24	Aug 08 07:00:51 PM PDT 24	61496705148 ps
T104	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1856760125	Aug 08 05:37:37 PM PDT 24	Aug 08 05:53:06 PM PDT 24	18599529085 ps
T165	/workspace/coverage/default/25.sram_ctrl_executable.3632627028	Aug 08 05:33:49 PM PDT 24	Aug 08 05:48:45 PM PDT 24	6547316968 ps
T105	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1870862928	Aug 08 05:32:11 PM PDT 24	Aug 08 05:43:10 PM PDT 24	12568411597 ps
T139	/workspace/coverage/default/42.sram_ctrl_regwen.860645188	Aug 08 05:36:51 PM PDT 24	Aug 08 05:50:17 PM PDT 24	10287378258 ps
T166	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2256432081	Aug 08 05:32:34 PM PDT 24	Aug 08 05:37:46 PM PDT 24	4785337496 ps
T167	/workspace/coverage/default/19.sram_ctrl_mem_walk.3170359318	Aug 08 05:33:09 PM PDT 24	Aug 08 05:37:14 PM PDT 24	5800114267 ps
T168	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2777124451	Aug 08 05:37:29 PM PDT 24	Aug 08 05:37:57 PM PDT 24	2973953009 ps
T169	/workspace/coverage/default/27.sram_ctrl_mem_walk.246315572	Aug 08 05:34:11 PM PDT 24	Aug 08 05:36:17 PM PDT 24	5645189967 ps
T170	/workspace/coverage/default/15.sram_ctrl_multiple_keys.1453382234	Aug 08 05:32:51 PM PDT 24	Aug 08 06:01:18 PM PDT 24	49126114662 ps
T65	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2202083898	Aug 08 05:32:35 PM PDT 24	Aug 08 05:35:22 PM PDT 24	19579830078 ps
T171	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3085055404	Aug 08 05:36:53 PM PDT 24	Aug 08 05:42:18 PM PDT 24	15130790124 ps
T172	/workspace/coverage/default/19.sram_ctrl_multiple_keys.2880587592	Aug 08 05:32:56 PM PDT 24	Aug 08 05:57:55 PM PDT 24	99718830631 ps
T173	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1296291483	Aug 08 05:36:53 PM PDT 24	Aug 08 05:42:26 PM PDT 24	11937870950 ps
T174	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1707614227	Aug 08 05:32:35 PM PDT 24	Aug 08 05:32:51 PM PDT 24	1459074523 ps
T175	/workspace/coverage/default/37.sram_ctrl_partial_access.3095435035	Aug 08 05:35:45 PM PDT 24	Aug 08 05:36:08 PM PDT 24	10185907699 ps
T66	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1977632580	Aug 08 05:33:50 PM PDT 24	Aug 08 05:36:38 PM PDT 24	5234477283 ps
T142	/workspace/coverage/default/40.sram_ctrl_executable.1580549317	Aug 08 05:36:33 PM PDT 24	Aug 08 05:55:13 PM PDT 24	14161894300 ps
T176	/workspace/coverage/default/38.sram_ctrl_bijection.3770666246	Aug 08 05:35:58 PM PDT 24	Aug 08 05:59:16 PM PDT 24	60561301093 ps
T177	/workspace/coverage/default/8.sram_ctrl_smoke.967270057	Aug 08 05:32:16 PM PDT 24	Aug 08 05:32:33 PM PDT 24	3599110677 ps
T178	/workspace/coverage/default/24.sram_ctrl_lc_escalation.3285591998	Aug 08 05:33:45 PM PDT 24	Aug 08 05:34:32 PM PDT 24	30522018745 ps
T179	/workspace/coverage/default/32.sram_ctrl_executable.1274511683	Aug 08 05:34:56 PM PDT 24	Aug 08 05:36:22 PM PDT 24	15882784078 ps
T180	/workspace/coverage/default/6.sram_ctrl_partial_access.3801811777	Aug 08 05:32:11 PM PDT 24	Aug 08 05:33:29 PM PDT 24	807771907 ps
T181	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3884407549	Aug 08 05:32:17 PM PDT 24	Aug 08 05:33:54 PM PDT 24	10852004170 ps
T182	/workspace/coverage/default/28.sram_ctrl_ram_cfg.1525555329	Aug 08 05:34:22 PM PDT 24	Aug 08 05:34:26 PM PDT 24	852575018 ps
T15	/workspace/coverage/default/26.sram_ctrl_alert_test.936167264	Aug 08 05:34:00 PM PDT 24	Aug 08 05:34:00 PM PDT 24	35040691 ps
T183	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.207888059	Aug 08 05:33:49 PM PDT 24	Aug 08 05:33:58 PM PDT 24	683041139 ps
T184	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1147145035	Aug 08 05:32:07 PM PDT 24	Aug 08 05:32:52 PM PDT 24	1461798327 ps
T185	/workspace/coverage/default/14.sram_ctrl_max_throughput.4128995293	Aug 08 05:32:51 PM PDT 24	Aug 08 05:33:31 PM PDT 24	739804902 ps
T186	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.643538419	Aug 08 05:32:23 PM PDT 24	Aug 08 05:48:15 PM PDT 24	44264551103 ps
T187	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3925737185	Aug 08 05:37:47 PM PDT 24	Aug 08 05:38:56 PM PDT 24	4386163843 ps
T188	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2165896278	Aug 08 05:38:09 PM PDT 24	Aug 08 05:40:42 PM PDT 24	4382491904 ps
T189	/workspace/coverage/default/34.sram_ctrl_ram_cfg.3036370402	Aug 08 05:35:26 PM PDT 24	Aug 08 05:35:31 PM PDT 24	4810032545 ps
T27	/workspace/coverage/default/17.sram_ctrl_stress_all.1998497106	Aug 08 05:32:56 PM PDT 24	Aug 08 06:09:51 PM PDT 24	152183385043 ps
T190	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.4035880162	Aug 08 05:35:25 PM PDT 24	Aug 08 05:51:04 PM PDT 24	12352481008 ps
T191	/workspace/coverage/default/11.sram_ctrl_multiple_keys.488382348	Aug 08 05:32:23 PM PDT 24	Aug 08 06:01:54 PM PDT 24	29708775487 ps
T192	/workspace/coverage/default/26.sram_ctrl_max_throughput.1860653473	Aug 08 05:33:53 PM PDT 24	Aug 08 05:34:15 PM PDT 24	711818130 ps
T193	/workspace/coverage/default/16.sram_ctrl_multiple_keys.3785118682	Aug 08 05:32:50 PM PDT 24	Aug 08 05:43:24 PM PDT 24	17637633253 ps
T194	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3272791010	Aug 08 05:32:13 PM PDT 24	Aug 08 05:40:55 PM PDT 24	102453185329 ps
T16	/workspace/coverage/default/35.sram_ctrl_alert_test.3864249180	Aug 08 05:35:33 PM PDT 24	Aug 08 05:35:34 PM PDT 24	30315957 ps
T195	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2937056608	Aug 08 05:35:46 PM PDT 24	Aug 08 05:38:16 PM PDT 24	1628385555 ps
T196	/workspace/coverage/default/48.sram_ctrl_ram_cfg.1414137563	Aug 08 05:38:00 PM PDT 24	Aug 08 05:38:03 PM PDT 24	1353744456 ps
T140	/workspace/coverage/default/34.sram_ctrl_stress_all.3769819771	Aug 08 05:35:25 PM PDT 24	Aug 08 06:33:27 PM PDT 24	148176431392 ps
T28	/workspace/coverage/default/47.sram_ctrl_stress_all.583622657	Aug 08 05:37:48 PM PDT 24	Aug 08 06:10:36 PM PDT 24	48185062837 ps
T143	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3704317998	Aug 08 05:32:46 PM PDT 24	Aug 08 05:43:31 PM PDT 24	88446181130 ps
T197	/workspace/coverage/default/37.sram_ctrl_lc_escalation.3472486954	Aug 08 05:35:57 PM PDT 24	Aug 08 05:36:37 PM PDT 24	13797247061 ps
T198	/workspace/coverage/default/18.sram_ctrl_max_throughput.2445835895	Aug 08 05:32:56 PM PDT 24	Aug 08 05:33:07 PM PDT 24	1348738921 ps
T86	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3387038334	Aug 08 05:35:24 PM PDT 24	Aug 08 05:35:33 PM PDT 24	259346319 ps
T67	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.308924695	Aug 08 05:37:19 PM PDT 24	Aug 08 05:40:20 PM PDT 24	20401591132 ps
T60	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3654323294	Aug 08 05:33:53 PM PDT 24	Aug 08 05:34:42 PM PDT 24	1580955765 ps
T120	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1785127289	Aug 08 05:37:37 PM PDT 24	Aug 08 05:37:57 PM PDT 24	657441194 ps
T199	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1503074261	Aug 08 05:37:59 PM PDT 24	Aug 08 05:43:07 PM PDT 24	4514496071 ps
T200	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.578487832	Aug 08 05:32:11 PM PDT 24	Aug 08 05:32:30 PM PDT 24	836662613 ps
T201	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3025991793	Aug 08 05:38:00 PM PDT 24	Aug 08 05:44:54 PM PDT 24	16747195348 ps
T202	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1058630818	Aug 08 05:32:04 PM PDT 24	Aug 08 05:56:42 PM PDT 24	30527684923 ps
T203	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2259165278	Aug 08 05:35:36 PM PDT 24	Aug 08 05:51:55 PM PDT 24	40752427453 ps
T204	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2943990772	Aug 08 05:33:21 PM PDT 24	Aug 08 05:35:16 PM PDT 24	1544298991 ps
T205	/workspace/coverage/default/9.sram_ctrl_executable.2541502358	Aug 08 05:32:27 PM PDT 24	Aug 08 05:34:23 PM PDT 24	4583445853 ps
T69	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.49565676	Aug 08 05:35:35 PM PDT 24	Aug 08 05:37:01 PM PDT 24	5807441754 ps
T206	/workspace/coverage/default/36.sram_ctrl_lc_escalation.4159973368	Aug 08 05:35:46 PM PDT 24	Aug 08 05:36:17 PM PDT 24	5041030547 ps
T207	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3951732693	Aug 08 05:33:08 PM PDT 24	Aug 08 05:33:16 PM PDT 24	195787235 ps
T208	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1767604101	Aug 08 05:32:12 PM PDT 24	Aug 08 05:38:24 PM PDT 24	12185584139 ps
T209	/workspace/coverage/default/24.sram_ctrl_ram_cfg.1488023398	Aug 08 05:33:41 PM PDT 24	Aug 08 05:33:44 PM PDT 24	1686283421 ps
T210	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2450968399	Aug 08 05:32:13 PM PDT 24	Aug 08 05:37:14 PM PDT 24	4450870243 ps
T211	/workspace/coverage/default/31.sram_ctrl_regwen.3477652697	Aug 08 05:34:46 PM PDT 24	Aug 08 05:43:10 PM PDT 24	4697947259 ps
T212	/workspace/coverage/default/21.sram_ctrl_executable.3338471179	Aug 08 05:33:18 PM PDT 24	Aug 08 05:41:45 PM PDT 24	60363387966 ps
T213	/workspace/coverage/default/32.sram_ctrl_lc_escalation.3827024287	Aug 08 05:34:55 PM PDT 24	Aug 08 05:36:05 PM PDT 24	25668379864 ps
T214	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.467655095	Aug 08 05:35:35 PM PDT 24	Aug 08 05:39:39 PM PDT 24	4974947999 ps
T215	/workspace/coverage/default/12.sram_ctrl_multiple_keys.2492900663	Aug 08 05:32:26 PM PDT 24	Aug 08 05:52:59 PM PDT 24	16457519637 ps
T141	/workspace/coverage/default/26.sram_ctrl_stress_all.4069253246	Aug 08 05:33:59 PM PDT 24	Aug 08 06:31:11 PM PDT 24	50393226044 ps
T216	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1720360446	Aug 08 05:32:09 PM PDT 24	Aug 08 05:32:28 PM PDT 24	725852354 ps
T217	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1817192555	Aug 08 05:32:13 PM PDT 24	Aug 08 05:36:10 PM PDT 24	37246919821 ps
T218	/workspace/coverage/default/9.sram_ctrl_multiple_keys.3725760175	Aug 08 05:32:22 PM PDT 24	Aug 08 05:35:05 PM PDT 24	2076597678 ps
T219	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.945335817	Aug 08 05:32:35 PM PDT 24	Aug 08 05:33:46 PM PDT 24	979457062 ps
T220	/workspace/coverage/default/38.sram_ctrl_mem_walk.3220379406	Aug 08 05:36:03 PM PDT 24	Aug 08 05:38:37 PM PDT 24	10513987865 ps
T221	/workspace/coverage/default/21.sram_ctrl_partial_access.2277954964	Aug 08 05:33:21 PM PDT 24	Aug 08 05:33:40 PM PDT 24	3337628612 ps
T222	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2647581848	Aug 08 05:35:24 PM PDT 24	Aug 08 05:41:28 PM PDT 24	28383510320 ps
T223	/workspace/coverage/default/1.sram_ctrl_smoke.2494686823	Aug 08 05:32:01 PM PDT 24	Aug 08 05:32:15 PM PDT 24	4971353952 ps
T224	/workspace/coverage/default/37.sram_ctrl_alert_test.2202563519	Aug 08 05:36:04 PM PDT 24	Aug 08 05:36:04 PM PDT 24	46543192 ps
T61	/workspace/coverage/default/29.sram_ctrl_mem_walk.402680041	Aug 08 05:34:38 PM PDT 24	Aug 08 05:37:35 PM PDT 24	12504616423 ps
T225	/workspace/coverage/default/21.sram_ctrl_ram_cfg.3341711424	Aug 08 05:33:22 PM PDT 24	Aug 08 05:33:25 PM PDT 24	655206773 ps
T226	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.679769979	Aug 08 05:32:23 PM PDT 24	Aug 08 05:38:24 PM PDT 24	6787088764 ps
T227	/workspace/coverage/default/13.sram_ctrl_stress_all.1397875486	Aug 08 05:32:36 PM PDT 24	Aug 08 06:44:55 PM PDT 24	240344310374 ps
T228	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3089057873	Aug 08 05:32:32 PM PDT 24	Aug 08 05:32:50 PM PDT 24	714801116 ps
T229	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.135529553	Aug 08 05:32:56 PM PDT 24	Aug 08 05:39:18 PM PDT 24	26581513359 ps
T230	/workspace/coverage/default/7.sram_ctrl_executable.2071676166	Aug 08 05:32:14 PM PDT 24	Aug 08 05:51:18 PM PDT 24	17505859532 ps
T231	/workspace/coverage/default/37.sram_ctrl_multiple_keys.1361292757	Aug 08 05:35:45 PM PDT 24	Aug 08 05:43:25 PM PDT 24	121033146513 ps
T232	/workspace/coverage/default/13.sram_ctrl_partial_access.100417607	Aug 08 05:32:46 PM PDT 24	Aug 08 05:33:07 PM PDT 24	2769410792 ps
T233	/workspace/coverage/default/22.sram_ctrl_lc_escalation.3294720533	Aug 08 05:33:19 PM PDT 24	Aug 08 05:34:45 PM PDT 24	64652606261 ps
T234	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2222062253	Aug 08 05:33:51 PM PDT 24	Aug 08 05:39:08 PM PDT 24	12450556295 ps
T235	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2814413663	Aug 08 05:33:33 PM PDT 24	Aug 08 05:33:39 PM PDT 24	61759626 ps
T236	/workspace/coverage/default/47.sram_ctrl_regwen.2283220969	Aug 08 05:37:47 PM PDT 24	Aug 08 05:50:39 PM PDT 24	28633773568 ps
T237	/workspace/coverage/default/43.sram_ctrl_executable.848913510	Aug 08 05:37:00 PM PDT 24	Aug 08 05:53:07 PM PDT 24	38195310252 ps
T238	/workspace/coverage/default/9.sram_ctrl_bijection.1498979453	Aug 08 05:32:22 PM PDT 24	Aug 08 05:55:41 PM PDT 24	77921560766 ps
T239	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3870119916	Aug 08 05:37:37 PM PDT 24	Aug 08 05:41:50 PM PDT 24	9660062132 ps
T240	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1538906925	Aug 08 05:37:10 PM PDT 24	Aug 08 05:41:57 PM PDT 24	11321993693 ps
T241	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.906170606	Aug 08 05:35:34 PM PDT 24	Aug 08 05:37:37 PM PDT 24	832287783 ps
T242	/workspace/coverage/default/22.sram_ctrl_mem_walk.3270031411	Aug 08 05:33:32 PM PDT 24	Aug 08 05:36:11 PM PDT 24	6907185522 ps
T243	/workspace/coverage/default/18.sram_ctrl_multiple_keys.3153909924	Aug 08 05:32:55 PM PDT 24	Aug 08 05:39:16 PM PDT 24	34860084261 ps
T244	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1869306003	Aug 08 05:32:32 PM PDT 24	Aug 08 05:35:39 PM PDT 24	3092718481 ps
T245	/workspace/coverage/default/21.sram_ctrl_smoke.2622871302	Aug 08 05:33:22 PM PDT 24	Aug 08 05:35:48 PM PDT 24	470473621 ps
T246	/workspace/coverage/default/38.sram_ctrl_max_throughput.3504143816	Aug 08 05:36:12 PM PDT 24	Aug 08 05:36:27 PM PDT 24	6912829063 ps
T247	/workspace/coverage/default/21.sram_ctrl_regwen.3600844245	Aug 08 05:33:19 PM PDT 24	Aug 08 05:49:12 PM PDT 24	3226216954 ps
T248	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2788767948	Aug 08 05:32:10 PM PDT 24	Aug 08 05:32:51 PM PDT 24	1607323786 ps
T249	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1411914822	Aug 08 05:32:24 PM PDT 24	Aug 08 05:36:57 PM PDT 24	5557220617 ps
T250	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1488440282	Aug 08 05:32:34 PM PDT 24	Aug 08 05:35:00 PM PDT 24	8953376635 ps
T251	/workspace/coverage/default/15.sram_ctrl_mem_walk.987154690	Aug 08 05:32:50 PM PDT 24	Aug 08 05:37:47 PM PDT 24	7296862079 ps
T252	/workspace/coverage/default/25.sram_ctrl_bijection.2422455918	Aug 08 05:33:39 PM PDT 24	Aug 08 05:46:33 PM PDT 24	33473908834 ps
T253	/workspace/coverage/default/25.sram_ctrl_ram_cfg.2544042783	Aug 08 05:33:54 PM PDT 24	Aug 08 05:33:57 PM PDT 24	684830188 ps
T254	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2496735244	Aug 08 05:34:21 PM PDT 24	Aug 08 05:40:26 PM PDT 24	12459581609 ps
T255	/workspace/coverage/default/6.sram_ctrl_alert_test.4172588235	Aug 08 05:32:15 PM PDT 24	Aug 08 05:32:16 PM PDT 24	63425944 ps
T256	/workspace/coverage/default/47.sram_ctrl_ram_cfg.3928637751	Aug 08 05:37:47 PM PDT 24	Aug 08 05:37:51 PM PDT 24	1349985816 ps
T257	/workspace/coverage/default/38.sram_ctrl_multiple_keys.1624902190	Aug 08 05:35:56 PM PDT 24	Aug 08 05:50:14 PM PDT 24	7377057544 ps
T258	/workspace/coverage/default/15.sram_ctrl_smoke.2989963943	Aug 08 05:32:50 PM PDT 24	Aug 08 05:32:56 PM PDT 24	2585980321 ps
T259	/workspace/coverage/default/23.sram_ctrl_regwen.1279634424	Aug 08 05:33:30 PM PDT 24	Aug 08 05:39:43 PM PDT 24	5659236422 ps
T121	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3806128671	Aug 08 05:32:04 PM PDT 24	Aug 08 05:32:21 PM PDT 24	671005674 ps
T260	/workspace/coverage/default/26.sram_ctrl_mem_walk.2924805743	Aug 08 05:33:58 PM PDT 24	Aug 08 05:36:27 PM PDT 24	7307701128 ps
T261	/workspace/coverage/default/23.sram_ctrl_executable.1626092965	Aug 08 05:33:31 PM PDT 24	Aug 08 05:42:30 PM PDT 24	11886656137 ps
T262	/workspace/coverage/default/42.sram_ctrl_max_throughput.2183284812	Aug 08 05:36:53 PM PDT 24	Aug 08 05:37:19 PM PDT 24	4160451558 ps
T263	/workspace/coverage/default/18.sram_ctrl_bijection.922680056	Aug 08 05:32:54 PM PDT 24	Aug 08 06:05:43 PM PDT 24	175094989584 ps
T264	/workspace/coverage/default/20.sram_ctrl_alert_test.2247968301	Aug 08 05:33:19 PM PDT 24	Aug 08 05:33:20 PM PDT 24	13638934 ps
T265	/workspace/coverage/default/32.sram_ctrl_max_throughput.3156165296	Aug 08 05:34:58 PM PDT 24	Aug 08 05:35:06 PM PDT 24	2501056649 ps
T266	/workspace/coverage/default/17.sram_ctrl_executable.3748186001	Aug 08 05:32:55 PM PDT 24	Aug 08 05:45:32 PM PDT 24	39797364413 ps
T267	/workspace/coverage/default/1.sram_ctrl_bijection.404242114	Aug 08 05:32:05 PM PDT 24	Aug 08 05:52:43 PM PDT 24	239902136925 ps
T62	/workspace/coverage/default/34.sram_ctrl_mem_walk.962882417	Aug 08 05:35:24 PM PDT 24	Aug 08 05:38:26 PM PDT 24	21114177917 ps
T70	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2645411254	Aug 08 05:33:08 PM PDT 24	Aug 08 05:35:58 PM PDT 24	5626053019 ps
T56	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3259667864	Aug 08 05:34:57 PM PDT 24	Aug 08 05:35:28 PM PDT 24	1033452131 ps
T268	/workspace/coverage/default/33.sram_ctrl_max_throughput.183898664	Aug 08 05:35:03 PM PDT 24	Aug 08 05:37:22 PM PDT 24	3172642917 ps
T269	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2999646338	Aug 08 05:33:14 PM PDT 24	Aug 08 05:39:46 PM PDT 24	16711825919 ps
T270	/workspace/coverage/default/9.sram_ctrl_regwen.2818303121	Aug 08 05:32:31 PM PDT 24	Aug 08 05:45:49 PM PDT 24	3209564189 ps
T271	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2952072599	Aug 08 05:32:45 PM PDT 24	Aug 08 05:33:05 PM PDT 24	1451150151 ps
T272	/workspace/coverage/default/9.sram_ctrl_ram_cfg.685851103	Aug 08 05:32:23 PM PDT 24	Aug 08 05:32:26 PM PDT 24	349602030 ps
T273	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3398563286	Aug 08 05:32:45 PM PDT 24	Aug 08 05:56:26 PM PDT 24	30745395872 ps
T274	/workspace/coverage/default/19.sram_ctrl_stress_all.3383732290	Aug 08 05:33:14 PM PDT 24	Aug 08 06:27:28 PM PDT 24	178391856793 ps
T275	/workspace/coverage/default/4.sram_ctrl_regwen.2414948843	Aug 08 05:32:10 PM PDT 24	Aug 08 05:40:28 PM PDT 24	36305858307 ps
T276	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.459918498	Aug 08 05:32:44 PM PDT 24	Aug 08 05:51:49 PM PDT 24	31491006303 ps
T277	/workspace/coverage/default/31.sram_ctrl_smoke.3421201659	Aug 08 05:34:46 PM PDT 24	Aug 08 05:36:51 PM PDT 24	903202218 ps
T278	/workspace/coverage/default/14.sram_ctrl_executable.3798846077	Aug 08 05:32:36 PM PDT 24	Aug 08 05:43:03 PM PDT 24	22003649394 ps
T279	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2084380243	Aug 08 05:32:14 PM PDT 24	Aug 08 05:47:50 PM PDT 24	41436865528 ps
T280	/workspace/coverage/default/24.sram_ctrl_alert_test.3351226065	Aug 08 05:33:40 PM PDT 24	Aug 08 05:33:40 PM PDT 24	26408704 ps
T281	/workspace/coverage/default/34.sram_ctrl_alert_test.2601250211	Aug 08 05:35:25 PM PDT 24	Aug 08 05:35:26 PM PDT 24	44651957 ps
T282	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3334751907	Aug 08 05:32:04 PM PDT 24	Aug 08 05:32:52 PM PDT 24	3075442160 ps
T283	/workspace/coverage/default/37.sram_ctrl_mem_walk.3278526686	Aug 08 05:35:55 PM PDT 24	Aug 08 05:39:02 PM PDT 24	44879155437 ps
T284	/workspace/coverage/default/49.sram_ctrl_multiple_keys.2907192817	Aug 08 05:38:00 PM PDT 24	Aug 08 05:43:42 PM PDT 24	12633837826 ps
T285	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2264959259	Aug 08 05:35:44 PM PDT 24	Aug 08 05:39:31 PM PDT 24	12960724772 ps
T286	/workspace/coverage/default/44.sram_ctrl_partial_access.467316180	Aug 08 05:37:10 PM PDT 24	Aug 08 05:37:31 PM PDT 24	928017395 ps
T287	/workspace/coverage/default/2.sram_ctrl_partial_access.2044578348	Aug 08 05:32:03 PM PDT 24	Aug 08 05:33:30 PM PDT 24	4718451852 ps
T57	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2254994863	Aug 08 05:33:42 PM PDT 24	Aug 08 05:34:21 PM PDT 24	5252841248 ps
T288	/workspace/coverage/default/6.sram_ctrl_max_throughput.2368677882	Aug 08 05:32:09 PM PDT 24	Aug 08 05:32:17 PM PDT 24	3362435075 ps
T289	/workspace/coverage/default/3.sram_ctrl_mem_walk.3928850128	Aug 08 05:32:14 PM PDT 24	Aug 08 05:35:37 PM PDT 24	147620326735 ps
T17	/workspace/coverage/default/1.sram_ctrl_sec_cm.514734231	Aug 08 05:32:03 PM PDT 24	Aug 08 05:32:06 PM PDT 24	754705272 ps
T39	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3270706313	Aug 08 05:32:24 PM PDT 24	Aug 08 05:34:56 PM PDT 24	43821350049 ps
T40	/workspace/coverage/default/14.sram_ctrl_stress_all.897602989	Aug 08 05:32:51 PM PDT 24	Aug 08 06:36:25 PM PDT 24	264620871706 ps
T41	/workspace/coverage/default/41.sram_ctrl_smoke.461139985	Aug 08 05:36:33 PM PDT 24	Aug 08 05:36:54 PM PDT 24	7085849882 ps
T42	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.403380244	Aug 08 05:33:20 PM PDT 24	Aug 08 05:37:31 PM PDT 24	17594013015 ps
T43	/workspace/coverage/default/19.sram_ctrl_partial_access.2905100375	Aug 08 05:33:09 PM PDT 24	Aug 08 05:33:15 PM PDT 24	410816732 ps
T44	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.99178938	Aug 08 05:32:50 PM PDT 24	Aug 08 05:38:37 PM PDT 24	34386329313 ps
T45	/workspace/coverage/default/9.sram_ctrl_mem_walk.2432886147	Aug 08 05:32:22 PM PDT 24	Aug 08 05:37:41 PM PDT 24	14405837217 ps
T46	/workspace/coverage/default/38.sram_ctrl_stress_all.2606256284	Aug 08 05:36:03 PM PDT 24	Aug 08 06:47:11 PM PDT 24	251164795396 ps
T47	/workspace/coverage/default/7.sram_ctrl_max_throughput.2407868236	Aug 08 05:32:15 PM PDT 24	Aug 08 05:32:22 PM PDT 24	2139562538 ps
T290	/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4129872786	Aug 08 05:37:59 PM PDT 24	Aug 08 06:06:51 PM PDT 24	78871696748 ps
T291	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2458891287	Aug 08 05:37:11 PM PDT 24	Aug 08 05:55:49 PM PDT 24	49534332318 ps
T292	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.2695057271	Aug 08 05:33:40 PM PDT 24	Aug 08 05:39:53 PM PDT 24	9719185261 ps
T293	/workspace/coverage/default/48.sram_ctrl_stress_all.1768598952	Aug 08 05:38:00 PM PDT 24	Aug 08 07:19:54 PM PDT 24	240471834472 ps
T294	/workspace/coverage/default/28.sram_ctrl_partial_access.2498374721	Aug 08 05:34:10 PM PDT 24	Aug 08 05:34:16 PM PDT 24	720843547 ps
T295	/workspace/coverage/default/30.sram_ctrl_stress_all.2484033945	Aug 08 05:34:45 PM PDT 24	Aug 08 06:10:04 PM PDT 24	65671694212 ps
T296	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2650771803	Aug 08 05:32:23 PM PDT 24	Aug 08 05:34:35 PM PDT 24	1592057017 ps
T297	/workspace/coverage/default/39.sram_ctrl_regwen.3609203438	Aug 08 05:36:13 PM PDT 24	Aug 08 05:52:12 PM PDT 24	12809763632 ps