Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	137083583	1			T1	73		T2	11414		T3	4614
triple_byte_access	2891385	1			T1	86		T2	228		T3	104
halfword_access	4433742	1			T1	109		T2	354		T3	147
byte_access	6207404	1			T1	137		T2	465		T3	208
zero_access	1874982	1			T1	26		T2	126		T3	43

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76088777

1

T1

243

T2

6253

T3

2536

auto[1]

76402319

1

T1

188

T2

6334

T3

2580

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	68244363	1			T1	39		T2	5666		T3	2291
auto[0]	triple_byte_access	1378558	1			T1	49		T2	124		T3	53
auto[0]	halfword_access	2167080	1			T1	59		T2	175		T3	74
auto[0]	byte_access	3180422	1			T1	81		T2	223		T3	97
auto[0]	zero_access	1118354	1			T1	15		T2	65		T3	21
auto[1]	word_access	68839220	1			T1	34		T2	5748		T3	2323
auto[1]	triple_byte_access	1512827	1			T1	37		T2	104		T3	51
auto[1]	halfword_access	2266662	1			T1	50		T2	179		T3	73
auto[1]	byte_access	3026982	1			T1	56		T2	242		T3	111
auto[1]	zero_access	756628	1			T1	11		T2	61		T3	22