| T788 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1285949491 |
|
|
Aug 08 05:32:30 PM PDT 24 |
Aug 08 05:32:57 PM PDT 24 |
790845775 ps |
| T789 |
/workspace/coverage/default/32.sram_ctrl_bijection.3569391117 |
|
|
Aug 08 05:34:55 PM PDT 24 |
Aug 08 06:12:54 PM PDT 24 |
313549628017 ps |
| T790 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1175577266 |
|
|
Aug 08 05:38:00 PM PDT 24 |
Aug 08 05:39:53 PM PDT 24 |
7657523543 ps |
| T791 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1478604803 |
|
|
Aug 08 05:34:22 PM PDT 24 |
Aug 08 05:39:28 PM PDT 24 |
18671152791 ps |
| T792 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.427184974 |
|
|
Aug 08 05:35:03 PM PDT 24 |
Aug 08 05:40:18 PM PDT 24 |
23205085434 ps |
| T793 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2782240047 |
|
|
Aug 08 05:36:35 PM PDT 24 |
Aug 08 05:37:12 PM PDT 24 |
1342326661 ps |
| T794 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1720819270 |
|
|
Aug 08 05:32:22 PM PDT 24 |
Aug 08 06:15:09 PM PDT 24 |
77157574475 ps |
| T795 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.4073165231 |
|
|
Aug 08 05:32:01 PM PDT 24 |
Aug 08 05:34:34 PM PDT 24 |
5379805752 ps |
| T796 |
/workspace/coverage/default/47.sram_ctrl_bijection.2959072391 |
|
|
Aug 08 05:37:37 PM PDT 24 |
Aug 08 06:13:19 PM PDT 24 |
63536593636 ps |
| T797 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3976426088 |
|
|
Aug 08 05:32:11 PM PDT 24 |
Aug 08 05:32:15 PM PDT 24 |
6722818664 ps |
| T798 |
/workspace/coverage/default/46.sram_ctrl_alert_test.134707117 |
|
|
Aug 08 05:37:38 PM PDT 24 |
Aug 08 05:37:39 PM PDT 24 |
19525902 ps |
| T799 |
/workspace/coverage/default/44.sram_ctrl_executable.3988892387 |
|
|
Aug 08 05:37:13 PM PDT 24 |
Aug 08 05:42:32 PM PDT 24 |
22907017294 ps |
| T800 |
/workspace/coverage/default/3.sram_ctrl_alert_test.635083420 |
|
|
Aug 08 05:32:10 PM PDT 24 |
Aug 08 05:32:11 PM PDT 24 |
81672974 ps |
| T801 |
/workspace/coverage/default/10.sram_ctrl_alert_test.151514933 |
|
|
Aug 08 05:32:22 PM PDT 24 |
Aug 08 05:32:22 PM PDT 24 |
26090004 ps |
| T802 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1584009451 |
|
|
Aug 08 05:37:01 PM PDT 24 |
Aug 08 05:46:36 PM PDT 24 |
32699321290 ps |
| T803 |
/workspace/coverage/default/10.sram_ctrl_regwen.3583383881 |
|
|
Aug 08 05:32:26 PM PDT 24 |
Aug 08 05:46:14 PM PDT 24 |
37084293981 ps |
| T804 |
/workspace/coverage/default/46.sram_ctrl_bijection.2104248352 |
|
|
Aug 08 05:37:19 PM PDT 24 |
Aug 08 05:51:54 PM PDT 24 |
12387061130 ps |
| T805 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.367460029 |
|
|
Aug 08 05:33:30 PM PDT 24 |
Aug 08 05:33:34 PM PDT 24 |
1065521551 ps |
| T806 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3287237912 |
|
|
Aug 08 05:33:40 PM PDT 24 |
Aug 08 06:20:19 PM PDT 24 |
107853620426 ps |
| T807 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1599300599 |
|
|
Aug 08 05:32:08 PM PDT 24 |
Aug 08 05:45:31 PM PDT 24 |
21997843911 ps |
| T808 |
/workspace/coverage/default/27.sram_ctrl_alert_test.543833388 |
|
|
Aug 08 05:34:10 PM PDT 24 |
Aug 08 05:34:11 PM PDT 24 |
25174547 ps |
| T809 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2712116943 |
|
|
Aug 08 05:35:04 PM PDT 24 |
Aug 08 05:36:32 PM PDT 24 |
14407725361 ps |
| T810 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3318903467 |
|
|
Aug 08 05:37:29 PM PDT 24 |
Aug 08 05:37:45 PM PDT 24 |
2241744092 ps |
| T811 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.598456620 |
|
|
Aug 08 05:32:25 PM PDT 24 |
Aug 08 05:49:56 PM PDT 24 |
48520467115 ps |
| T812 |
/workspace/coverage/default/6.sram_ctrl_bijection.390171121 |
|
|
Aug 08 05:32:08 PM PDT 24 |
Aug 08 06:06:19 PM PDT 24 |
57208895453 ps |
| T813 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2547811232 |
|
|
Aug 08 05:34:46 PM PDT 24 |
Aug 08 05:37:41 PM PDT 24 |
10370220008 ps |
| T814 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2731255789 |
|
|
Aug 08 05:32:26 PM PDT 24 |
Aug 08 05:32:35 PM PDT 24 |
692955044 ps |
| T815 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.4208805444 |
|
|
Aug 08 05:33:31 PM PDT 24 |
Aug 08 05:47:15 PM PDT 24 |
16929467527 ps |
| T816 |
/workspace/coverage/default/5.sram_ctrl_alert_test.4053902229 |
|
|
Aug 08 05:32:13 PM PDT 24 |
Aug 08 05:32:13 PM PDT 24 |
14721695 ps |
| T817 |
/workspace/coverage/default/38.sram_ctrl_executable.1281829439 |
|
|
Aug 08 05:36:05 PM PDT 24 |
Aug 08 05:38:46 PM PDT 24 |
1171767263 ps |
| T818 |
/workspace/coverage/default/49.sram_ctrl_bijection.4226145903 |
|
|
Aug 08 05:37:59 PM PDT 24 |
Aug 08 05:47:07 PM PDT 24 |
105917606882 ps |
| T819 |
/workspace/coverage/default/5.sram_ctrl_bijection.1467654321 |
|
|
Aug 08 05:32:08 PM PDT 24 |
Aug 08 05:51:22 PM PDT 24 |
90985539082 ps |
| T820 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1739871180 |
|
|
Aug 08 05:34:46 PM PDT 24 |
Aug 08 05:36:02 PM PDT 24 |
842437942 ps |
| T821 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1464406223 |
|
|
Aug 08 05:32:46 PM PDT 24 |
Aug 08 05:51:10 PM PDT 24 |
19545621625 ps |
| T822 |
/workspace/coverage/default/10.sram_ctrl_smoke.478007940 |
|
|
Aug 08 05:32:30 PM PDT 24 |
Aug 08 05:32:34 PM PDT 24 |
739768376 ps |
| T823 |
/workspace/coverage/default/45.sram_ctrl_regwen.1996167233 |
|
|
Aug 08 05:37:18 PM PDT 24 |
Aug 08 05:50:31 PM PDT 24 |
14769726312 ps |
| T824 |
/workspace/coverage/default/1.sram_ctrl_alert_test.614390561 |
|
|
Aug 08 05:32:06 PM PDT 24 |
Aug 08 05:32:07 PM PDT 24 |
17855375 ps |
| T825 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1317989201 |
|
|
Aug 08 05:35:45 PM PDT 24 |
Aug 08 05:41:59 PM PDT 24 |
7241991919 ps |
| T826 |
/workspace/coverage/default/35.sram_ctrl_stress_all.441843102 |
|
|
Aug 08 05:35:34 PM PDT 24 |
Aug 08 06:33:44 PM PDT 24 |
131689802371 ps |
| T827 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1266777270 |
|
|
Aug 08 05:37:20 PM PDT 24 |
Aug 08 05:38:23 PM PDT 24 |
36286564975 ps |
| T828 |
/workspace/coverage/default/37.sram_ctrl_executable.2100592299 |
|
|
Aug 08 05:35:56 PM PDT 24 |
Aug 08 05:43:39 PM PDT 24 |
17582751917 ps |
| T829 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2655421012 |
|
|
Aug 08 05:32:11 PM PDT 24 |
Aug 08 05:36:19 PM PDT 24 |
4696717290 ps |
| T830 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.822957248 |
|
|
Aug 08 05:33:39 PM PDT 24 |
Aug 08 05:37:45 PM PDT 24 |
5513690685 ps |
| T831 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2126004639 |
|
|
Aug 08 05:32:08 PM PDT 24 |
Aug 08 05:32:25 PM PDT 24 |
1081200462 ps |
| T832 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.77023891 |
|
|
Aug 08 05:35:34 PM PDT 24 |
Aug 08 05:37:40 PM PDT 24 |
2197302227 ps |
| T833 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2760467177 |
|
|
Aug 08 05:35:25 PM PDT 24 |
Aug 08 05:40:08 PM PDT 24 |
19644310593 ps |
| T834 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.2790737504 |
|
|
Aug 08 05:34:00 PM PDT 24 |
Aug 08 05:35:07 PM PDT 24 |
23520737332 ps |
| T835 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2287464925 |
|
|
Aug 08 05:32:10 PM PDT 24 |
Aug 08 05:32:57 PM PDT 24 |
1504817564 ps |
| T836 |
/workspace/coverage/default/45.sram_ctrl_smoke.4128605534 |
|
|
Aug 08 05:37:13 PM PDT 24 |
Aug 08 05:37:38 PM PDT 24 |
6647570642 ps |
| T107 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.926160617 |
|
|
Aug 08 05:32:46 PM PDT 24 |
Aug 08 05:35:22 PM PDT 24 |
5570471249 ps |
| T837 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1324291222 |
|
|
Aug 08 05:35:24 PM PDT 24 |
Aug 08 05:35:55 PM PDT 24 |
2581806443 ps |
| T838 |
/workspace/coverage/default/21.sram_ctrl_alert_test.3465153999 |
|
|
Aug 08 05:33:28 PM PDT 24 |
Aug 08 05:33:29 PM PDT 24 |
22421617 ps |
| T839 |
/workspace/coverage/default/19.sram_ctrl_regwen.2633201169 |
|
|
Aug 08 05:33:08 PM PDT 24 |
Aug 08 05:37:16 PM PDT 24 |
8502059872 ps |
| T840 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3877977354 |
|
|
Aug 08 05:36:44 PM PDT 24 |
Aug 08 05:36:47 PM PDT 24 |
361789297 ps |
| T841 |
/workspace/coverage/default/2.sram_ctrl_alert_test.505336819 |
|
|
Aug 08 05:32:08 PM PDT 24 |
Aug 08 05:32:09 PM PDT 24 |
13092795 ps |
| T842 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.484224251 |
|
|
Aug 08 05:32:00 PM PDT 24 |
Aug 08 05:35:39 PM PDT 24 |
3459485918 ps |
| T843 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.421905344 |
|
|
Aug 08 05:32:12 PM PDT 24 |
Aug 08 05:35:16 PM PDT 24 |
10896825688 ps |
| T844 |
/workspace/coverage/default/10.sram_ctrl_stress_all.3807715409 |
|
|
Aug 08 05:32:25 PM PDT 24 |
Aug 08 06:19:39 PM PDT 24 |
56871805276 ps |
| T845 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.164582800 |
|
|
Aug 08 05:35:35 PM PDT 24 |
Aug 08 05:35:39 PM PDT 24 |
867089076 ps |
| T846 |
/workspace/coverage/default/6.sram_ctrl_regwen.4230941314 |
|
|
Aug 08 05:32:14 PM PDT 24 |
Aug 08 05:51:09 PM PDT 24 |
4010843189 ps |
| T847 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3776290657 |
|
|
Aug 08 05:37:29 PM PDT 24 |
Aug 08 05:37:33 PM PDT 24 |
1211121125 ps |
| T848 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3177114610 |
|
|
Aug 08 05:35:45 PM PDT 24 |
Aug 08 05:38:48 PM PDT 24 |
25919759078 ps |
| T849 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4053275294 |
|
|
Aug 08 05:32:13 PM PDT 24 |
Aug 08 05:32:17 PM PDT 24 |
1303894563 ps |
| T850 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2472607756 |
|
|
Aug 08 05:38:00 PM PDT 24 |
Aug 08 05:43:51 PM PDT 24 |
82806685965 ps |
| T851 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1788010023 |
|
|
Aug 08 05:34:36 PM PDT 24 |
Aug 08 05:37:23 PM PDT 24 |
1330798704 ps |
| T852 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3913659196 |
|
|
Aug 08 05:37:28 PM PDT 24 |
Aug 08 05:38:45 PM PDT 24 |
44158233276 ps |
| T853 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1525248409 |
|
|
Aug 08 05:36:13 PM PDT 24 |
Aug 08 05:36:42 PM PDT 24 |
4299049812 ps |
| T854 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4148523077 |
|
|
Aug 08 05:33:57 PM PDT 24 |
Aug 08 05:34:15 PM PDT 24 |
962065964 ps |
| T855 |
/workspace/coverage/default/7.sram_ctrl_smoke.70624224 |
|
|
Aug 08 05:32:14 PM PDT 24 |
Aug 08 05:34:38 PM PDT 24 |
451168626 ps |
| T856 |
/workspace/coverage/default/4.sram_ctrl_bijection.1863292091 |
|
|
Aug 08 05:32:10 PM PDT 24 |
Aug 08 05:46:21 PM PDT 24 |
38597474896 ps |
| T857 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1169954678 |
|
|
Aug 08 05:37:47 PM PDT 24 |
Aug 08 05:37:48 PM PDT 24 |
19807100 ps |
| T858 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3901826620 |
|
|
Aug 08 05:36:42 PM PDT 24 |
Aug 08 05:36:42 PM PDT 24 |
24496454 ps |
| T859 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.4207833728 |
|
|
Aug 08 05:32:04 PM PDT 24 |
Aug 08 05:36:29 PM PDT 24 |
3944251226 ps |
| T860 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2316461740 |
|
|
Aug 08 05:32:06 PM PDT 24 |
Aug 08 05:35:03 PM PDT 24 |
2192726775 ps |
| T861 |
/workspace/coverage/default/35.sram_ctrl_smoke.1865305636 |
|
|
Aug 08 05:35:25 PM PDT 24 |
Aug 08 05:37:17 PM PDT 24 |
861396900 ps |
| T862 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3827392856 |
|
|
Aug 08 05:32:11 PM PDT 24 |
Aug 08 05:32:23 PM PDT 24 |
1960871530 ps |
| T863 |
/workspace/coverage/default/44.sram_ctrl_regwen.1679020177 |
|
|
Aug 08 05:37:09 PM PDT 24 |
Aug 08 05:44:58 PM PDT 24 |
7724252037 ps |
| T864 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1353668273 |
|
|
Aug 08 05:32:56 PM PDT 24 |
Aug 08 05:33:26 PM PDT 24 |
6560363005 ps |
| T865 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1677333884 |
|
|
Aug 08 05:36:14 PM PDT 24 |
Aug 08 05:54:00 PM PDT 24 |
26105766640 ps |
| T866 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.119676231 |
|
|
Aug 08 05:37:18 PM PDT 24 |
Aug 08 05:40:07 PM PDT 24 |
1529665453 ps |
| T867 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.102495817 |
|
|
Aug 08 05:34:46 PM PDT 24 |
Aug 08 05:38:47 PM PDT 24 |
3946530202 ps |
| T868 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1536431765 |
|
|
Aug 08 05:33:24 PM PDT 24 |
Aug 08 05:34:47 PM PDT 24 |
5338823993 ps |
| T869 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2705493735 |
|
|
Aug 08 05:32:26 PM PDT 24 |
Aug 08 05:34:25 PM PDT 24 |
10573987933 ps |
| T870 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2828253917 |
|
|
Aug 08 05:33:31 PM PDT 24 |
Aug 08 05:34:38 PM PDT 24 |
4020265634 ps |
| T871 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3098964258 |
|
|
Aug 08 05:32:03 PM PDT 24 |
Aug 08 05:32:09 PM PDT 24 |
462162297 ps |
| T872 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.532863896 |
|
|
Aug 08 05:32:24 PM PDT 24 |
Aug 08 05:32:44 PM PDT 24 |
1433187914 ps |
| T873 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.3528208335 |
|
|
Aug 08 05:34:58 PM PDT 24 |
Aug 08 05:50:04 PM PDT 24 |
5072838836 ps |
| T874 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.646026984 |
|
|
Aug 08 05:36:13 PM PDT 24 |
Aug 08 05:38:59 PM PDT 24 |
799701045 ps |
| T875 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.352586620 |
|
|
Aug 08 05:36:03 PM PDT 24 |
Aug 08 05:36:53 PM PDT 24 |
3038085749 ps |
| T876 |
/workspace/coverage/default/40.sram_ctrl_bijection.634197075 |
|
|
Aug 08 05:36:22 PM PDT 24 |
Aug 08 06:06:44 PM PDT 24 |
26564505841 ps |
| T877 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1022514057 |
|
|
Aug 08 05:35:04 PM PDT 24 |
Aug 08 05:39:36 PM PDT 24 |
4108466181 ps |
| T878 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3303954441 |
|
|
Aug 08 05:32:13 PM PDT 24 |
Aug 08 05:32:16 PM PDT 24 |
364385442 ps |
| T879 |
/workspace/coverage/default/35.sram_ctrl_bijection.3189008726 |
|
|
Aug 08 05:35:26 PM PDT 24 |
Aug 08 06:16:49 PM PDT 24 |
273942247257 ps |
| T880 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3352366809 |
|
|
Aug 08 05:34:35 PM PDT 24 |
Aug 08 05:35:12 PM PDT 24 |
7210694834 ps |
| T881 |
/workspace/coverage/default/3.sram_ctrl_smoke.2319691669 |
|
|
Aug 08 05:32:04 PM PDT 24 |
Aug 08 05:32:15 PM PDT 24 |
918947075 ps |
| T882 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.470617842 |
|
|
Aug 08 05:35:58 PM PDT 24 |
Aug 08 05:36:01 PM PDT 24 |
969187448 ps |
| T883 |
/workspace/coverage/default/8.sram_ctrl_partial_access.1820564909 |
|
|
Aug 08 05:32:11 PM PDT 24 |
Aug 08 05:33:18 PM PDT 24 |
737451577 ps |
| T884 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2510314142 |
|
|
Aug 08 05:37:02 PM PDT 24 |
Aug 08 05:38:20 PM PDT 24 |
4810159176 ps |
| T885 |
/workspace/coverage/default/29.sram_ctrl_alert_test.2422405614 |
|
|
Aug 08 05:34:34 PM PDT 24 |
Aug 08 05:34:34 PM PDT 24 |
18830306 ps |
| T886 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.322993645 |
|
|
Aug 08 05:35:46 PM PDT 24 |
Aug 08 05:37:34 PM PDT 24 |
1582883465 ps |
| T887 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.871466931 |
|
|
Aug 08 05:36:33 PM PDT 24 |
Aug 08 05:40:11 PM PDT 24 |
3450130612 ps |
| T888 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1844584811 |
|
|
Aug 08 05:34:35 PM PDT 24 |
Aug 08 05:39:18 PM PDT 24 |
3219741892 ps |
| T889 |
/workspace/coverage/default/19.sram_ctrl_executable.3874117606 |
|
|
Aug 08 05:33:08 PM PDT 24 |
Aug 08 05:52:08 PM PDT 24 |
257374724921 ps |
| T890 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2923700726 |
|
|
Aug 08 05:32:31 PM PDT 24 |
Aug 08 05:32:38 PM PDT 24 |
505677951 ps |
| T891 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3820694396 |
|
|
Aug 08 05:34:10 PM PDT 24 |
Aug 08 05:51:54 PM PDT 24 |
49986897318 ps |
| T892 |
/workspace/coverage/default/9.sram_ctrl_partial_access.989693733 |
|
|
Aug 08 05:32:26 PM PDT 24 |
Aug 08 05:32:32 PM PDT 24 |
2685676946 ps |
| T893 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3104234688 |
|
|
Aug 08 05:32:31 PM PDT 24 |
Aug 08 05:43:03 PM PDT 24 |
106017309155 ps |
| T894 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3989371730 |
|
|
Aug 08 05:32:34 PM PDT 24 |
Aug 08 06:50:42 PM PDT 24 |
46078532513 ps |
| T895 |
/workspace/coverage/default/1.sram_ctrl_executable.2057282078 |
|
|
Aug 08 05:32:04 PM PDT 24 |
Aug 08 05:41:13 PM PDT 24 |
22572339095 ps |
| T38 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.163256993 |
|
|
Aug 08 05:32:03 PM PDT 24 |
Aug 08 05:32:07 PM PDT 24 |
1250324989 ps |
| T896 |
/workspace/coverage/default/46.sram_ctrl_executable.3267578632 |
|
|
Aug 08 05:37:27 PM PDT 24 |
Aug 08 06:03:44 PM PDT 24 |
21541277609 ps |
| T897 |
/workspace/coverage/default/0.sram_ctrl_regwen.3755611426 |
|
|
Aug 08 05:32:02 PM PDT 24 |
Aug 08 05:44:16 PM PDT 24 |
11796817912 ps |
| T898 |
/workspace/coverage/default/11.sram_ctrl_bijection.1443875958 |
|
|
Aug 08 05:32:24 PM PDT 24 |
Aug 08 06:03:44 PM PDT 24 |
225665287951 ps |
| T899 |
/workspace/coverage/default/43.sram_ctrl_bijection.579141730 |
|
|
Aug 08 05:37:04 PM PDT 24 |
Aug 08 06:05:09 PM PDT 24 |
28532726756 ps |
| T900 |
/workspace/coverage/default/24.sram_ctrl_executable.2198621093 |
|
|
Aug 08 05:33:46 PM PDT 24 |
Aug 08 05:48:20 PM PDT 24 |
21022535439 ps |
| T901 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2973336803 |
|
|
Aug 08 05:33:49 PM PDT 24 |
Aug 08 05:38:09 PM PDT 24 |
16417545089 ps |
| T902 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1288973568 |
|
|
Aug 08 05:37:11 PM PDT 24 |
Aug 08 05:39:54 PM PDT 24 |
7280829629 ps |
| T903 |
/workspace/coverage/default/39.sram_ctrl_alert_test.630037865 |
|
|
Aug 08 05:36:22 PM PDT 24 |
Aug 08 05:36:23 PM PDT 24 |
29061262 ps |
| T904 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1179731014 |
|
|
Aug 08 05:36:41 PM PDT 24 |
Aug 08 05:37:04 PM PDT 24 |
2682664508 ps |
| T905 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.3764428525 |
|
|
Aug 08 05:33:51 PM PDT 24 |
Aug 08 05:33:55 PM PDT 24 |
419113894 ps |
| T906 |
/workspace/coverage/default/8.sram_ctrl_executable.3468661729 |
|
|
Aug 08 05:32:14 PM PDT 24 |
Aug 08 05:51:19 PM PDT 24 |
38365063119 ps |
| T907 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1359559312 |
|
|
Aug 08 05:36:52 PM PDT 24 |
Aug 08 05:37:39 PM PDT 24 |
3946198692 ps |
| T908 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2172405387 |
|
|
Aug 08 05:34:34 PM PDT 24 |
Aug 08 05:34:45 PM PDT 24 |
1208465675 ps |
| T909 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.480573746 |
|
|
Aug 08 05:33:42 PM PDT 24 |
Aug 08 05:34:18 PM PDT 24 |
728276847 ps |
| T910 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3549820659 |
|
|
Aug 08 05:33:29 PM PDT 24 |
Aug 08 05:38:28 PM PDT 24 |
5072398635 ps |
| T911 |
/workspace/coverage/default/32.sram_ctrl_smoke.3675867048 |
|
|
Aug 08 05:34:54 PM PDT 24 |
Aug 08 05:35:27 PM PDT 24 |
2603997047 ps |
| T912 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2777861883 |
|
|
Aug 08 05:35:35 PM PDT 24 |
Aug 08 05:47:43 PM PDT 24 |
68790423486 ps |
| T913 |
/workspace/coverage/default/37.sram_ctrl_regwen.4266735260 |
|
|
Aug 08 05:35:56 PM PDT 24 |
Aug 08 05:37:11 PM PDT 24 |
7698368497 ps |
| T914 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.35390142 |
|
|
Aug 08 05:34:00 PM PDT 24 |
Aug 08 05:36:38 PM PDT 24 |
4563453313 ps |
| T915 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1742920397 |
|
|
Aug 08 05:36:05 PM PDT 24 |
Aug 08 05:37:21 PM PDT 24 |
2907065074 ps |
| T916 |
/workspace/coverage/default/43.sram_ctrl_smoke.1634132929 |
|
|
Aug 08 05:36:50 PM PDT 24 |
Aug 08 05:37:11 PM PDT 24 |
2324051978 ps |
| T917 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2163624735 |
|
|
Aug 08 05:35:26 PM PDT 24 |
Aug 08 05:40:56 PM PDT 24 |
38167276895 ps |
| T918 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2814383256 |
|
|
Aug 08 05:37:21 PM PDT 24 |
Aug 08 05:39:34 PM PDT 24 |
8581523160 ps |
| T919 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.377821820 |
|
|
Aug 08 05:32:54 PM PDT 24 |
Aug 08 05:38:12 PM PDT 24 |
26608572571 ps |
| T920 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3813203341 |
|
|
Aug 08 05:33:19 PM PDT 24 |
Aug 08 05:38:00 PM PDT 24 |
27734526811 ps |
| T921 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1682514230 |
|
|
Aug 08 05:34:35 PM PDT 24 |
Aug 08 05:34:42 PM PDT 24 |
747796991 ps |
| T922 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.356582024 |
|
|
Aug 08 05:32:29 PM PDT 24 |
Aug 08 05:33:22 PM PDT 24 |
9515911000 ps |
| T923 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.810476864 |
|
|
Aug 08 05:37:20 PM PDT 24 |
Aug 08 05:45:52 PM PDT 24 |
10718177731 ps |
| T924 |
/workspace/coverage/default/6.sram_ctrl_stress_all.3766344168 |
|
|
Aug 08 05:32:17 PM PDT 24 |
Aug 08 06:58:25 PM PDT 24 |
201735029782 ps |
| T925 |
/workspace/coverage/default/44.sram_ctrl_stress_all.2769501411 |
|
|
Aug 08 05:37:10 PM PDT 24 |
Aug 08 06:21:40 PM PDT 24 |
113565505059 ps |
| T926 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.742232725 |
|
|
Aug 08 05:33:08 PM PDT 24 |
Aug 08 05:54:48 PM PDT 24 |
37480626107 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2530189787 |
|
|
Aug 08 05:34:35 PM PDT 24 |
Aug 08 05:34:42 PM PDT 24 |
2774679088 ps |
| T928 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2283396143 |
|
|
Aug 08 05:34:36 PM PDT 24 |
Aug 08 05:49:05 PM PDT 24 |
32401101079 ps |
| T929 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1957138910 |
|
|
Aug 08 05:33:28 PM PDT 24 |
Aug 08 05:47:06 PM PDT 24 |
16860345641 ps |
| T930 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.1291717915 |
|
|
Aug 08 05:33:29 PM PDT 24 |
Aug 08 05:38:47 PM PDT 24 |
57609386612 ps |
| T931 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2937785889 |
|
|
Aug 08 05:32:10 PM PDT 24 |
Aug 08 05:36:39 PM PDT 24 |
78789550278 ps |
| T932 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2374153069 |
|
|
Aug 08 05:32:50 PM PDT 24 |
Aug 08 05:41:38 PM PDT 24 |
6936238014 ps |
| T933 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2796795475 |
|
|
Aug 08 05:36:11 PM PDT 24 |
Aug 08 05:36:35 PM PDT 24 |
3409474277 ps |
| T934 |
/workspace/coverage/default/25.sram_ctrl_stress_all.1019340317 |
|
|
Aug 08 05:33:49 PM PDT 24 |
Aug 08 06:51:14 PM PDT 24 |
229821837492 ps |
| T935 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.4197510772 |
|
|
Aug 08 05:36:44 PM PDT 24 |
Aug 08 05:38:21 PM PDT 24 |
803185045 ps |
| T936 |
/workspace/coverage/default/8.sram_ctrl_stress_all.2250845865 |
|
|
Aug 08 05:32:11 PM PDT 24 |
Aug 08 05:57:11 PM PDT 24 |
122388950831 ps |
| T937 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.2197778910 |
|
|
Aug 08 05:31:59 PM PDT 24 |
Aug 08 05:34:21 PM PDT 24 |
3305572422 ps |
| T938 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3383531703 |
|
|
Aug 08 05:33:33 PM PDT 24 |
Aug 08 05:34:50 PM PDT 24 |
14964601923 ps |
| T939 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.693219056 |
|
|
Aug 08 05:28:46 PM PDT 24 |
Aug 08 05:28:51 PM PDT 24 |
713186765 ps |
| T81 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4186583712 |
|
|
Aug 08 05:28:38 PM PDT 24 |
Aug 08 05:29:08 PM PDT 24 |
11176868624 ps |
| T940 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1969643124 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:28:40 PM PDT 24 |
1368499052 ps |
| T941 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1949974711 |
|
|
Aug 08 05:28:24 PM PDT 24 |
Aug 08 05:28:28 PM PDT 24 |
369027824 ps |
| T942 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2159000007 |
|
|
Aug 08 05:28:45 PM PDT 24 |
Aug 08 05:28:48 PM PDT 24 |
27281711 ps |
| T82 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3537638357 |
|
|
Aug 08 05:28:29 PM PDT 24 |
Aug 08 05:28:29 PM PDT 24 |
22245811 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3628832136 |
|
|
Aug 08 05:28:23 PM PDT 24 |
Aug 08 05:28:24 PM PDT 24 |
12170408 ps |
| T119 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1247792415 |
|
|
Aug 08 05:28:25 PM PDT 24 |
Aug 08 05:28:26 PM PDT 24 |
95119611 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.436851800 |
|
|
Aug 08 05:28:26 PM PDT 24 |
Aug 08 05:28:27 PM PDT 24 |
135508142 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3057821120 |
|
|
Aug 08 05:28:40 PM PDT 24 |
Aug 08 05:28:44 PM PDT 24 |
398057191 ps |
| T78 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.200346428 |
|
|
Aug 08 05:28:39 PM PDT 24 |
Aug 08 05:28:41 PM PDT 24 |
386580689 ps |
| T91 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3304026754 |
|
|
Aug 08 05:28:36 PM PDT 24 |
Aug 08 05:29:35 PM PDT 24 |
14690785783 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3996358403 |
|
|
Aug 08 05:28:24 PM PDT 24 |
Aug 08 05:29:16 PM PDT 24 |
7390946716 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1740951507 |
|
|
Aug 08 05:28:28 PM PDT 24 |
Aug 08 05:28:30 PM PDT 24 |
80642037 ps |
| T111 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.138535828 |
|
|
Aug 08 05:28:46 PM PDT 24 |
Aug 08 05:28:47 PM PDT 24 |
16839697 ps |
| T112 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.523929798 |
|
|
Aug 08 05:28:48 PM PDT 24 |
Aug 08 05:28:49 PM PDT 24 |
72747322 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3679445123 |
|
|
Aug 08 05:28:27 PM PDT 24 |
Aug 08 05:28:27 PM PDT 24 |
15454693 ps |
| T944 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3493736032 |
|
|
Aug 08 05:28:52 PM PDT 24 |
Aug 08 05:28:56 PM PDT 24 |
350183876 ps |
| T80 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2112545371 |
|
|
Aug 08 05:28:50 PM PDT 24 |
Aug 08 05:28:53 PM PDT 24 |
1225682587 ps |
| T127 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.703019979 |
|
|
Aug 08 05:28:23 PM PDT 24 |
Aug 08 05:28:25 PM PDT 24 |
92668072 ps |
| T93 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4147711433 |
|
|
Aug 08 05:28:51 PM PDT 24 |
Aug 08 05:29:47 PM PDT 24 |
7062806390 ps |
| T128 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3778693187 |
|
|
Aug 08 05:28:41 PM PDT 24 |
Aug 08 05:28:43 PM PDT 24 |
349458689 ps |
| T945 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.360161888 |
|
|
Aug 08 05:28:46 PM PDT 24 |
Aug 08 05:28:47 PM PDT 24 |
18513754 ps |
| T946 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1876128582 |
|
|
Aug 08 05:28:38 PM PDT 24 |
Aug 08 05:28:42 PM PDT 24 |
219877170 ps |
| T94 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4059599000 |
|
|
Aug 08 05:28:24 PM PDT 24 |
Aug 08 05:29:21 PM PDT 24 |
12380336170 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4171803508 |
|
|
Aug 08 05:28:25 PM PDT 24 |
Aug 08 05:28:26 PM PDT 24 |
19398432 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.57125862 |
|
|
Aug 08 05:28:24 PM PDT 24 |
Aug 08 05:29:19 PM PDT 24 |
7073404119 ps |
| T96 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1713343150 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:29:07 PM PDT 24 |
16009677862 ps |
| T97 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4007818855 |
|
|
Aug 08 05:28:24 PM PDT 24 |
Aug 08 05:28:25 PM PDT 24 |
22019862 ps |
| T948 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1723429306 |
|
|
Aug 08 05:28:57 PM PDT 24 |
Aug 08 05:28:58 PM PDT 24 |
55631770 ps |
| T130 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3340114465 |
|
|
Aug 08 05:28:46 PM PDT 24 |
Aug 08 05:28:48 PM PDT 24 |
141279739 ps |
| T133 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1923266728 |
|
|
Aug 08 05:28:25 PM PDT 24 |
Aug 08 05:28:27 PM PDT 24 |
132271567 ps |
| T949 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.563846935 |
|
|
Aug 08 05:28:47 PM PDT 24 |
Aug 08 05:28:48 PM PDT 24 |
36903674 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.464627160 |
|
|
Aug 08 05:28:36 PM PDT 24 |
Aug 08 05:28:37 PM PDT 24 |
64220056 ps |
| T99 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1085788742 |
|
|
Aug 08 05:28:47 PM PDT 24 |
Aug 08 05:29:44 PM PDT 24 |
24356368242 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2973848236 |
|
|
Aug 08 05:28:45 PM PDT 24 |
Aug 08 05:28:46 PM PDT 24 |
40295244 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3833075703 |
|
|
Aug 08 05:28:25 PM PDT 24 |
Aug 08 05:28:26 PM PDT 24 |
19019164 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3616379207 |
|
|
Aug 08 05:28:28 PM PDT 24 |
Aug 08 05:28:31 PM PDT 24 |
697646972 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1829561730 |
|
|
Aug 08 05:28:38 PM PDT 24 |
Aug 08 05:28:39 PM PDT 24 |
18826944 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3014441010 |
|
|
Aug 08 05:28:39 PM PDT 24 |
Aug 08 05:28:40 PM PDT 24 |
79460972 ps |
| T100 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2103590932 |
|
|
Aug 08 05:28:36 PM PDT 24 |
Aug 08 05:29:27 PM PDT 24 |
7603021334 ps |
| T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3936351824 |
|
|
Aug 08 05:28:46 PM PDT 24 |
Aug 08 05:28:47 PM PDT 24 |
142893149 ps |
| T957 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1290623269 |
|
|
Aug 08 05:28:38 PM PDT 24 |
Aug 08 05:28:40 PM PDT 24 |
212290839 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3740343202 |
|
|
Aug 08 05:28:28 PM PDT 24 |
Aug 08 05:28:29 PM PDT 24 |
66479718 ps |
| T101 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2741951055 |
|
|
Aug 08 05:28:36 PM PDT 24 |
Aug 08 05:29:03 PM PDT 24 |
7697652003 ps |
| T959 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2692024539 |
|
|
Aug 08 05:28:36 PM PDT 24 |
Aug 08 05:28:37 PM PDT 24 |
25743626 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.622538956 |
|
|
Aug 08 05:28:38 PM PDT 24 |
Aug 08 05:28:38 PM PDT 24 |
36184759 ps |
| T961 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3308201269 |
|
|
Aug 08 05:28:48 PM PDT 24 |
Aug 08 05:28:48 PM PDT 24 |
74931133 ps |
| T131 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2927784998 |
|
|
Aug 08 05:28:39 PM PDT 24 |
Aug 08 05:28:42 PM PDT 24 |
885937427 ps |
| T132 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2421889454 |
|
|
Aug 08 05:28:41 PM PDT 24 |
Aug 08 05:28:43 PM PDT 24 |
336983978 ps |
| T134 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1635871524 |
|
|
Aug 08 05:28:48 PM PDT 24 |
Aug 08 05:28:50 PM PDT 24 |
205594514 ps |
| T962 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1945814941 |
|
|
Aug 08 05:28:50 PM PDT 24 |
Aug 08 05:28:55 PM PDT 24 |
256168167 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1242773078 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:28:38 PM PDT 24 |
28620856 ps |
| T964 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.760545941 |
|
|
Aug 08 05:28:39 PM PDT 24 |
Aug 08 05:28:40 PM PDT 24 |
82551078 ps |
| T109 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1195499837 |
|
|
Aug 08 05:28:24 PM PDT 24 |
Aug 08 05:28:51 PM PDT 24 |
3688317747 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1314971850 |
|
|
Aug 08 05:28:24 PM PDT 24 |
Aug 08 05:28:27 PM PDT 24 |
78081200 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.689809905 |
|
|
Aug 08 05:28:25 PM PDT 24 |
Aug 08 05:28:29 PM PDT 24 |
1477356042 ps |
| T967 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.934339148 |
|
|
Aug 08 05:28:52 PM PDT 24 |
Aug 08 05:28:53 PM PDT 24 |
21100800 ps |
| T968 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1769833260 |
|
|
Aug 08 05:28:46 PM PDT 24 |
Aug 08 05:28:47 PM PDT 24 |
18630779 ps |
| T969 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2764741257 |
|
|
Aug 08 05:28:46 PM PDT 24 |
Aug 08 05:28:50 PM PDT 24 |
1480548051 ps |
| T110 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3958650427 |
|
|
Aug 08 05:28:46 PM PDT 24 |
Aug 08 05:28:47 PM PDT 24 |
52873829 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1049655356 |
|
|
Aug 08 05:28:29 PM PDT 24 |
Aug 08 05:28:30 PM PDT 24 |
24434602 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1689953827 |
|
|
Aug 08 05:28:28 PM PDT 24 |
Aug 08 05:29:32 PM PDT 24 |
43974929123 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3163520753 |
|
|
Aug 08 05:28:23 PM PDT 24 |
Aug 08 05:28:26 PM PDT 24 |
365319557 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3295065195 |
|
|
Aug 08 05:28:48 PM PDT 24 |
Aug 08 05:29:15 PM PDT 24 |
7595656161 ps |
| T135 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1960295755 |
|
|
Aug 08 05:28:28 PM PDT 24 |
Aug 08 05:28:29 PM PDT 24 |
349690893 ps |
| T974 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2695930223 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:28:39 PM PDT 24 |
135800424 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1354105362 |
|
|
Aug 08 05:28:41 PM PDT 24 |
Aug 08 05:28:42 PM PDT 24 |
31587847 ps |
| T976 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1906319000 |
|
|
Aug 08 05:28:35 PM PDT 24 |
Aug 08 05:28:39 PM PDT 24 |
353542554 ps |
| T129 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.92391511 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:28:40 PM PDT 24 |
375969383 ps |
| T977 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1866576627 |
|
|
Aug 08 05:28:27 PM PDT 24 |
Aug 08 05:28:28 PM PDT 24 |
46321214 ps |
| T978 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2173630408 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:28:39 PM PDT 24 |
95557073 ps |
| T979 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1109221495 |
|
|
Aug 08 05:28:28 PM PDT 24 |
Aug 08 05:28:31 PM PDT 24 |
301401677 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1085583690 |
|
|
Aug 08 05:28:38 PM PDT 24 |
Aug 08 05:28:39 PM PDT 24 |
56921829 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1934165152 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:28:38 PM PDT 24 |
82674023 ps |
| T982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3023548104 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:28:38 PM PDT 24 |
40096710 ps |
| T983 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3845632656 |
|
|
Aug 08 05:28:35 PM PDT 24 |
Aug 08 05:28:37 PM PDT 24 |
125851892 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4106818438 |
|
|
Aug 08 05:28:48 PM PDT 24 |
Aug 08 05:28:52 PM PDT 24 |
43700094 ps |
| T985 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3239007560 |
|
|
Aug 08 05:28:48 PM PDT 24 |
Aug 08 05:28:49 PM PDT 24 |
74166611 ps |
| T986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4060569292 |
|
|
Aug 08 05:28:35 PM PDT 24 |
Aug 08 05:28:39 PM PDT 24 |
44926415 ps |
| T987 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3348872314 |
|
|
Aug 08 05:28:41 PM PDT 24 |
Aug 08 05:28:41 PM PDT 24 |
12020901 ps |
| T988 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1048205032 |
|
|
Aug 08 05:28:48 PM PDT 24 |
Aug 08 05:28:49 PM PDT 24 |
106827835 ps |
| T989 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1697607179 |
|
|
Aug 08 05:28:38 PM PDT 24 |
Aug 08 05:28:43 PM PDT 24 |
513493471 ps |
| T990 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2598066357 |
|
|
Aug 08 05:28:39 PM PDT 24 |
Aug 08 05:28:42 PM PDT 24 |
77522297 ps |
| T991 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.35641636 |
|
|
Aug 08 05:28:50 PM PDT 24 |
Aug 08 05:28:50 PM PDT 24 |
25587284 ps |
| T992 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3267201101 |
|
|
Aug 08 05:28:49 PM PDT 24 |
Aug 08 05:29:16 PM PDT 24 |
3693010650 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1951964159 |
|
|
Aug 08 05:28:38 PM PDT 24 |
Aug 08 05:28:39 PM PDT 24 |
13473415 ps |
| T994 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4126579990 |
|
|
Aug 08 05:28:55 PM PDT 24 |
Aug 08 05:28:56 PM PDT 24 |
99121866 ps |
| T995 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.292307790 |
|
|
Aug 08 05:28:52 PM PDT 24 |
Aug 08 05:28:55 PM PDT 24 |
362963361 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.973594369 |
|
|
Aug 08 05:28:40 PM PDT 24 |
Aug 08 05:28:43 PM PDT 24 |
147680156 ps |
| T997 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.496203291 |
|
|
Aug 08 05:28:52 PM PDT 24 |
Aug 08 05:28:56 PM PDT 24 |
2462342609 ps |
| T998 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3005831459 |
|
|
Aug 08 05:28:41 PM PDT 24 |
Aug 08 05:28:44 PM PDT 24 |
2623135852 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.394669562 |
|
|
Aug 08 05:28:26 PM PDT 24 |
Aug 08 05:28:27 PM PDT 24 |
25075421 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.293485908 |
|
|
Aug 08 05:28:27 PM PDT 24 |
Aug 08 05:28:30 PM PDT 24 |
720321275 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.801854310 |
|
|
Aug 08 05:28:47 PM PDT 24 |
Aug 08 05:28:51 PM PDT 24 |
364691761 ps |
| T1002 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.739903816 |
|
|
Aug 08 05:28:37 PM PDT 24 |
Aug 08 05:29:31 PM PDT 24 |
14429822514 ps |
| T1003 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2211021544 |
|
|
Aug 08 05:28:39 PM PDT 24 |
Aug 08 05:28:40 PM PDT 24 |
17581242 ps |