Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	350956856	1			T2	50002		T3	187356		T4	227336
instr_valid_dis	311628576	1			T2	50002		T4	227336		T5	393212
instr_en	21948598	1			T3	187356		T20	151902		T30	273290

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13513485	1			T3	24138		T20	225110		T30	28608
sram_ifetch_valid_disable	306689664	1			T2	50002		T3	97986		T4	227336
sram_ifetch_enable	30753707	1			T3	65232		T20	367142		T30	102574

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	350956856	1			T2	50002		T3	187356		T4	227336
hw_debug_en_valid_off	311775873	1			T2	50002		T3	79938		T4	227336
hw_debug_en_on	26024244	1			T3	43100		T20	324166		T30	59388

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	306689664	1			T2	50002		T3	97986		T4	227336
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	290693543	1			T2	50002		T4	227336		T5	393212
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10693523	1			T3	97986		T20	55594		T30	142108
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4205554	1			T20	21424		T30	18498		T134	36204
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2142710	1			T20	8078		T132	44		T26	13064
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1199798	1			T30	18498		T134	36204		T48	68
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7243806	1			T20	141610		T30	10110		T23	71612
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1953798	1			T20	62982		T23	42888		T24	29290
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1661530	1			T20	68354		T30	10110		T23	28724
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10225674	1			T3	20806		T20	100472		T30	34400
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3874814	1			T20	100472		T23	57464		T134	42824
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4569144	1			T3	20806		T30	34400		T23	93610

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7434851	1			T3	65232		T20	27954		T30	102574
lc_exec_en	8554764	1			T3	22294		T20	82084		T30	14878
valid_exec_dis	305656091	1			T2	50002		T3	77180		T4	227336
invalid_exec_dis	44267192	1			T3	89370		T20	592252		T30	131182