Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	146437121	1			T2	9935		T3	42091		T4	20921
triple_byte_access	2790501	1			T3	803		T4	18382		T10	3553
halfword_access	4280151	1			T3	1274		T4	27831		T10	6598
byte_access	5990847	1			T3	1678		T4	37266		T10	12560
zero_access	1813094	1			T3	421		T4	9268		T10	7395

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80379412

1

T3

27587

T4

57074

T5

65536

auto[1]

80932302

1

T2

9935

T3

18680

T4

56594

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72808973	1			T3	25069		T4	10451		T5	65536
auto[0]	triple_byte_access	1329359	1			T3	474		T4	9235		T10	664
auto[0]	halfword_access	2090130	1			T3	769		T4	14016		T10	2339
auto[0]	byte_access	3067766	1			T3	1015		T4	18671		T10	6818
auto[0]	zero_access	1083184	1			T3	260		T4	4701		T10	5892
auto[1]	word_access	73628148	1			T2	9935		T3	17022		T4	10470
auto[1]	triple_byte_access	1461142	1			T3	329		T4	9147		T10	2889
auto[1]	halfword_access	2190021	1			T3	505		T4	13815		T10	4259
auto[1]	byte_access	2923081	1			T3	663		T4	18595		T10	5742
auto[1]	zero_access	729910	1			T3	161		T4	4567		T10	1503