Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	340481654	1			T1	556228		T2	314572		T3	345962
instr_valid_dis	302429912	1			T1	46306		T2	314572		T3	345866
instr_en	27569675	1			T1	509922		T3	96		T8	73036

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10960288	1			T1	477072		T3	115324		T8	18964
sram_ifetch_valid_disable	305096400	1			T1	59524		T2	314572		T3	80726
sram_ifetch_enable	24424966	1			T1	19632		T3	149912		T8	143454

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	340481654	1			T1	556228		T2	314572		T3	345962
hw_debug_en_valid_off	303123828	1			T1	70342		T2	314572		T3	94406
hw_debug_en_on	24287542	1			T1	435716		T3	201318		T8	110606

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	305096400	1			T1	59524		T2	314572		T3	80726
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	290143238	1			T1	1014		T2	314572		T3	80630
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11259911	1			T1	58510		T3	96		T8	73036
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4014970	1			T18	46114		T35	37608		T17	49534
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1144250	1			T18	35276		T35	37608		T17	23532
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2132852	1			T17	26002		T135	38734		T27	12552
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4655246	1			T1	431780		T3	100278		T8	18964
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1455944	1			T3	100278		T8	18964		T18	43380
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2463342	1			T1	431780		T18	132116		T17	68068
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10033266	1			T1	3936		T3	29012		T8	39052
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4228064	1			T3	29012		T8	39052		T18	47652
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4631262	1			T1	3936		T18	54956		T17	28664

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10878176	1			T1	19632		T18	198906		T17	112502
lc_exec_en	9599030	1			T3	72028		T8	52590		T18	261056
valid_exec_dis	297402314	1			T1	50710		T2	314572		T3	201626
invalid_exec_dis	35385254	1			T1	496704		T3	265236		T8	162418