Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	140387225	1			T1	217567		T2	157286		T3	74441
triple_byte_access	2820491	1			T1	4325		T3	1500		T4	16
halfword_access	4332307	1			T1	6581		T3	2276		T4	33
byte_access	6070727	1			T1	8514		T3	2967		T4	38
zero_access	1848412	1			T1	2121		T3	766		T4	8

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77537670

1

T1

121416

T2

786432

T3

47479

auto[1]

77921492

1

T1

117692

T2

786432

T3

34471

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69860628	1			T1	110449		T2	786432		T3	43142
auto[0]	triple_byte_access	1342249	1			T1	2228		T3	877		T4	9
auto[0]	halfword_access	2113933	1			T1	3339		T3	1307		T4	20
auto[0]	byte_access	3111845	1			T1	4315		T3	1702		T4	18
auto[0]	zero_access	1109015	1			T1	1085		T3	451		T4	5
auto[1]	word_access	70526597	1			T1	107118		T2	786432		T3	31299
auto[1]	triple_byte_access	1478242	1			T1	2097		T3	623		T4	7
auto[1]	halfword_access	2218374	1			T1	3242		T3	969		T4	13
auto[1]	byte_access	2958882	1			T1	4199		T3	1265		T4	20
auto[1]	zero_access	739397	1			T1	1036		T3	315		T4	3