Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	329292176	1			T1	389714		T2	11900		T3	20000
instr_valid_dis	292160387	1			T1	389714		T2	11900		T3	20000
instr_en	28906525	1			T5	561652		T9	91352		T27	222674

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11178686	1			T5	345218		T9	36388		T27	77732
sram_ifetch_valid_disable	284926870	1			T1	389714		T2	11900		T3	20000
sram_ifetch_enable	33186620	1			T5	393620		T9	93932		T27	233266

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	329292176	1			T1	389714		T2	11900		T3	20000
hw_debug_en_valid_off	290205814	1			T1	389714		T2	11900		T3	20000
hw_debug_en_on	26254090	1			T5	423574		T9	64650		T27	131074

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	284926870	1			T1	389714		T2	11900		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	271396655	1			T1	389714		T2	11900		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10333975	1			T5	47028		T9	23638		T27	100684
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5038694	1			T5	164736		T9	5680		T27	77732
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2256530	1			T27	29630		T142	44156		T139	42894
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2409072	1			T5	164736		T27	48102		T69	76
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4225570	1			T5	167858		T69	3246		T38	65736
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1606040	1			T69	3246		T139	1576		T20	130234
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2002466	1			T5	49754		T38	65736		T65	18620
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10237348	1			T5	32738		T9	6178		T27	79556
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4810492	1			T141	53994		T72	57252		T142	91966
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4219572	1			T5	32738		T27	52866		T69	32838

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13229154	1			T5	287510		T9	58472		T27	73888
lc_exec_en	11791172	1			T5	222978		T9	58472		T27	51518
valid_exec_dis	286919950	1			T1	389714		T2	11900		T3	20000
invalid_exec_dis	44365306	1			T5	738838		T9	130320		T27	310998