Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1033
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
73.13 73.13 93.05 93.05 72.99 72.99 86.67 86.67 33.33 33.33 83.65 83.65 93.57 93.57 48.63 48.63 /workspace/coverage/default/47.sram_ctrl_stress_all.3244836834
89.66 16.53 98.04 4.99 79.86 6.87 87.36 0.69 100.00 66.67 91.94 8.29 96.20 2.63 74.22 25.59 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.76854360
92.34 2.68 98.04 0.00 85.07 5.21 96.90 9.54 100.00 0.00 93.60 1.66 96.20 0.00 76.60 2.38 /workspace/coverage/default/45.sram_ctrl_stress_all.2386786150
93.59 1.24 98.28 0.25 85.31 0.24 96.90 0.00 100.00 0.00 93.60 0.00 96.20 0.00 84.83 8.23 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.957320045
94.51 0.93 98.45 0.16 86.14 0.83 97.11 0.21 100.00 0.00 94.31 0.71 96.20 0.00 89.40 4.57 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2418343885
95.23 0.71 98.61 0.16 87.91 1.78 97.93 0.83 100.00 0.00 95.02 0.71 96.78 0.58 90.31 0.91 /workspace/coverage/default/0.sram_ctrl_sec_cm.2893620204
95.73 0.51 98.86 0.25 88.74 0.83 97.93 0.00 100.00 0.00 95.73 0.71 97.81 1.02 91.04 0.73 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3645083879
96.08 0.35 98.86 0.00 90.17 1.42 98.00 0.07 100.00 0.00 95.97 0.24 97.81 0.00 91.77 0.73 /workspace/coverage/default/24.sram_ctrl_regwen.1460670322
96.36 0.28 99.10 0.25 90.28 0.12 98.07 0.07 100.00 0.00 96.21 0.24 97.81 0.00 93.05 1.28 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.1658150059
96.56 0.20 99.10 0.00 90.28 0.00 98.14 0.07 100.00 0.00 96.21 0.00 99.12 1.32 93.05 0.00 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3680564023
96.75 0.19 99.10 0.00 90.28 0.00 98.17 0.03 100.00 0.00 96.21 0.00 99.12 0.00 94.33 1.28 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3749781736
96.89 0.15 99.10 0.00 90.40 0.12 98.17 0.00 100.00 0.00 96.21 0.00 99.12 0.00 95.25 0.91 /workspace/coverage/default/10.sram_ctrl_stress_all.1427031418
97.02 0.13 99.10 0.00 90.40 0.00 98.17 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.16 0.91 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1837457889
97.15 0.13 99.18 0.08 90.40 0.00 99.00 0.83 100.00 0.00 96.21 0.00 99.12 0.00 96.16 0.00 /workspace/coverage/default/11.sram_ctrl_ram_cfg.1688121852
97.25 0.10 99.18 0.00 90.76 0.36 99.14 0.14 100.00 0.00 96.21 0.00 99.12 0.00 96.34 0.18 /workspace/coverage/default/12.sram_ctrl_alert_test.2680487352
97.33 0.08 99.18 0.00 90.76 0.00 99.72 0.59 100.00 0.00 96.21 0.00 99.12 0.00 96.34 0.00 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.284246780
97.41 0.08 99.18 0.00 90.76 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.89 0.55 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.253466483
97.45 0.03 99.18 0.00 91.00 0.24 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.89 0.00 /workspace/coverage/default/1.sram_ctrl_stress_all.1341678120
97.47 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.07 0.18 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1031810622
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.892883986
97.52 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.18 /workspace/coverage/default/11.sram_ctrl_executable.2005377616

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.96643340
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2569176983
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1976105108
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2223884902
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2752036808
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2697447840
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2788995177
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.551193502
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2243886819
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3100172295
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2612876445
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.824771521
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3228132761
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3182121667
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2902309135
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1240673809
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.515423795
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3597439246
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.91617599
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1429732425
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3846298361
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2940550114
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.949187808
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1030731625
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.146987980
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1607107513
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3613663261
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2611750314
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2744239370
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3657349653
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1615271522
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3212033541
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2101959921
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.931019427
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.560805024
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1591612980
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2453749319
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2897641164
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4055395752
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1174801996
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.199083395
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3660553894
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3413207425
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.473383216
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1781038504
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4054976100
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3685356602
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.317045631
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3789646192
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2067943055
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3866172237
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3186300220
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1272087538
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.638006983
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.418901741
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.844610796
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3126169469
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1009758611
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2428638850
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1072819296
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.850130509
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.288435315
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.525659875
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1208637132
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2764469186
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1471094700
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1921766735
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.27887906
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1245199147
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.966576482
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4271248416
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.815784030
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.557276463
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1783770171
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1045186627
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2051248130
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3034040617
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2402828293
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4065546226
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1355779
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3065521959
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2817720575
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.974544699
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3490263826
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2048899322
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.123363112
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.789569300
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.841700701
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2780605561
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3880572481
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.30112708
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1410379187
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3619347201
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1823758906
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.568167915
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1293623770
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1754211054
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1518934637
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2534703468
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2072065507
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3582001067
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4072911846
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1714393251
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3436825813
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1363082960
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1549937144
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2127023725
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3712540035
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2457716516
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4077956468
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4274888722
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4273540516
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3037971043
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.210941952
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.521937634
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1791127321
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1967512516
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3003705943
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3680677715
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.901452517
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3333433026
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1787678000
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3636078003
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3764166727
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1392841330
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3413437925
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3873267239
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2584622914
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2417226722
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.204620925
/workspace/coverage/default/0.sram_ctrl_alert_test.125367032
/workspace/coverage/default/0.sram_ctrl_bijection.352156056
/workspace/coverage/default/0.sram_ctrl_executable.1410967177
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3300486240
/workspace/coverage/default/0.sram_ctrl_max_throughput.2859203389
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1693016280
/workspace/coverage/default/0.sram_ctrl_mem_walk.1948018838
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2660927149
/workspace/coverage/default/0.sram_ctrl_partial_access.2707324663
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3077086391
/workspace/coverage/default/0.sram_ctrl_ram_cfg.869425617
/workspace/coverage/default/0.sram_ctrl_regwen.3731904924
/workspace/coverage/default/0.sram_ctrl_smoke.3058322175
/workspace/coverage/default/0.sram_ctrl_stress_all.1839595890
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2267582126
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2481314560
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1685330354
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.222933305
/workspace/coverage/default/1.sram_ctrl_alert_test.2751244020
/workspace/coverage/default/1.sram_ctrl_bijection.1274850380
/workspace/coverage/default/1.sram_ctrl_executable.591999203
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3257211281
/workspace/coverage/default/1.sram_ctrl_max_throughput.2247544983
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2536519725
/workspace/coverage/default/1.sram_ctrl_mem_walk.1426812889
/workspace/coverage/default/1.sram_ctrl_multiple_keys.400872626
/workspace/coverage/default/1.sram_ctrl_partial_access.4076548834
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1122641299
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1414371537
/workspace/coverage/default/1.sram_ctrl_regwen.894085454
/workspace/coverage/default/1.sram_ctrl_sec_cm.1626680127
/workspace/coverage/default/1.sram_ctrl_smoke.4268160779
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1882921652
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2759229687
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1320528590
/workspace/coverage/default/10.sram_ctrl_alert_test.3548471416
/workspace/coverage/default/10.sram_ctrl_bijection.1925649047
/workspace/coverage/default/10.sram_ctrl_executable.66570858
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3838249656
/workspace/coverage/default/10.sram_ctrl_max_throughput.4235028531
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2335916102
/workspace/coverage/default/10.sram_ctrl_mem_walk.3555315285
/workspace/coverage/default/10.sram_ctrl_multiple_keys.614660138
/workspace/coverage/default/10.sram_ctrl_partial_access.3937658505
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1649849083
/workspace/coverage/default/10.sram_ctrl_ram_cfg.715593739
/workspace/coverage/default/10.sram_ctrl_regwen.2042700625
/workspace/coverage/default/10.sram_ctrl_smoke.3207295216
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3942246354
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.316842326
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4210108984
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1770509611
/workspace/coverage/default/11.sram_ctrl_alert_test.1279195291
/workspace/coverage/default/11.sram_ctrl_bijection.179974507
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2299309051
/workspace/coverage/default/11.sram_ctrl_max_throughput.133422879
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2871561937
/workspace/coverage/default/11.sram_ctrl_mem_walk.2908044542
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1687381025
/workspace/coverage/default/11.sram_ctrl_partial_access.1308745831
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3551011977
/workspace/coverage/default/11.sram_ctrl_regwen.2491726752
/workspace/coverage/default/11.sram_ctrl_smoke.1906679545
/workspace/coverage/default/11.sram_ctrl_stress_all.4292961071
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2758036254
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3644526325
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.179005950
/workspace/coverage/default/12.sram_ctrl_bijection.765752951
/workspace/coverage/default/12.sram_ctrl_executable.3046351548
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2975299949
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/workspace/coverage/default/42.sram_ctrl_stress_all.3467909198
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3107834094
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2716428384
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1858957704
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2451177735
/workspace/coverage/default/43.sram_ctrl_alert_test.341035313
/workspace/coverage/default/43.sram_ctrl_bijection.215158264
/workspace/coverage/default/43.sram_ctrl_executable.1492898230
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3268997645
/workspace/coverage/default/43.sram_ctrl_max_throughput.3238992412
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.4293110424
/workspace/coverage/default/43.sram_ctrl_mem_walk.1930549853
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3928802364
/workspace/coverage/default/43.sram_ctrl_partial_access.518758384
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2712416792
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2600243390
/workspace/coverage/default/43.sram_ctrl_regwen.3764116126
/workspace/coverage/default/43.sram_ctrl_smoke.281054571
/workspace/coverage/default/43.sram_ctrl_stress_all.474709325
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2311460335
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2322370325
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.348277253
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3355612612
/workspace/coverage/default/44.sram_ctrl_alert_test.1161147185
/workspace/coverage/default/44.sram_ctrl_bijection.2677536146
/workspace/coverage/default/44.sram_ctrl_executable.488305641
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3842157373
/workspace/coverage/default/44.sram_ctrl_max_throughput.1629505705
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2375830196
/workspace/coverage/default/44.sram_ctrl_mem_walk.3467543995
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1061180060
/workspace/coverage/default/44.sram_ctrl_partial_access.3213884713
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1191395641
/workspace/coverage/default/44.sram_ctrl_ram_cfg.773440912
/workspace/coverage/default/44.sram_ctrl_regwen.2862732320
/workspace/coverage/default/44.sram_ctrl_smoke.3941436500
/workspace/coverage/default/44.sram_ctrl_stress_all.3912517168
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2053470921
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1690611258
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4127580151
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3794797801
/workspace/coverage/default/45.sram_ctrl_alert_test.858827480
/workspace/coverage/default/45.sram_ctrl_bijection.2036927915
/workspace/coverage/default/45.sram_ctrl_executable.2457975111
/workspace/coverage/default/45.sram_ctrl_lc_escalation.131587473
/workspace/coverage/default/45.sram_ctrl_max_throughput.2750849677
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.4230887304
/workspace/coverage/default/45.sram_ctrl_mem_walk.207803956
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2980829746
/workspace/coverage/default/45.sram_ctrl_partial_access.3608760217
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3426658588
/workspace/coverage/default/45.sram_ctrl_ram_cfg.4202100884
/workspace/coverage/default/45.sram_ctrl_regwen.428717939
/workspace/coverage/default/45.sram_ctrl_smoke.809026963
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2030823849
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2674163404
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2350291562
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1290819468
/workspace/coverage/default/46.sram_ctrl_alert_test.425061705
/workspace/coverage/default/46.sram_ctrl_bijection.206916927
/workspace/coverage/default/46.sram_ctrl_executable.1602527080
/workspace/coverage/default/46.sram_ctrl_lc_escalation.538553954
/workspace/coverage/default/46.sram_ctrl_max_throughput.1575476228
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1946747311
/workspace/coverage/default/46.sram_ctrl_mem_walk.2660088865
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1791619600
/workspace/coverage/default/46.sram_ctrl_partial_access.3965781643
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1754443769
/workspace/coverage/default/46.sram_ctrl_ram_cfg.308138903
/workspace/coverage/default/46.sram_ctrl_regwen.1325489463
/workspace/coverage/default/46.sram_ctrl_smoke.486583870
/workspace/coverage/default/46.sram_ctrl_stress_all.225419892
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3721598850
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3298482753
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3515705784
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2753313562
/workspace/coverage/default/47.sram_ctrl_alert_test.1075672530
/workspace/coverage/default/47.sram_ctrl_executable.4092688392
/workspace/coverage/default/47.sram_ctrl_lc_escalation.569701743
/workspace/coverage/default/47.sram_ctrl_max_throughput.2246556643
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1375548166
/workspace/coverage/default/47.sram_ctrl_mem_walk.2639181511
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2014427538
/workspace/coverage/default/47.sram_ctrl_partial_access.1457003684
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2383065585
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3930789228
/workspace/coverage/default/47.sram_ctrl_regwen.3690111015
/workspace/coverage/default/47.sram_ctrl_smoke.772663967
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1719221199
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.368241935
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2818801767
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3691134026
/workspace/coverage/default/48.sram_ctrl_alert_test.2445777394
/workspace/coverage/default/48.sram_ctrl_bijection.1366196053
/workspace/coverage/default/48.sram_ctrl_executable.1325557668
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1751461687
/workspace/coverage/default/48.sram_ctrl_max_throughput.1252931384
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.255994472
/workspace/coverage/default/48.sram_ctrl_mem_walk.1150590303
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1594880391
/workspace/coverage/default/48.sram_ctrl_partial_access.1626993318
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1901463144
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2382280781
/workspace/coverage/default/48.sram_ctrl_regwen.2197502772
/workspace/coverage/default/48.sram_ctrl_smoke.3536821840
/workspace/coverage/default/48.sram_ctrl_stress_all.2602173220
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3862325737
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2347895613
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1206070046
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2208972376
/workspace/coverage/default/49.sram_ctrl_alert_test.4120306937
/workspace/coverage/default/49.sram_ctrl_bijection.3554706600
/workspace/coverage/default/49.sram_ctrl_executable.3485836490
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2517601391
/workspace/coverage/default/49.sram_ctrl_max_throughput.2026415863
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3425682175
/workspace/coverage/default/49.sram_ctrl_mem_walk.1343397964
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2705392898
/workspace/coverage/default/49.sram_ctrl_partial_access.1144373378
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2913528147
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2235639416
/workspace/coverage/default/49.sram_ctrl_regwen.2956450610
/workspace/coverage/default/49.sram_ctrl_smoke.1717586373
/workspace/coverage/default/49.sram_ctrl_stress_all.2582979124
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.844130376
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2027165756
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2254761033
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1803119314
/workspace/coverage/default/5.sram_ctrl_alert_test.1942238808
/workspace/coverage/default/5.sram_ctrl_bijection.3252412537
/workspace/coverage/default/5.sram_ctrl_executable.2333793390
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3519218946
/workspace/coverage/default/5.sram_ctrl_max_throughput.1323669800
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2104514477
/workspace/coverage/default/5.sram_ctrl_mem_walk.4245761418
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1998445901
/workspace/coverage/default/5.sram_ctrl_partial_access.1498818373
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1753235849
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2163404685
/workspace/coverage/default/5.sram_ctrl_regwen.1498655914
/workspace/coverage/default/5.sram_ctrl_smoke.2539315660
/workspace/coverage/default/5.sram_ctrl_stress_all.1856983574
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2728383776
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3963490088
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1902381491
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2223115722
/workspace/coverage/default/6.sram_ctrl_alert_test.1104161765
/workspace/coverage/default/6.sram_ctrl_bijection.1091859944
/workspace/coverage/default/6.sram_ctrl_executable.3023553792
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2524490669
/workspace/coverage/default/6.sram_ctrl_max_throughput.3142679692
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1764712548
/workspace/coverage/default/6.sram_ctrl_mem_walk.419656603
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1683561080
/workspace/coverage/default/6.sram_ctrl_partial_access.2181605340
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2525448305
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3831973180
/workspace/coverage/default/6.sram_ctrl_regwen.1581353067
/workspace/coverage/default/6.sram_ctrl_smoke.3256596162
/workspace/coverage/default/6.sram_ctrl_stress_all.1607502739
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3068409174
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3978218720
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2544787891
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2423484346
/workspace/coverage/default/7.sram_ctrl_alert_test.4117187488
/workspace/coverage/default/7.sram_ctrl_bijection.2922546443
/workspace/coverage/default/7.sram_ctrl_executable.2046588434
/workspace/coverage/default/7.sram_ctrl_lc_escalation.583530287
/workspace/coverage/default/7.sram_ctrl_max_throughput.17880751
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.850156328
/workspace/coverage/default/7.sram_ctrl_mem_walk.1364115010
/workspace/coverage/default/7.sram_ctrl_partial_access.323616977
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3853306549
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1300248564
/workspace/coverage/default/7.sram_ctrl_regwen.2532674807
/workspace/coverage/default/7.sram_ctrl_smoke.3014237288
/workspace/coverage/default/7.sram_ctrl_stress_all.2417460865
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1452162709
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1562513572
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.608026837
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1178110608
/workspace/coverage/default/8.sram_ctrl_alert_test.205772227
/workspace/coverage/default/8.sram_ctrl_bijection.3729524303
/workspace/coverage/default/8.sram_ctrl_executable.1496415936
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1142711559
/workspace/coverage/default/8.sram_ctrl_max_throughput.3276480541
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2324608868
/workspace/coverage/default/8.sram_ctrl_mem_walk.364012817
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2639396659
/workspace/coverage/default/8.sram_ctrl_partial_access.718992693
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1386968960
/workspace/coverage/default/8.sram_ctrl_ram_cfg.439586128
/workspace/coverage/default/8.sram_ctrl_regwen.4215822660
/workspace/coverage/default/8.sram_ctrl_smoke.3738244774
/workspace/coverage/default/8.sram_ctrl_stress_all.1269250221
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3726238640
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1600918767
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3236285687
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1281009412
/workspace/coverage/default/9.sram_ctrl_alert_test.1838757083
/workspace/coverage/default/9.sram_ctrl_bijection.58973083
/workspace/coverage/default/9.sram_ctrl_executable.816111873
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2607150940
/workspace/coverage/default/9.sram_ctrl_max_throughput.3992522422
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1318612462
/workspace/coverage/default/9.sram_ctrl_mem_walk.60682656
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1441406824
/workspace/coverage/default/9.sram_ctrl_partial_access.2716506487
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.755700618
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3318843141
/workspace/coverage/default/9.sram_ctrl_regwen.244315212
/workspace/coverage/default/9.sram_ctrl_smoke.4078393569
/workspace/coverage/default/9.sram_ctrl_stress_all.550826836
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3036145857
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1633560431
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2166848747



Total test records in report: 1033
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/45.sram_ctrl_stress_all.2386786150 Aug 11 05:54:46 PM PDT 24 Aug 11 06:59:03 PM PDT 24 741281214789 ps
T2 /workspace/coverage/default/18.sram_ctrl_smoke.1033083738 Aug 11 05:47:42 PM PDT 24 Aug 11 05:48:37 PM PDT 24 1539328635 ps
T3 /workspace/coverage/default/28.sram_ctrl_max_throughput.198630541 Aug 11 05:50:10 PM PDT 24 Aug 11 05:52:45 PM PDT 24 1532633753 ps
T4 /workspace/coverage/default/0.sram_ctrl_sec_cm.2893620204 Aug 11 05:44:37 PM PDT 24 Aug 11 05:44:40 PM PDT 24 243002040 ps
T8 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2637686512 Aug 11 05:47:02 PM PDT 24 Aug 11 05:54:40 PM PDT 24 6131575396 ps
T5 /workspace/coverage/default/47.sram_ctrl_stress_all.3244836834 Aug 11 05:55:11 PM PDT 24 Aug 11 06:55:45 PM PDT 24 31760019202 ps
T9 /workspace/coverage/default/18.sram_ctrl_regwen.2917805208 Aug 11 05:47:48 PM PDT 24 Aug 11 05:58:34 PM PDT 24 5501270243 ps
T10 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3865274024 Aug 11 05:49:05 PM PDT 24 Aug 11 05:51:51 PM PDT 24 13511406940 ps
T11 /workspace/coverage/default/22.sram_ctrl_mem_walk.2213494905 Aug 11 05:48:49 PM PDT 24 Aug 11 05:53:18 PM PDT 24 8208118319 ps
T12 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3645083879 Aug 11 05:53:47 PM PDT 24 Aug 11 05:56:16 PM PDT 24 4577046051 ps
T33 /workspace/coverage/default/25.sram_ctrl_max_throughput.1628409239 Aug 11 05:49:35 PM PDT 24 Aug 11 05:52:15 PM PDT 24 782448593 ps
T18 /workspace/coverage/default/5.sram_ctrl_bijection.3252412537 Aug 11 05:45:09 PM PDT 24 Aug 11 06:19:31 PM PDT 24 234627979131 ps
T23 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.1658150059 Aug 11 05:48:45 PM PDT 24 Aug 11 05:52:52 PM PDT 24 4187403277 ps
T13 /workspace/coverage/default/18.sram_ctrl_alert_test.2617542135 Aug 11 05:47:56 PM PDT 24 Aug 11 05:47:56 PM PDT 24 19734928 ps
T24 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2231542067 Aug 11 05:46:52 PM PDT 24 Aug 11 05:47:03 PM PDT 24 1064609556 ps
T34 /workspace/coverage/default/32.sram_ctrl_smoke.3785555669 Aug 11 05:51:09 PM PDT 24 Aug 11 05:52:17 PM PDT 24 1303413109 ps
T27 /workspace/coverage/default/29.sram_ctrl_executable.1165861317 Aug 11 05:50:28 PM PDT 24 Aug 11 06:17:38 PM PDT 24 11530193160 ps
T69 /workspace/coverage/default/38.sram_ctrl_executable.842240979 Aug 11 05:53:01 PM PDT 24 Aug 11 06:06:30 PM PDT 24 5992081962 ps
T70 /workspace/coverage/default/46.sram_ctrl_bijection.206916927 Aug 11 05:54:43 PM PDT 24 Aug 11 06:03:57 PM PDT 24 54167671039 ps
T71 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1206070046 Aug 11 05:55:20 PM PDT 24 Aug 11 05:57:43 PM PDT 24 4872721338 ps
T6 /workspace/coverage/default/42.sram_ctrl_lc_escalation.1947434558 Aug 11 05:53:51 PM PDT 24 Aug 11 05:55:26 PM PDT 24 17403872606 ps
T25 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2267582126 Aug 11 05:44:39 PM PDT 24 Aug 11 05:45:08 PM PDT 24 1464423568 ps
T51 /workspace/coverage/default/45.sram_ctrl_bijection.2036927915 Aug 11 05:54:37 PM PDT 24 Aug 11 06:20:23 PM PDT 24 81731039570 ps
T52 /workspace/coverage/default/5.sram_ctrl_max_throughput.1323669800 Aug 11 05:45:07 PM PDT 24 Aug 11 05:45:27 PM PDT 24 723833226 ps
T53 /workspace/coverage/default/28.sram_ctrl_bijection.2048951792 Aug 11 05:50:12 PM PDT 24 Aug 11 06:00:36 PM PDT 24 28428041120 ps
T40 /workspace/coverage/default/29.sram_ctrl_mem_walk.2391758753 Aug 11 05:50:29 PM PDT 24 Aug 11 05:53:32 PM PDT 24 12046952095 ps
T14 /workspace/coverage/default/45.sram_ctrl_alert_test.858827480 Aug 11 05:54:41 PM PDT 24 Aug 11 05:54:42 PM PDT 24 18120464 ps
T38 /workspace/coverage/default/41.sram_ctrl_regwen.2178114991 Aug 11 05:53:38 PM PDT 24 Aug 11 06:15:04 PM PDT 24 55129477596 ps
T7 /workspace/coverage/default/38.sram_ctrl_lc_escalation.118463383 Aug 11 05:53:00 PM PDT 24 Aug 11 05:54:01 PM PDT 24 10605614713 ps
T54 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1633560431 Aug 11 05:45:41 PM PDT 24 Aug 11 05:50:39 PM PDT 24 9779809183 ps
T55 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2937486747 Aug 11 05:47:13 PM PDT 24 Aug 11 05:49:51 PM PDT 24 2531362161 ps
T158 /workspace/coverage/default/19.sram_ctrl_smoke.2827946455 Aug 11 05:47:54 PM PDT 24 Aug 11 05:48:13 PM PDT 24 2156527381 ps
T65 /workspace/coverage/default/2.sram_ctrl_regwen.3784797429 Aug 11 05:44:53 PM PDT 24 Aug 11 05:45:24 PM PDT 24 803401493 ps
T39 /workspace/coverage/default/15.sram_ctrl_executable.75493543 Aug 11 05:47:08 PM PDT 24 Aug 11 06:08:46 PM PDT 24 26810350137 ps
T141 /workspace/coverage/default/21.sram_ctrl_executable.2488780699 Aug 11 05:48:35 PM PDT 24 Aug 11 06:00:28 PM PDT 24 125046102269 ps
T22 /workspace/coverage/default/37.sram_ctrl_lc_escalation.867165349 Aug 11 05:52:41 PM PDT 24 Aug 11 05:53:47 PM PDT 24 84486854773 ps
T15 /workspace/coverage/default/12.sram_ctrl_alert_test.2680487352 Aug 11 05:46:25 PM PDT 24 Aug 11 05:46:26 PM PDT 24 25180741 ps
T159 /workspace/coverage/default/4.sram_ctrl_partial_access.3012771829 Aug 11 05:45:02 PM PDT 24 Aug 11 05:45:52 PM PDT 24 754252236 ps
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T156 /workspace/coverage/default/36.sram_ctrl_bijection.2988826436 Aug 11 05:52:18 PM PDT 24 Aug 11 06:06:15 PM PDT 24 24331438781 ps
T35 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3223405753 Aug 11 05:51:39 PM PDT 24 Aug 11 06:14:09 PM PDT 24 147433021413 ps
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T142 /workspace/coverage/default/24.sram_ctrl_regwen.1460670322 Aug 11 05:49:17 PM PDT 24 Aug 11 06:00:27 PM PDT 24 52162971014 ps
T103 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.946650144 Aug 11 05:48:00 PM PDT 24 Aug 11 05:53:14 PM PDT 24 92454931721 ps
T160 /workspace/coverage/default/29.sram_ctrl_max_throughput.332847260 Aug 11 05:50:23 PM PDT 24 Aug 11 05:50:32 PM PDT 24 2084897452 ps
T41 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4218722386 Aug 11 05:53:56 PM PDT 24 Aug 11 05:56:35 PM PDT 24 9686751649 ps
T88 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2203844744 Aug 11 05:47:37 PM PDT 24 Aug 11 05:48:57 PM PDT 24 10679476808 ps
T26 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3083584120 Aug 11 05:47:09 PM PDT 24 Aug 11 05:47:18 PM PDT 24 187660172 ps
T139 /workspace/coverage/default/15.sram_ctrl_stress_all.576890551 Aug 11 05:47:08 PM PDT 24 Aug 11 07:38:11 PM PDT 24 989086627522 ps
T36 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.1248809002 Aug 11 05:52:07 PM PDT 24 Aug 11 06:05:53 PM PDT 24 15814651406 ps
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T154 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.224483744 Aug 11 05:52:59 PM PDT 24 Aug 11 05:53:06 PM PDT 24 774735274 ps
T104 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.737697126 Aug 11 05:52:06 PM PDT 24 Aug 11 05:57:16 PM PDT 24 5988130996 ps
T28 /workspace/coverage/default/28.sram_ctrl_ram_cfg.4124510486 Aug 11 05:50:18 PM PDT 24 Aug 11 05:50:21 PM PDT 24 1396490865 ps
T162 /workspace/coverage/default/29.sram_ctrl_partial_access.4070096993 Aug 11 05:50:27 PM PDT 24 Aug 11 05:51:06 PM PDT 24 2341279811 ps
T37 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1478806300 Aug 11 05:49:16 PM PDT 24 Aug 11 06:04:41 PM PDT 24 60853170196 ps
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T164 /workspace/coverage/default/18.sram_ctrl_partial_access.4119642190 Aug 11 05:47:48 PM PDT 24 Aug 11 05:48:11 PM PDT 24 922173398 ps
T165 /workspace/coverage/default/11.sram_ctrl_multiple_keys.1687381025 Aug 11 05:46:03 PM PDT 24 Aug 11 05:52:00 PM PDT 24 3744852839 ps
T166 /workspace/coverage/default/15.sram_ctrl_partial_access.3952452046 Aug 11 05:47:01 PM PDT 24 Aug 11 05:47:59 PM PDT 24 3013621702 ps
T105 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.500556538 Aug 11 05:44:47 PM PDT 24 Aug 11 05:48:33 PM PDT 24 3473639596 ps
T167 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.66430336 Aug 11 05:51:31 PM PDT 24 Aug 11 05:55:42 PM PDT 24 3355533992 ps
T147 /workspace/coverage/default/48.sram_ctrl_lc_escalation.1751461687 Aug 11 05:55:20 PM PDT 24 Aug 11 05:56:35 PM PDT 24 52306666655 ps
T29 /workspace/coverage/default/5.sram_ctrl_ram_cfg.2163404685 Aug 11 05:45:09 PM PDT 24 Aug 11 05:45:13 PM PDT 24 1774412302 ps
T157 /workspace/coverage/default/17.sram_ctrl_lc_escalation.3740226355 Aug 11 05:47:36 PM PDT 24 Aug 11 05:47:45 PM PDT 24 4831709265 ps
T149 /workspace/coverage/default/4.sram_ctrl_mem_walk.966674438 Aug 11 05:45:01 PM PDT 24 Aug 11 05:47:12 PM PDT 24 3953248242 ps
T168 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.211926807 Aug 11 05:50:39 PM PDT 24 Aug 11 05:51:43 PM PDT 24 4179676351 ps
T153 /workspace/coverage/default/33.sram_ctrl_alert_test.1148243553 Aug 11 05:51:39 PM PDT 24 Aug 11 05:51:40 PM PDT 24 33180172 ps
T169 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.316842326 Aug 11 05:45:51 PM PDT 24 Aug 11 05:51:03 PM PDT 24 3868162342 ps
T152 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1649849083 Aug 11 05:45:48 PM PDT 24 Aug 11 05:49:20 PM PDT 24 29421127993 ps
T44 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.850156328 Aug 11 05:45:27 PM PDT 24 Aug 11 05:46:53 PM PDT 24 5804836807 ps
T170 /workspace/coverage/default/35.sram_ctrl_partial_access.2588321005 Aug 11 05:52:07 PM PDT 24 Aug 11 05:52:29 PM PDT 24 1496958644 ps
T150 /workspace/coverage/default/42.sram_ctrl_multiple_keys.1643211455 Aug 11 05:53:43 PM PDT 24 Aug 11 06:17:42 PM PDT 24 144640310697 ps
T30 /workspace/coverage/default/35.sram_ctrl_ram_cfg.1449289431 Aug 11 05:52:12 PM PDT 24 Aug 11 05:52:15 PM PDT 24 367483923 ps
T171 /workspace/coverage/default/36.sram_ctrl_multiple_keys.514164400 Aug 11 05:52:18 PM PDT 24 Aug 11 05:52:42 PM PDT 24 5713493198 ps
T123 /workspace/coverage/default/44.sram_ctrl_lc_escalation.3842157373 Aug 11 05:54:18 PM PDT 24 Aug 11 05:55:06 PM PDT 24 21013520291 ps
T89 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.21837180 Aug 11 05:45:01 PM PDT 24 Aug 11 06:00:34 PM PDT 24 10853728128 ps
T48 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.957320045 Aug 11 05:51:10 PM PDT 24 Aug 11 05:53:03 PM PDT 24 1917197677 ps
T49 /workspace/coverage/default/31.sram_ctrl_mem_walk.3875835599 Aug 11 05:50:59 PM PDT 24 Aug 11 05:56:27 PM PDT 24 17963796916 ps
T155 /workspace/coverage/default/24.sram_ctrl_max_throughput.2010891237 Aug 11 05:49:17 PM PDT 24 Aug 11 05:49:23 PM PDT 24 1371845146 ps
T140 /workspace/coverage/default/11.sram_ctrl_executable.2005377616 Aug 11 05:46:10 PM PDT 24 Aug 11 06:03:44 PM PDT 24 24494352759 ps
T172 /workspace/coverage/default/5.sram_ctrl_alert_test.1942238808 Aug 11 05:45:10 PM PDT 24 Aug 11 05:45:11 PM PDT 24 23934213 ps
T148 /workspace/coverage/default/16.sram_ctrl_stress_all.2457218164 Aug 11 05:47:30 PM PDT 24 Aug 11 06:40:42 PM PDT 24 153969539128 ps
T173 /workspace/coverage/default/11.sram_ctrl_lc_escalation.2299309051 Aug 11 05:46:08 PM PDT 24 Aug 11 05:46:58 PM PDT 24 15743545363 ps
T174 /workspace/coverage/default/46.sram_ctrl_alert_test.425061705 Aug 11 05:55:01 PM PDT 24 Aug 11 05:55:02 PM PDT 24 43528356 ps
T50 /workspace/coverage/default/26.sram_ctrl_mem_walk.3266914394 Aug 11 05:49:56 PM PDT 24 Aug 11 05:52:35 PM PDT 24 14132150551 ps
T175 /workspace/coverage/default/21.sram_ctrl_partial_access.4093473958 Aug 11 05:48:24 PM PDT 24 Aug 11 05:49:43 PM PDT 24 5788724458 ps
T176 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.409578250 Aug 11 05:50:23 PM PDT 24 Aug 11 05:51:18 PM PDT 24 788552351 ps
T177 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1658942415 Aug 11 05:50:12 PM PDT 24 Aug 11 05:50:22 PM PDT 24 5286316264 ps
T178 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3933266400 Aug 11 05:53:38 PM PDT 24 Aug 11 05:55:26 PM PDT 24 802782232 ps
T179 /workspace/coverage/default/23.sram_ctrl_partial_access.1487297453 Aug 11 05:49:05 PM PDT 24 Aug 11 05:50:47 PM PDT 24 2064924631 ps
T180 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1977269277 Aug 11 05:48:56 PM PDT 24 Aug 11 05:52:43 PM PDT 24 5532907540 ps
T90 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.184889698 Aug 11 05:46:52 PM PDT 24 Aug 11 06:22:33 PM PDT 24 40458261313 ps
T181 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2803928098 Aug 11 05:51:38 PM PDT 24 Aug 11 05:51:42 PM PDT 24 1347247830 ps
T20 /workspace/coverage/default/10.sram_ctrl_stress_all.1427031418 Aug 11 05:46:03 PM PDT 24 Aug 11 07:17:21 PM PDT 24 584607147528 ps
T182 /workspace/coverage/default/35.sram_ctrl_multiple_keys.1514791745 Aug 11 05:52:06 PM PDT 24 Aug 11 05:55:37 PM PDT 24 4772712001 ps
T183 /workspace/coverage/default/6.sram_ctrl_partial_access.2181605340 Aug 11 05:45:14 PM PDT 24 Aug 11 05:45:40 PM PDT 24 1707819159 ps
T184 /workspace/coverage/default/28.sram_ctrl_alert_test.1397777225 Aug 11 05:50:18 PM PDT 24 Aug 11 05:50:19 PM PDT 24 20733494 ps
T151 /workspace/coverage/default/21.sram_ctrl_alert_test.371471259 Aug 11 05:48:42 PM PDT 24 Aug 11 05:48:43 PM PDT 24 21485680 ps
T91 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2871561937 Aug 11 05:46:09 PM PDT 24 Aug 11 05:47:30 PM PDT 24 14690362940 ps
T185 /workspace/coverage/default/12.sram_ctrl_multiple_keys.895044075 Aug 11 05:46:16 PM PDT 24 Aug 11 05:53:43 PM PDT 24 9550477030 ps
T186 /workspace/coverage/default/11.sram_ctrl_ram_cfg.1688121852 Aug 11 05:46:09 PM PDT 24 Aug 11 05:46:13 PM PDT 24 349793851 ps
T144 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3749781736 Aug 11 05:47:47 PM PDT 24 Aug 11 05:57:59 PM PDT 24 48859916952 ps
T187 /workspace/coverage/default/31.sram_ctrl_ram_cfg.3717126314 Aug 11 05:50:58 PM PDT 24 Aug 11 05:51:01 PM PDT 24 887092456 ps
T188 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2716428384 Aug 11 05:53:43 PM PDT 24 Aug 11 05:57:17 PM PDT 24 15098363081 ps
T189 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2726553919 Aug 11 05:47:36 PM PDT 24 Aug 11 05:47:54 PM PDT 24 737590984 ps
T190 /workspace/coverage/default/1.sram_ctrl_lc_escalation.3257211281 Aug 11 05:44:51 PM PDT 24 Aug 11 05:45:26 PM PDT 24 30625584037 ps
T16 /workspace/coverage/default/1.sram_ctrl_sec_cm.1626680127 Aug 11 05:44:47 PM PDT 24 Aug 11 05:44:50 PM PDT 24 225367659 ps
T191 /workspace/coverage/default/26.sram_ctrl_alert_test.3402241398 Aug 11 05:49:53 PM PDT 24 Aug 11 05:49:54 PM PDT 24 32980615 ps
T192 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1090179197 Aug 11 05:50:38 PM PDT 24 Aug 11 06:14:08 PM PDT 24 10179397053 ps
T66 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.844130376 Aug 11 05:56:06 PM PDT 24 Aug 11 05:56:45 PM PDT 24 5330879647 ps
T101 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3689964195 Aug 11 05:48:28 PM PDT 24 Aug 11 05:49:45 PM PDT 24 22240360299 ps
T193 /workspace/coverage/default/18.sram_ctrl_bijection.41091770 Aug 11 05:47:45 PM PDT 24 Aug 11 05:58:55 PM PDT 24 35233273991 ps
T194 /workspace/coverage/default/27.sram_ctrl_ram_cfg.1208618689 Aug 11 05:50:03 PM PDT 24 Aug 11 05:50:06 PM PDT 24 976254613 ps
T195 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2208972376 Aug 11 05:56:03 PM PDT 24 Aug 11 06:05:04 PM PDT 24 9198656609 ps
T196 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3590425840 Aug 11 05:47:49 PM PDT 24 Aug 11 05:53:15 PM PDT 24 9327897567 ps
T197 /workspace/coverage/default/3.sram_ctrl_partial_access.190035208 Aug 11 05:44:53 PM PDT 24 Aug 11 05:45:02 PM PDT 24 710821225 ps
T47 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2324608868 Aug 11 05:45:36 PM PDT 24 Aug 11 05:48:08 PM PDT 24 10999382557 ps
T198 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3236285687 Aug 11 05:45:38 PM PDT 24 Aug 11 05:47:19 PM PDT 24 5940435553 ps
T199 /workspace/coverage/default/0.sram_ctrl_partial_access.2707324663 Aug 11 05:44:32 PM PDT 24 Aug 11 05:44:54 PM PDT 24 1269981226 ps
T46 /workspace/coverage/default/35.sram_ctrl_mem_walk.3961355662 Aug 11 05:52:10 PM PDT 24 Aug 11 05:55:25 PM PDT 24 128433376411 ps
T200 /workspace/coverage/default/13.sram_ctrl_partial_access.149367489 Aug 11 05:46:31 PM PDT 24 Aug 11 05:46:43 PM PDT 24 1765623640 ps
T201 /workspace/coverage/default/43.sram_ctrl_partial_access.518758384 Aug 11 05:53:56 PM PDT 24 Aug 11 05:54:05 PM PDT 24 3675363753 ps
T202 /workspace/coverage/default/26.sram_ctrl_executable.3588703275 Aug 11 05:49:46 PM PDT 24 Aug 11 06:06:20 PM PDT 24 93816393423 ps
T203 /workspace/coverage/default/30.sram_ctrl_max_throughput.3230237693 Aug 11 05:50:36 PM PDT 24 Aug 11 05:50:43 PM PDT 24 2679320796 ps
T204 /workspace/coverage/default/36.sram_ctrl_alert_test.2227658371 Aug 11 05:52:35 PM PDT 24 Aug 11 05:52:36 PM PDT 24 47977178 ps
T124 /workspace/coverage/default/31.sram_ctrl_stress_all.1027203373 Aug 11 05:51:09 PM PDT 24 Aug 11 08:25:46 PM PDT 24 4112432702290 ps
T42 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.76854360 Aug 11 05:44:49 PM PDT 24 Aug 11 05:47:30 PM PDT 24 7859893553 ps
T114 /workspace/coverage/default/34.sram_ctrl_lc_escalation.2442661672 Aug 11 05:52:08 PM PDT 24 Aug 11 05:52:28 PM PDT 24 10040942116 ps
T115 /workspace/coverage/default/21.sram_ctrl_lc_escalation.3505728424 Aug 11 05:48:29 PM PDT 24 Aug 11 05:49:23 PM PDT 24 16285071875 ps
T116 /workspace/coverage/default/31.sram_ctrl_regwen.4090289009 Aug 11 05:50:59 PM PDT 24 Aug 11 05:58:43 PM PDT 24 41754038370 ps
T117 /workspace/coverage/default/29.sram_ctrl_regwen.2335453133 Aug 11 05:50:32 PM PDT 24 Aug 11 05:54:37 PM PDT 24 4402387256 ps
T118 /workspace/coverage/default/31.sram_ctrl_alert_test.3470083066 Aug 11 05:51:10 PM PDT 24 Aug 11 05:51:11 PM PDT 24 19202080 ps
T119 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.348277253 Aug 11 05:54:00 PM PDT 24 Aug 11 05:54:08 PM PDT 24 3070144304 ps
T120 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2316565075 Aug 11 05:52:42 PM PDT 24 Aug 11 05:56:35 PM PDT 24 38469620399 ps
T121 /workspace/coverage/default/0.sram_ctrl_alert_test.125367032 Aug 11 05:44:38 PM PDT 24 Aug 11 05:44:39 PM PDT 24 15377490 ps
T122 /workspace/coverage/default/24.sram_ctrl_executable.4176444642 Aug 11 05:49:14 PM PDT 24 Aug 11 05:52:37 PM PDT 24 28094152481 ps
T205 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3298482753 Aug 11 05:54:43 PM PDT 24 Aug 11 05:57:43 PM PDT 24 10359275309 ps
T206 /workspace/coverage/default/48.sram_ctrl_partial_access.1626993318 Aug 11 05:55:17 PM PDT 24 Aug 11 05:57:13 PM PDT 24 1976707550 ps
T56 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1508551591 Aug 11 05:46:45 PM PDT 24 Aug 11 05:49:21 PM PDT 24 4386714683 ps
T207 /workspace/coverage/default/6.sram_ctrl_bijection.1091859944 Aug 11 05:45:16 PM PDT 24 Aug 11 06:08:10 PM PDT 24 20096987378 ps
T208 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4127580151 Aug 11 05:54:20 PM PDT 24 Aug 11 05:56:30 PM PDT 24 800708953 ps
T209 /workspace/coverage/default/8.sram_ctrl_max_throughput.3276480541 Aug 11 05:45:35 PM PDT 24 Aug 11 05:45:43 PM PDT 24 3036284394 ps
T210 /workspace/coverage/default/12.sram_ctrl_lc_escalation.2975299949 Aug 11 05:46:15 PM PDT 24 Aug 11 05:47:58 PM PDT 24 151727293554 ps
T211 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1281009412 Aug 11 05:45:44 PM PDT 24 Aug 11 05:55:38 PM PDT 24 14365452712 ps
T212 /workspace/coverage/default/20.sram_ctrl_ram_cfg.167488718 Aug 11 05:48:17 PM PDT 24 Aug 11 05:48:20 PM PDT 24 1529523520 ps
T213 /workspace/coverage/default/23.sram_ctrl_executable.941046980 Aug 11 05:49:02 PM PDT 24 Aug 11 06:11:03 PM PDT 24 21382839735 ps
T214 /workspace/coverage/default/36.sram_ctrl_lc_escalation.3945280403 Aug 11 05:52:24 PM PDT 24 Aug 11 05:53:47 PM PDT 24 59479448729 ps
T215 /workspace/coverage/default/33.sram_ctrl_lc_escalation.2513926345 Aug 11 05:51:39 PM PDT 24 Aug 11 05:52:13 PM PDT 24 22028010674 ps
T43 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3455061469 Aug 11 05:52:08 PM PDT 24 Aug 11 05:53:09 PM PDT 24 1925573402 ps
T21 /workspace/coverage/default/30.sram_ctrl_stress_all.456374105 Aug 11 05:50:46 PM PDT 24 Aug 11 06:57:13 PM PDT 24 97301573293 ps
T67 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.284246780 Aug 11 05:46:10 PM PDT 24 Aug 11 05:46:24 PM PDT 24 880450490 ps
T216 /workspace/coverage/default/33.sram_ctrl_partial_access.3226453202 Aug 11 05:51:27 PM PDT 24 Aug 11 05:51:42 PM PDT 24 831672510 ps
T68 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1452162709 Aug 11 05:45:31 PM PDT 24 Aug 11 05:45:40 PM PDT 24 445128623 ps
T217 /workspace/coverage/default/13.sram_ctrl_multiple_keys.1559671639 Aug 11 05:46:24 PM PDT 24 Aug 11 05:55:43 PM PDT 24 10627946054 ps
T145 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1968508227 Aug 11 05:50:58 PM PDT 24 Aug 11 05:57:05 PM PDT 24 14456748131 ps
T218 /workspace/coverage/default/48.sram_ctrl_max_throughput.1252931384 Aug 11 05:55:21 PM PDT 24 Aug 11 05:55:38 PM PDT 24 2900766997 ps
T219 /workspace/coverage/default/0.sram_ctrl_mem_walk.1948018838 Aug 11 05:44:38 PM PDT 24 Aug 11 05:49:11 PM PDT 24 4108817112 ps
T220 /workspace/coverage/default/26.sram_ctrl_smoke.2913602166 Aug 11 05:49:46 PM PDT 24 Aug 11 05:50:10 PM PDT 24 762207638 ps
T221 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.839682415 Aug 11 05:46:24 PM PDT 24 Aug 11 05:47:43 PM PDT 24 11224806571 ps
T222 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2237670366 Aug 11 05:53:25 PM PDT 24 Aug 11 05:53:37 PM PDT 24 424886361 ps
T223 /workspace/coverage/default/45.sram_ctrl_mem_walk.207803956 Aug 11 05:54:43 PM PDT 24 Aug 11 05:57:21 PM PDT 24 11438093229 ps
T224 /workspace/coverage/default/5.sram_ctrl_executable.2333793390 Aug 11 05:45:08 PM PDT 24 Aug 11 05:56:08 PM PDT 24 14305604494 ps
T225 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3942246354 Aug 11 05:46:04 PM PDT 24 Aug 11 05:46:56 PM PDT 24 3425898150 ps
T226 /workspace/coverage/default/49.sram_ctrl_regwen.2956450610 Aug 11 05:56:02 PM PDT 24 Aug 11 06:03:12 PM PDT 24 8616072103 ps
T227 /workspace/coverage/default/2.sram_ctrl_lc_escalation.2506860881 Aug 11 05:44:47 PM PDT 24 Aug 11 05:47:02 PM PDT 24 79896946173 ps
T228 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3426658588 Aug 11 05:54:40 PM PDT 24 Aug 11 06:04:03 PM PDT 24 9275759585 ps
T229 /workspace/coverage/default/20.sram_ctrl_regwen.1341591976 Aug 11 05:48:19 PM PDT 24 Aug 11 05:57:41 PM PDT 24 13928213899 ps
T230 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.1718690726 Aug 11 05:45:02 PM PDT 24 Aug 11 05:50:57 PM PDT 24 60908203751 ps
T146 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2445682367 Aug 11 05:48:44 PM PDT 24 Aug 11 05:54:00 PM PDT 24 98583078876 ps
T143 /workspace/coverage/default/44.sram_ctrl_regwen.2862732320 Aug 11 05:54:19 PM PDT 24 Aug 11 06:02:08 PM PDT 24 48109880305 ps
T231 /workspace/coverage/default/27.sram_ctrl_stress_all.1819528131 Aug 11 05:50:06 PM PDT 24 Aug 11 06:58:34 PM PDT 24 193495786284 ps
T232 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.322293034 Aug 11 05:46:52 PM PDT 24 Aug 11 05:48:35 PM PDT 24 3183858845 ps
T233 /workspace/coverage/default/14.sram_ctrl_ram_cfg.1005078096 Aug 11 05:46:53 PM PDT 24 Aug 11 05:46:57 PM PDT 24 2597416342 ps
T234 /workspace/coverage/default/14.sram_ctrl_lc_escalation.3227541717 Aug 11 05:46:58 PM PDT 24 Aug 11 05:47:23 PM PDT 24 13652686894 ps
T107 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3068409174 Aug 11 05:45:24 PM PDT 24 Aug 11 05:45:44 PM PDT 24 3139885335 ps
T235 /workspace/coverage/default/13.sram_ctrl_smoke.571729143 Aug 11 05:46:24 PM PDT 24 Aug 11 05:46:44 PM PDT 24 1057750291 ps
T236 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.280117104 Aug 11 05:49:17 PM PDT 24 Aug 11 05:49:38 PM PDT 24 1419839796 ps
T237 /workspace/coverage/default/39.sram_ctrl_stress_all.2219738607 Aug 11 05:53:20 PM PDT 24 Aug 11 06:59:50 PM PDT 24 597976742684 ps
T238 /workspace/coverage/default/32.sram_ctrl_multiple_keys.4221420342 Aug 11 05:51:14 PM PDT 24 Aug 11 06:08:49 PM PDT 24 13733558420 ps
T239 /workspace/coverage/default/42.sram_ctrl_smoke.2532600322 Aug 11 05:53:48 PM PDT 24 Aug 11 05:55:21 PM PDT 24 3709833129 ps
T240 /workspace/coverage/default/20.sram_ctrl_stress_all.3411552886 Aug 11 05:48:30 PM PDT 24 Aug 11 06:44:23 PM PDT 24 218709550367 ps
T241 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.275086635 Aug 11 05:49:41 PM PDT 24 Aug 11 06:07:23 PM PDT 24 11882669977 ps
T242 /workspace/coverage/default/30.sram_ctrl_bijection.554638455 Aug 11 05:50:36 PM PDT 24 Aug 11 06:13:24 PM PDT 24 20017605244 ps
T243 /workspace/coverage/default/19.sram_ctrl_lc_escalation.64184495 Aug 11 05:48:06 PM PDT 24 Aug 11 05:49:28 PM PDT 24 14336895475 ps
T244 /workspace/coverage/default/39.sram_ctrl_smoke.807060774 Aug 11 05:53:05 PM PDT 24 Aug 11 05:53:36 PM PDT 24 1445297174 ps
T57 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3721598850 Aug 11 05:55:00 PM PDT 24 Aug 11 05:57:33 PM PDT 24 24369603563 ps
T58 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.734616473 Aug 11 05:47:28 PM PDT 24 Aug 11 05:48:44 PM PDT 24 7575119102 ps
T245 /workspace/coverage/default/16.sram_ctrl_bijection.3095574201 Aug 11 05:47:09 PM PDT 24 Aug 11 06:12:06 PM PDT 24 65229815965 ps
T246 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3021576050 Aug 11 05:48:43 PM PDT 24 Aug 11 05:49:26 PM PDT 24 5170278173 ps
T247 /workspace/coverage/default/21.sram_ctrl_max_throughput.1479414997 Aug 11 05:48:27 PM PDT 24 Aug 11 05:48:33 PM PDT 24 1282952871 ps
T248 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2550167435 Aug 11 05:53:01 PM PDT 24 Aug 11 06:07:32 PM PDT 24 11962432315 ps
T249 /workspace/coverage/default/8.sram_ctrl_bijection.3729524303 Aug 11 05:45:27 PM PDT 24 Aug 11 06:19:01 PM PDT 24 689974325810 ps
T250 /workspace/coverage/default/25.sram_ctrl_ram_cfg.900604856 Aug 11 05:49:34 PM PDT 24 Aug 11 05:49:38 PM PDT 24 1168358488 ps
T251 /workspace/coverage/default/36.sram_ctrl_mem_walk.722754234 Aug 11 05:52:29 PM PDT 24 Aug 11 05:55:09 PM PDT 24 7956720907 ps
T252 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1770509611 Aug 11 05:46:10 PM PDT 24 Aug 11 06:00:44 PM PDT 24 52825653705 ps
T253 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.179005950 Aug 11 05:46:16 PM PDT 24 Aug 11 05:56:55 PM PDT 24 7721812618 ps
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T255 /workspace/coverage/default/34.sram_ctrl_multiple_keys.2037345676 Aug 11 05:51:45 PM PDT 24 Aug 11 05:57:35 PM PDT 24 14155761327 ps
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T257 /workspace/coverage/default/40.sram_ctrl_max_throughput.2611534535 Aug 11 05:53:20 PM PDT 24 Aug 11 05:54:55 PM PDT 24 1154437449 ps
T258 /workspace/coverage/default/38.sram_ctrl_bijection.2164670417 Aug 11 05:52:54 PM PDT 24 Aug 11 06:25:53 PM PDT 24 110684081806 ps
T259 /workspace/coverage/default/7.sram_ctrl_partial_access.323616977 Aug 11 05:45:23 PM PDT 24 Aug 11 05:45:45 PM PDT 24 4271127272 ps
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T261 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3737499683 Aug 11 05:53:38 PM PDT 24 Aug 11 06:16:03 PM PDT 24 14431852430 ps
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T263 /workspace/coverage/default/2.sram_ctrl_partial_access.39044424 Aug 11 05:44:49 PM PDT 24 Aug 11 05:45:04 PM PDT 24 533963971 ps
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T265 /workspace/coverage/default/46.sram_ctrl_lc_escalation.538553954 Aug 11 05:54:55 PM PDT 24 Aug 11 05:55:28 PM PDT 24 4302011796 ps
T266 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.4292749283 Aug 11 05:44:54 PM PDT 24 Aug 11 05:46:19 PM PDT 24 9667301198 ps
T267 /workspace/coverage/default/9.sram_ctrl_lc_escalation.2607150940 Aug 11 05:45:41 PM PDT 24 Aug 11 05:46:27 PM PDT 24 7757347190 ps
T268 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2268800899 Aug 11 05:49:39 PM PDT 24 Aug 11 05:50:05 PM PDT 24 2841991861 ps
T269 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.843299952 Aug 11 05:52:52 PM PDT 24 Aug 11 05:58:32 PM PDT 24 14630608281 ps
T270 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3515705784 Aug 11 05:54:49 PM PDT 24 Aug 11 05:55:42 PM PDT 24 1116928559 ps
T271 /workspace/coverage/default/35.sram_ctrl_alert_test.3773200177 Aug 11 05:52:19 PM PDT 24 Aug 11 05:52:19 PM PDT 24 14027645 ps
T272 /workspace/coverage/default/39.sram_ctrl_executable.2889514967 Aug 11 05:53:13 PM PDT 24 Aug 11 06:10:27 PM PDT 24 32438373186 ps
T45 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2104514477 Aug 11 05:45:07 PM PDT 24 Aug 11 05:48:07 PM PDT 24 22498763180 ps
T273 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1239580780 Aug 11 05:49:46 PM PDT 24 Aug 11 05:56:23 PM PDT 24 7186164595 ps
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T275 /workspace/coverage/default/32.sram_ctrl_partial_access.3621515110 Aug 11 05:51:15 PM PDT 24 Aug 11 05:51:35 PM PDT 24 4802952896 ps
T276 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3509634450 Aug 11 05:44:46 PM PDT 24 Aug 11 05:47:11 PM PDT 24 800996453 ps
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T278 /workspace/coverage/default/14.sram_ctrl_bijection.1190112011 Aug 11 05:46:45 PM PDT 24 Aug 11 05:58:05 PM PDT 24 50071502096 ps
T279 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3963490088 Aug 11 05:45:11 PM PDT 24 Aug 11 05:49:21 PM PDT 24 4274032192 ps
T280 /workspace/coverage/default/49.sram_ctrl_stress_all.2582979124 Aug 11 05:56:07 PM PDT 24 Aug 11 06:43:33 PM PDT 24 169379715336 ps
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T282 /workspace/coverage/default/26.sram_ctrl_max_throughput.1589713654 Aug 11 05:49:47 PM PDT 24 Aug 11 05:50:28 PM PDT 24 1475887812 ps
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T290 /workspace/coverage/default/27.sram_ctrl_multiple_keys.2478747308 Aug 11 05:49:58 PM PDT 24 Aug 11 05:58:56 PM PDT 24 69290006526 ps
T291 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1879988224 Aug 11 05:49:03 PM PDT 24 Aug 11 06:12:09 PM PDT 24 15881389434 ps
T292 /workspace/coverage/default/33.sram_ctrl_stress_all.3192035218 Aug 11 05:51:39 PM PDT 24 Aug 11 06:48:02 PM PDT 24 468922952721 ps
T293 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1939730753 Aug 11 05:51:13 PM PDT 24 Aug 11 05:59:07 PM PDT 24 74324740810 ps
T294 /workspace/coverage/default/27.sram_ctrl_mem_walk.1590568712 Aug 11 05:50:05 PM PDT 24 Aug 11 05:52:40 PM PDT 24 6997349697 ps
T295 /workspace/coverage/default/26.sram_ctrl_ram_cfg.77870070 Aug 11 05:49:54 PM PDT 24 Aug 11 05:49:57 PM PDT 24 362924802 ps
T296 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2424790184 Aug 11 05:48:19 PM PDT 24 Aug 11 05:59:32 PM PDT 24 11274010971 ps
T297 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2759229687 Aug 11 05:44:37 PM PDT 24 Aug 11 05:46:20 PM PDT 24 3340824639 ps
T298 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1001376305 Aug 11 05:46:39 PM PDT 24 Aug 11 05:47:58 PM PDT 24 34211675931 ps
T299 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3794797801 Aug 11 05:54:39 PM PDT 24 Aug 11 06:02:28 PM PDT 24 50915316710 ps
T300 /workspace/coverage/default/0.sram_ctrl_max_throughput.2859203389 Aug 11 05:44:29 PM PDT 24 Aug 11 05:46:09 PM PDT 24 1588267937 ps
T301 /workspace/coverage/default/18.sram_ctrl_lc_escalation.2049397610 Aug 11 05:47:48 PM PDT 24 Aug 11 05:49:19 PM PDT 24 52126170653 ps
T302 /workspace/coverage/default/5.sram_ctrl_multiple_keys.1998445901 Aug 11 05:45:07 PM PDT 24 Aug 11 06:06:10 PM PDT 24 9449741568 ps
T303 /workspace/coverage/default/34.sram_ctrl_alert_test.3675523576 Aug 11 05:52:07 PM PDT 24 Aug 11 05:52:08 PM PDT 24 25186776 ps
T304 /workspace/coverage/default/10.sram_ctrl_mem_walk.3555315285 Aug 11 05:46:03 PM PDT 24 Aug 11 05:51:41 PM PDT 24 27690410791 ps
T305 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1195823225 Aug 11 05:50:12 PM PDT 24 Aug 11 05:57:31 PM PDT 24 19203977946 ps
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