Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	134922628	1			T1	193822		T2	5403		T3	10000
triple_byte_access	2847131	1			T1	2061		T2	115		T8	6484
halfword_access	4367695	1			T1	3156		T2	152		T8	9836
byte_access	6113676	1			T1	4098		T2	217		T8	13201
zero_access	1851584	1			T1	1039		T2	63		T8	3387

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74931192

1

T1

974381

T2

3016

T3

4983

auto[1]

75171522

1

T1

974193

T2

2934

T3

5017

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	67200965	1			T1	969189		T2	2728		T3	4983
auto[0]	triple_byte_access	1358051	1			T1	1073		T2	56		T8	3237
auto[0]	halfword_access	2132839	1			T1	1544		T2	88		T8	4866
auto[0]	byte_access	3132733	1			T1	2051		T2	108		T8	6533
auto[0]	zero_access	1106604	1			T1	524		T2	36		T8	1723
auto[1]	word_access	67721663	1			T1	969031		T2	2675		T3	5017
auto[1]	triple_byte_access	1489080	1			T1	988		T2	59		T8	3247
auto[1]	halfword_access	2234856	1			T1	1612		T2	64		T8	4970
auto[1]	byte_access	2980943	1			T1	2047		T2	109		T8	6668
auto[1]	zero_access	744980	1			T1	515		T2	27		T8	1664