| T796 |
/workspace/coverage/default/28.sram_ctrl_regwen.4153518953 |
|
|
Aug 11 05:50:17 PM PDT 24 |
Aug 11 06:02:32 PM PDT 24 |
34634247471 ps |
| T797 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2445777394 |
|
|
Aug 11 05:55:37 PM PDT 24 |
Aug 11 05:55:37 PM PDT 24 |
11459903 ps |
| T798 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2307298502 |
|
|
Aug 11 05:49:52 PM PDT 24 |
Aug 11 05:52:24 PM PDT 24 |
9734381781 ps |
| T799 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2121883249 |
|
|
Aug 11 05:48:36 PM PDT 24 |
Aug 11 05:48:53 PM PDT 24 |
454948939 ps |
| T800 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.848815862 |
|
|
Aug 11 05:46:47 PM PDT 24 |
Aug 11 05:52:36 PM PDT 24 |
10380439138 ps |
| T801 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1105646392 |
|
|
Aug 11 05:47:00 PM PDT 24 |
Aug 11 06:02:55 PM PDT 24 |
60133116823 ps |
| T802 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2756361417 |
|
|
Aug 11 05:44:54 PM PDT 24 |
Aug 11 05:47:51 PM PDT 24 |
18012381090 ps |
| T803 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2133646039 |
|
|
Aug 11 05:53:09 PM PDT 24 |
Aug 11 05:58:27 PM PDT 24 |
36001017611 ps |
| T32 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1186247489 |
|
|
Aug 11 05:45:09 PM PDT 24 |
Aug 11 05:45:11 PM PDT 24 |
643957237 ps |
| T804 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1284750132 |
|
|
Aug 11 05:52:04 PM PDT 24 |
Aug 11 06:11:10 PM PDT 24 |
13506148765 ps |
| T805 |
/workspace/coverage/default/43.sram_ctrl_executable.1492898230 |
|
|
Aug 11 05:54:13 PM PDT 24 |
Aug 11 06:10:50 PM PDT 24 |
216155544128 ps |
| T806 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1858957704 |
|
|
Aug 11 05:53:49 PM PDT 24 |
Aug 11 05:54:06 PM PDT 24 |
767532492 ps |
| T807 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1560057640 |
|
|
Aug 11 05:47:10 PM PDT 24 |
Aug 11 05:47:10 PM PDT 24 |
14907506 ps |
| T808 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.4286208540 |
|
|
Aug 11 05:46:46 PM PDT 24 |
Aug 11 05:49:37 PM PDT 24 |
21398806758 ps |
| T809 |
/workspace/coverage/default/47.sram_ctrl_partial_access.1457003684 |
|
|
Aug 11 05:55:10 PM PDT 24 |
Aug 11 05:55:13 PM PDT 24 |
359806035 ps |
| T810 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.4115530160 |
|
|
Aug 11 05:48:36 PM PDT 24 |
Aug 11 05:51:20 PM PDT 24 |
5563538675 ps |
| T811 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.17880751 |
|
|
Aug 11 05:45:28 PM PDT 24 |
Aug 11 05:47:06 PM PDT 24 |
757264935 ps |
| T812 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3786599710 |
|
|
Aug 11 05:46:58 PM PDT 24 |
Aug 11 05:51:29 PM PDT 24 |
10841800946 ps |
| T813 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.656364123 |
|
|
Aug 11 05:49:40 PM PDT 24 |
Aug 11 05:50:36 PM PDT 24 |
8756170996 ps |
| T814 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3113293800 |
|
|
Aug 11 05:52:42 PM PDT 24 |
Aug 11 06:07:26 PM PDT 24 |
57370361416 ps |
| T815 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2322370325 |
|
|
Aug 11 05:53:55 PM PDT 24 |
Aug 11 05:57:14 PM PDT 24 |
16267725913 ps |
| T816 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2712416792 |
|
|
Aug 11 05:54:01 PM PDT 24 |
Aug 11 06:00:49 PM PDT 24 |
29587699621 ps |
| T817 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.2315669773 |
|
|
Aug 11 05:53:58 PM PDT 24 |
Aug 11 05:54:02 PM PDT 24 |
1349958639 ps |
| T818 |
/workspace/coverage/default/23.sram_ctrl_alert_test.655035709 |
|
|
Aug 11 05:49:08 PM PDT 24 |
Aug 11 05:49:09 PM PDT 24 |
16633465 ps |
| T819 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1617662637 |
|
|
Aug 11 05:53:56 PM PDT 24 |
Aug 11 05:59:05 PM PDT 24 |
21879101643 ps |
| T820 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4273752973 |
|
|
Aug 11 05:53:16 PM PDT 24 |
Aug 11 05:53:42 PM PDT 24 |
2430862108 ps |
| T821 |
/workspace/coverage/default/49.sram_ctrl_alert_test.4120306937 |
|
|
Aug 11 05:56:17 PM PDT 24 |
Aug 11 05:56:17 PM PDT 24 |
16123445 ps |
| T822 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.261997553 |
|
|
Aug 11 05:50:01 PM PDT 24 |
Aug 11 05:51:08 PM PDT 24 |
2906059355 ps |
| T823 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.4124996483 |
|
|
Aug 11 05:47:58 PM PDT 24 |
Aug 11 05:54:17 PM PDT 24 |
15754857015 ps |
| T824 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3238992412 |
|
|
Aug 11 05:54:09 PM PDT 24 |
Aug 11 05:54:15 PM PDT 24 |
675202644 ps |
| T825 |
/workspace/coverage/default/44.sram_ctrl_bijection.2677536146 |
|
|
Aug 11 05:54:15 PM PDT 24 |
Aug 11 06:17:12 PM PDT 24 |
29854891086 ps |
| T826 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1320528590 |
|
|
Aug 11 05:45:55 PM PDT 24 |
Aug 11 06:03:15 PM PDT 24 |
12310474155 ps |
| T827 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2981800395 |
|
|
Aug 11 05:51:14 PM PDT 24 |
Aug 11 05:53:14 PM PDT 24 |
28363446012 ps |
| T828 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2015200661 |
|
|
Aug 11 05:50:06 PM PDT 24 |
Aug 11 06:08:51 PM PDT 24 |
137225617867 ps |
| T829 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1343397964 |
|
|
Aug 11 05:56:01 PM PDT 24 |
Aug 11 06:00:29 PM PDT 24 |
3942953003 ps |
| T830 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.1382512727 |
|
|
Aug 11 05:51:39 PM PDT 24 |
Aug 11 05:55:52 PM PDT 24 |
15167040630 ps |
| T831 |
/workspace/coverage/default/41.sram_ctrl_bijection.314186160 |
|
|
Aug 11 05:53:38 PM PDT 24 |
Aug 11 06:19:15 PM PDT 24 |
69406401973 ps |
| T832 |
/workspace/coverage/default/40.sram_ctrl_stress_all.3767766525 |
|
|
Aug 11 05:53:40 PM PDT 24 |
Aug 11 07:25:50 PM PDT 24 |
209131064591 ps |
| T833 |
/workspace/coverage/default/49.sram_ctrl_executable.3485836490 |
|
|
Aug 11 05:56:02 PM PDT 24 |
Aug 11 06:05:40 PM PDT 24 |
21070103348 ps |
| T834 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.60682656 |
|
|
Aug 11 05:45:44 PM PDT 24 |
Aug 11 05:51:21 PM PDT 24 |
18533596757 ps |
| T835 |
/workspace/coverage/default/20.sram_ctrl_executable.549682101 |
|
|
Aug 11 05:48:19 PM PDT 24 |
Aug 11 06:01:45 PM PDT 24 |
51117227267 ps |
| T836 |
/workspace/coverage/default/31.sram_ctrl_bijection.290850711 |
|
|
Aug 11 05:50:46 PM PDT 24 |
Aug 11 06:29:53 PM PDT 24 |
603828513795 ps |
| T837 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2223115722 |
|
|
Aug 11 05:45:16 PM PDT 24 |
Aug 11 06:03:20 PM PDT 24 |
9054629116 ps |
| T838 |
/workspace/coverage/default/33.sram_ctrl_smoke.2722429035 |
|
|
Aug 11 05:51:20 PM PDT 24 |
Aug 11 05:51:31 PM PDT 24 |
676130365 ps |
| T839 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1795234832 |
|
|
Aug 11 05:52:50 PM PDT 24 |
Aug 11 07:29:54 PM PDT 24 |
2401869680709 ps |
| T840 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2030358109 |
|
|
Aug 11 05:48:25 PM PDT 24 |
Aug 11 05:48:26 PM PDT 24 |
63682020 ps |
| T841 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2716506487 |
|
|
Aug 11 05:45:41 PM PDT 24 |
Aug 11 05:46:00 PM PDT 24 |
430596292 ps |
| T842 |
/workspace/coverage/default/47.sram_ctrl_regwen.3690111015 |
|
|
Aug 11 05:55:07 PM PDT 24 |
Aug 11 05:55:39 PM PDT 24 |
895455254 ps |
| T843 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3790961576 |
|
|
Aug 11 05:47:01 PM PDT 24 |
Aug 11 05:54:53 PM PDT 24 |
16800945052 ps |
| T844 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.569701743 |
|
|
Aug 11 05:55:07 PM PDT 24 |
Aug 11 05:56:01 PM PDT 24 |
29554942095 ps |
| T845 |
/workspace/coverage/default/37.sram_ctrl_executable.3264825849 |
|
|
Aug 11 05:52:47 PM PDT 24 |
Aug 11 06:15:56 PM PDT 24 |
44660774894 ps |
| T846 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.973391291 |
|
|
Aug 11 05:51:50 PM PDT 24 |
Aug 11 05:57:06 PM PDT 24 |
14465269378 ps |
| T847 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.4193455042 |
|
|
Aug 11 05:47:09 PM PDT 24 |
Aug 11 05:49:39 PM PDT 24 |
10589872107 ps |
| T848 |
/workspace/coverage/default/36.sram_ctrl_partial_access.2485943642 |
|
|
Aug 11 05:52:18 PM PDT 24 |
Aug 11 05:52:32 PM PDT 24 |
1953354321 ps |
| T849 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.420830103 |
|
|
Aug 11 05:52:55 PM PDT 24 |
Aug 11 05:53:22 PM PDT 24 |
742947268 ps |
| T850 |
/workspace/coverage/default/7.sram_ctrl_alert_test.4117187488 |
|
|
Aug 11 05:45:30 PM PDT 24 |
Aug 11 05:45:31 PM PDT 24 |
15808610 ps |
| T851 |
/workspace/coverage/default/0.sram_ctrl_smoke.3058322175 |
|
|
Aug 11 05:44:30 PM PDT 24 |
Aug 11 05:44:35 PM PDT 24 |
1041663040 ps |
| T852 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.463345208 |
|
|
Aug 11 05:44:45 PM PDT 24 |
Aug 11 06:08:04 PM PDT 24 |
74504076668 ps |
| T853 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.4129905381 |
|
|
Aug 11 05:52:53 PM PDT 24 |
Aug 11 05:55:24 PM PDT 24 |
9914237685 ps |
| T854 |
/workspace/coverage/default/21.sram_ctrl_smoke.1188793730 |
|
|
Aug 11 05:48:25 PM PDT 24 |
Aug 11 05:48:42 PM PDT 24 |
3220747861 ps |
| T855 |
/workspace/coverage/default/16.sram_ctrl_alert_test.2936627919 |
|
|
Aug 11 05:47:27 PM PDT 24 |
Aug 11 05:47:27 PM PDT 24 |
18432393 ps |
| T856 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3300486240 |
|
|
Aug 11 05:44:41 PM PDT 24 |
Aug 11 05:44:55 PM PDT 24 |
2168024696 ps |
| T857 |
/workspace/coverage/default/18.sram_ctrl_executable.1331127642 |
|
|
Aug 11 05:47:48 PM PDT 24 |
Aug 11 06:05:44 PM PDT 24 |
116548709486 ps |
| T858 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.214456192 |
|
|
Aug 11 05:52:37 PM PDT 24 |
Aug 11 05:52:59 PM PDT 24 |
2036224004 ps |
| T859 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2481314560 |
|
|
Aug 11 05:44:31 PM PDT 24 |
Aug 11 05:48:39 PM PDT 24 |
3787331903 ps |
| T860 |
/workspace/coverage/default/36.sram_ctrl_smoke.1806657668 |
|
|
Aug 11 05:52:17 PM PDT 24 |
Aug 11 05:52:32 PM PDT 24 |
4946696432 ps |
| T861 |
/workspace/coverage/default/32.sram_ctrl_bijection.4265618519 |
|
|
Aug 11 05:51:14 PM PDT 24 |
Aug 11 06:27:07 PM PDT 24 |
478001177983 ps |
| T862 |
/workspace/coverage/default/44.sram_ctrl_partial_access.3213884713 |
|
|
Aug 11 05:54:11 PM PDT 24 |
Aug 11 05:54:33 PM PDT 24 |
1245867171 ps |
| T863 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.692309114 |
|
|
Aug 11 05:49:15 PM PDT 24 |
Aug 11 05:49:19 PM PDT 24 |
383796528 ps |
| T864 |
/workspace/coverage/default/11.sram_ctrl_alert_test.1279195291 |
|
|
Aug 11 05:46:14 PM PDT 24 |
Aug 11 05:46:15 PM PDT 24 |
128821352 ps |
| T865 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2350291562 |
|
|
Aug 11 05:54:37 PM PDT 24 |
Aug 11 05:56:34 PM PDT 24 |
1608921864 ps |
| T866 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.255994472 |
|
|
Aug 11 05:55:31 PM PDT 24 |
Aug 11 05:56:50 PM PDT 24 |
2530294846 ps |
| T867 |
/workspace/coverage/default/33.sram_ctrl_bijection.128462651 |
|
|
Aug 11 05:51:29 PM PDT 24 |
Aug 11 06:11:28 PM PDT 24 |
52675903040 ps |
| T868 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1349493973 |
|
|
Aug 11 05:52:17 PM PDT 24 |
Aug 11 05:59:06 PM PDT 24 |
24722128363 ps |
| T869 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2660088865 |
|
|
Aug 11 05:54:56 PM PDT 24 |
Aug 11 06:01:48 PM PDT 24 |
197486901476 ps |
| T870 |
/workspace/coverage/default/17.sram_ctrl_smoke.3462805946 |
|
|
Aug 11 05:47:29 PM PDT 24 |
Aug 11 05:47:43 PM PDT 24 |
815992159 ps |
| T871 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.2246556643 |
|
|
Aug 11 05:55:06 PM PDT 24 |
Aug 11 05:56:58 PM PDT 24 |
1188302961 ps |
| T872 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.3301938243 |
|
|
Aug 11 05:51:21 PM PDT 24 |
Aug 11 05:56:30 PM PDT 24 |
31492349318 ps |
| T873 |
/workspace/coverage/default/40.sram_ctrl_regwen.3146947797 |
|
|
Aug 11 05:53:19 PM PDT 24 |
Aug 11 06:10:16 PM PDT 24 |
49489688815 ps |
| T874 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.3297942561 |
|
|
Aug 11 05:47:35 PM PDT 24 |
Aug 11 05:47:39 PM PDT 24 |
4213926319 ps |
| T94 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1318612462 |
|
|
Aug 11 05:45:46 PM PDT 24 |
Aug 11 05:46:48 PM PDT 24 |
1020395780 ps |
| T875 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2438063066 |
|
|
Aug 11 05:46:54 PM PDT 24 |
Aug 11 05:47:24 PM PDT 24 |
752519270 ps |
| T876 |
/workspace/coverage/default/1.sram_ctrl_alert_test.2751244020 |
|
|
Aug 11 05:44:49 PM PDT 24 |
Aug 11 05:44:50 PM PDT 24 |
23433234 ps |
| T877 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2267748226 |
|
|
Aug 11 05:48:43 PM PDT 24 |
Aug 11 05:50:05 PM PDT 24 |
37311838774 ps |
| T878 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2103101519 |
|
|
Aug 11 05:44:56 PM PDT 24 |
Aug 11 05:46:07 PM PDT 24 |
788123824 ps |
| T879 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2397876669 |
|
|
Aug 11 05:46:23 PM PDT 24 |
Aug 11 06:34:09 PM PDT 24 |
283885501697 ps |
| T880 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3986297407 |
|
|
Aug 11 05:49:31 PM PDT 24 |
Aug 11 07:17:28 PM PDT 24 |
70765128762 ps |
| T881 |
/workspace/coverage/default/26.sram_ctrl_bijection.3210902710 |
|
|
Aug 11 05:49:42 PM PDT 24 |
Aug 11 06:19:34 PM PDT 24 |
95726939519 ps |
| T882 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1632578880 |
|
|
Aug 11 05:46:26 PM PDT 24 |
Aug 11 05:46:29 PM PDT 24 |
364400828 ps |
| T883 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2512197184 |
|
|
Aug 11 05:53:25 PM PDT 24 |
Aug 11 05:53:29 PM PDT 24 |
1544938131 ps |
| T884 |
/workspace/coverage/default/15.sram_ctrl_bijection.2912266094 |
|
|
Aug 11 05:47:01 PM PDT 24 |
Aug 11 06:17:43 PM PDT 24 |
863985527423 ps |
| T885 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.2011950350 |
|
|
Aug 11 05:53:20 PM PDT 24 |
Aug 11 06:03:38 PM PDT 24 |
29337060821 ps |
| T886 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.715593739 |
|
|
Aug 11 05:45:57 PM PDT 24 |
Aug 11 05:46:01 PM PDT 24 |
349086759 ps |
| T887 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3392278606 |
|
|
Aug 11 05:50:35 PM PDT 24 |
Aug 11 06:03:12 PM PDT 24 |
14050983958 ps |
| T888 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3059623367 |
|
|
Aug 11 05:49:47 PM PDT 24 |
Aug 11 05:50:25 PM PDT 24 |
5911709582 ps |
| T889 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.355091398 |
|
|
Aug 11 05:49:23 PM PDT 24 |
Aug 11 05:52:06 PM PDT 24 |
17543623830 ps |
| T890 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.133422879 |
|
|
Aug 11 05:46:09 PM PDT 24 |
Aug 11 05:46:25 PM PDT 24 |
2096482096 ps |
| T891 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3431818918 |
|
|
Aug 11 05:47:14 PM PDT 24 |
Aug 11 05:49:55 PM PDT 24 |
3124416446 ps |
| T892 |
/workspace/coverage/default/23.sram_ctrl_bijection.1527175794 |
|
|
Aug 11 05:48:57 PM PDT 24 |
Aug 11 06:04:48 PM PDT 24 |
55420639347 ps |
| T893 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3551011977 |
|
|
Aug 11 05:46:09 PM PDT 24 |
Aug 11 05:51:21 PM PDT 24 |
14548600439 ps |
| T894 |
/workspace/coverage/default/10.sram_ctrl_regwen.2042700625 |
|
|
Aug 11 05:45:55 PM PDT 24 |
Aug 11 05:59:05 PM PDT 24 |
14184565544 ps |
| T895 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1548748388 |
|
|
Aug 11 05:47:48 PM PDT 24 |
Aug 11 05:48:04 PM PDT 24 |
1580824271 ps |
| T896 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3062832199 |
|
|
Aug 11 05:45:03 PM PDT 24 |
Aug 11 05:46:21 PM PDT 24 |
12445940742 ps |
| T897 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2913528147 |
|
|
Aug 11 05:55:51 PM PDT 24 |
Aug 11 06:04:03 PM PDT 24 |
85634117198 ps |
| T898 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2503722795 |
|
|
Aug 11 05:49:04 PM PDT 24 |
Aug 11 05:51:00 PM PDT 24 |
3341179675 ps |
| T899 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1395496934 |
|
|
Aug 11 05:48:42 PM PDT 24 |
Aug 11 06:00:10 PM PDT 24 |
19026568841 ps |
| T900 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3930789228 |
|
|
Aug 11 05:55:08 PM PDT 24 |
Aug 11 05:55:11 PM PDT 24 |
1401674073 ps |
| T901 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.1762400722 |
|
|
Aug 11 05:52:04 PM PDT 24 |
Aug 11 05:52:18 PM PDT 24 |
691802500 ps |
| T902 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.828401558 |
|
|
Aug 11 05:49:04 PM PDT 24 |
Aug 11 05:51:53 PM PDT 24 |
18242642976 ps |
| T903 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.4017470234 |
|
|
Aug 11 05:53:18 PM PDT 24 |
Aug 11 05:53:50 PM PDT 24 |
18572490565 ps |
| T904 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.135933877 |
|
|
Aug 11 05:50:18 PM PDT 24 |
Aug 11 05:52:29 PM PDT 24 |
6555607586 ps |
| T905 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2054635576 |
|
|
Aug 11 05:49:30 PM PDT 24 |
Aug 11 05:54:40 PM PDT 24 |
4306454729 ps |
| T906 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.4245761418 |
|
|
Aug 11 05:45:06 PM PDT 24 |
Aug 11 05:47:12 PM PDT 24 |
2058733000 ps |
| T907 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3691134026 |
|
|
Aug 11 05:55:21 PM PDT 24 |
Aug 11 06:07:01 PM PDT 24 |
6109501445 ps |
| T908 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1692370988 |
|
|
Aug 11 05:44:47 PM PDT 24 |
Aug 11 05:49:32 PM PDT 24 |
66425716213 ps |
| T909 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1754443769 |
|
|
Aug 11 05:54:48 PM PDT 24 |
Aug 11 05:58:26 PM PDT 24 |
4381132343 ps |
| T910 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1067740221 |
|
|
Aug 11 05:49:40 PM PDT 24 |
Aug 11 05:54:33 PM PDT 24 |
4273897139 ps |
| T911 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.773440912 |
|
|
Aug 11 05:54:21 PM PDT 24 |
Aug 11 05:54:24 PM PDT 24 |
1408921521 ps |
| T912 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.3258059477 |
|
|
Aug 11 05:51:27 PM PDT 24 |
Aug 11 05:52:10 PM PDT 24 |
3007927904 ps |
| T913 |
/workspace/coverage/default/43.sram_ctrl_stress_all.474709325 |
|
|
Aug 11 05:54:10 PM PDT 24 |
Aug 11 07:25:24 PM PDT 24 |
247200998094 ps |
| T914 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3616085762 |
|
|
Aug 11 05:48:19 PM PDT 24 |
Aug 11 05:49:29 PM PDT 24 |
73751689024 ps |
| T915 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3851900271 |
|
|
Aug 11 05:47:58 PM PDT 24 |
Aug 11 05:49:40 PM PDT 24 |
848725962 ps |
| T916 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1142711559 |
|
|
Aug 11 05:45:34 PM PDT 24 |
Aug 11 05:46:40 PM PDT 24 |
48147655822 ps |
| T917 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1600918767 |
|
|
Aug 11 05:45:36 PM PDT 24 |
Aug 11 05:51:51 PM PDT 24 |
11086882549 ps |
| T918 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1061180060 |
|
|
Aug 11 05:54:16 PM PDT 24 |
Aug 11 06:13:55 PM PDT 24 |
107942807282 ps |
| T919 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.880441026 |
|
|
Aug 11 05:47:35 PM PDT 24 |
Aug 11 06:03:47 PM PDT 24 |
21905127944 ps |
| T920 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1846649385 |
|
|
Aug 11 05:49:16 PM PDT 24 |
Aug 11 05:50:42 PM PDT 24 |
15056488138 ps |
| T921 |
/workspace/coverage/default/6.sram_ctrl_smoke.3256596162 |
|
|
Aug 11 05:45:14 PM PDT 24 |
Aug 11 05:45:36 PM PDT 24 |
4970149048 ps |
| T922 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2116348076 |
|
|
Aug 11 05:52:23 PM PDT 24 |
Aug 11 06:12:00 PM PDT 24 |
15477085984 ps |
| T923 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2602173220 |
|
|
Aug 11 05:55:40 PM PDT 24 |
Aug 11 07:16:34 PM PDT 24 |
313324015551 ps |
| T924 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1398996382 |
|
|
Aug 11 05:48:13 PM PDT 24 |
Aug 11 05:53:15 PM PDT 24 |
5474959612 ps |
| T925 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.1629505705 |
|
|
Aug 11 05:54:18 PM PDT 24 |
Aug 11 05:54:32 PM PDT 24 |
740153844 ps |
| T926 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2760173764 |
|
|
Aug 11 05:44:54 PM PDT 24 |
Aug 11 05:45:01 PM PDT 24 |
687998528 ps |
| T927 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3997639070 |
|
|
Aug 11 05:48:14 PM PDT 24 |
Aug 11 05:51:57 PM PDT 24 |
27260394397 ps |
| T928 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.121780661 |
|
|
Aug 11 05:49:36 PM PDT 24 |
Aug 11 05:54:17 PM PDT 24 |
56294772671 ps |
| T929 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3093930799 |
|
|
Aug 11 05:49:59 PM PDT 24 |
Aug 11 05:50:05 PM PDT 24 |
1390913513 ps |
| T930 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3077086391 |
|
|
Aug 11 05:44:31 PM PDT 24 |
Aug 11 05:53:21 PM PDT 24 |
7998201002 ps |
| T931 |
/workspace/coverage/default/4.sram_ctrl_regwen.3223552374 |
|
|
Aug 11 05:45:05 PM PDT 24 |
Aug 11 05:47:40 PM PDT 24 |
1985011388 ps |
| T932 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2525448305 |
|
|
Aug 11 05:45:17 PM PDT 24 |
Aug 11 05:52:26 PM PDT 24 |
22268015282 ps |
| T933 |
/workspace/coverage/default/37.sram_ctrl_partial_access.4189855875 |
|
|
Aug 11 05:52:42 PM PDT 24 |
Aug 11 05:52:59 PM PDT 24 |
3458061900 ps |
| T934 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1150254660 |
|
|
Aug 11 05:53:43 PM PDT 24 |
Aug 11 05:53:44 PM PDT 24 |
68504202 ps |
| T935 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2600243390 |
|
|
Aug 11 05:54:13 PM PDT 24 |
Aug 11 05:54:17 PM PDT 24 |
1462646101 ps |
| T936 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1930549853 |
|
|
Aug 11 05:54:13 PM PDT 24 |
Aug 11 05:58:36 PM PDT 24 |
3983280773 ps |
| T937 |
/workspace/coverage/default/28.sram_ctrl_stress_all.3480047461 |
|
|
Aug 11 05:50:18 PM PDT 24 |
Aug 11 06:20:40 PM PDT 24 |
73873602333 ps |
| T938 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.131587473 |
|
|
Aug 11 05:54:37 PM PDT 24 |
Aug 11 05:56:18 PM PDT 24 |
115946062012 ps |
| T939 |
/workspace/coverage/default/48.sram_ctrl_bijection.1366196053 |
|
|
Aug 11 05:55:21 PM PDT 24 |
Aug 11 06:11:35 PM PDT 24 |
113073571639 ps |
| T940 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2705392898 |
|
|
Aug 11 05:55:45 PM PDT 24 |
Aug 11 06:00:21 PM PDT 24 |
14744265936 ps |
| T941 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1731978448 |
|
|
Aug 11 05:51:44 PM PDT 24 |
Aug 11 05:51:56 PM PDT 24 |
3684386797 ps |
| T62 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.418901741 |
|
|
Aug 11 05:44:23 PM PDT 24 |
Aug 11 05:44:24 PM PDT 24 |
15744916 ps |
| T942 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4072911846 |
|
|
Aug 11 05:43:55 PM PDT 24 |
Aug 11 05:43:59 PM PDT 24 |
368589600 ps |
| T943 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1591612980 |
|
|
Aug 11 05:44:17 PM PDT 24 |
Aug 11 05:44:21 PM PDT 24 |
1405234879 ps |
| T63 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.557276463 |
|
|
Aug 11 05:44:31 PM PDT 24 |
Aug 11 05:44:32 PM PDT 24 |
92288716 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1009758611 |
|
|
Aug 11 05:44:25 PM PDT 24 |
Aug 11 05:44:27 PM PDT 24 |
52039442 ps |
| T64 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3866172237 |
|
|
Aug 11 05:44:26 PM PDT 24 |
Aug 11 05:44:27 PM PDT 24 |
17062229 ps |
| T59 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2243886819 |
|
|
Aug 11 05:43:21 PM PDT 24 |
Aug 11 05:43:23 PM PDT 24 |
138025107 ps |
| T60 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1967512516 |
|
|
Aug 11 05:44:04 PM PDT 24 |
Aug 11 05:44:05 PM PDT 24 |
115654207 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3680564023 |
|
|
Aug 11 05:43:57 PM PDT 24 |
Aug 11 05:44:49 PM PDT 24 |
14661991207 ps |
| T945 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4274888722 |
|
|
Aug 11 05:44:01 PM PDT 24 |
Aug 11 05:44:06 PM PDT 24 |
247338632 ps |
| T102 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3333433026 |
|
|
Aug 11 05:43:56 PM PDT 24 |
Aug 11 05:43:57 PM PDT 24 |
28566327 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1549937144 |
|
|
Aug 11 05:43:48 PM PDT 24 |
Aug 11 05:43:51 PM PDT 24 |
49660073 ps |
| T61 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2418343885 |
|
|
Aug 11 05:43:36 PM PDT 24 |
Aug 11 05:43:38 PM PDT 24 |
696291044 ps |
| T74 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3873267239 |
|
|
Aug 11 05:44:09 PM PDT 24 |
Aug 11 05:44:10 PM PDT 24 |
27801477 ps |
| T106 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.568167915 |
|
|
Aug 11 05:43:50 PM PDT 24 |
Aug 11 05:43:50 PM PDT 24 |
52966772 ps |
| T75 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.473383216 |
|
|
Aug 11 05:44:17 PM PDT 24 |
Aug 11 05:44:46 PM PDT 24 |
11536632354 ps |
| T132 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3685356602 |
|
|
Aug 11 05:44:18 PM PDT 24 |
Aug 11 05:44:20 PM PDT 24 |
150196755 ps |
| T76 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.901452517 |
|
|
Aug 11 05:43:59 PM PDT 24 |
Aug 11 05:44:53 PM PDT 24 |
28321653015 ps |
| T77 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2611750314 |
|
|
Aug 11 05:44:09 PM PDT 24 |
Aug 11 05:44:10 PM PDT 24 |
19211711 ps |
| T78 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2101959921 |
|
|
Aug 11 05:44:12 PM PDT 24 |
Aug 11 05:44:13 PM PDT 24 |
46825617 ps |
| T129 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1030731625 |
|
|
Aug 11 05:44:03 PM PDT 24 |
Aug 11 05:44:05 PM PDT 24 |
650315138 ps |
| T947 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.931019427 |
|
|
Aug 11 05:44:09 PM PDT 24 |
Aug 11 05:44:13 PM PDT 24 |
133273425 ps |
| T79 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.844610796 |
|
|
Aug 11 05:44:24 PM PDT 24 |
Aug 11 05:45:16 PM PDT 24 |
7781933510 ps |
| T134 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2127023725 |
|
|
Aug 11 05:43:49 PM PDT 24 |
Aug 11 05:43:51 PM PDT 24 |
298106873 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.789569300 |
|
|
Aug 11 05:43:43 PM PDT 24 |
Aug 11 05:43:46 PM PDT 24 |
1773515283 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1245199147 |
|
|
Aug 11 05:44:32 PM PDT 24 |
Aug 11 05:44:36 PM PDT 24 |
44355980 ps |
| T125 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2417226722 |
|
|
Aug 11 05:44:02 PM PDT 24 |
Aug 11 05:44:04 PM PDT 24 |
748179258 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2612876445 |
|
|
Aug 11 05:43:33 PM PDT 24 |
Aug 11 05:43:36 PM PDT 24 |
489631828 ps |
| T80 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4271248416 |
|
|
Aug 11 05:44:30 PM PDT 24 |
Aug 11 05:44:30 PM PDT 24 |
20934074 ps |
| T130 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1410379187 |
|
|
Aug 11 05:43:40 PM PDT 24 |
Aug 11 05:43:43 PM PDT 24 |
680235861 ps |
| T81 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3880572481 |
|
|
Aug 11 05:43:40 PM PDT 24 |
Aug 11 05:43:41 PM PDT 24 |
25975763 ps |
| T951 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.560805024 |
|
|
Aug 11 05:44:11 PM PDT 24 |
Aug 11 05:44:13 PM PDT 24 |
75136699 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1783770171 |
|
|
Aug 11 05:44:31 PM PDT 24 |
Aug 11 05:44:34 PM PDT 24 |
128617840 ps |
| T953 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2428638850 |
|
|
Aug 11 05:44:24 PM PDT 24 |
Aug 11 05:44:27 PM PDT 24 |
1260244384 ps |
| T126 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1272087538 |
|
|
Aug 11 05:44:17 PM PDT 24 |
Aug 11 05:44:19 PM PDT 24 |
83740237 ps |
| T954 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1240673809 |
|
|
Aug 11 05:43:32 PM PDT 24 |
Aug 11 05:43:33 PM PDT 24 |
18415252 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.841700701 |
|
|
Aug 11 05:43:43 PM PDT 24 |
Aug 11 05:43:44 PM PDT 24 |
158410314 ps |
| T956 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3712540035 |
|
|
Aug 11 05:44:03 PM PDT 24 |
Aug 11 05:44:08 PM PDT 24 |
730595693 ps |
| T957 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3100172295 |
|
|
Aug 11 05:43:29 PM PDT 24 |
Aug 11 05:43:30 PM PDT 24 |
45848418 ps |
| T82 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2067943055 |
|
|
Aug 11 05:44:17 PM PDT 24 |
Aug 11 05:44:46 PM PDT 24 |
7613405187 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.210941952 |
|
|
Aug 11 05:43:56 PM PDT 24 |
Aug 11 05:44:50 PM PDT 24 |
14425506575 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3034040617 |
|
|
Aug 11 05:43:36 PM PDT 24 |
Aug 11 05:43:39 PM PDT 24 |
307263420 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2780605561 |
|
|
Aug 11 05:43:40 PM PDT 24 |
Aug 11 05:44:09 PM PDT 24 |
14773158548 ps |
| T135 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1045186627 |
|
|
Aug 11 05:44:31 PM PDT 24 |
Aug 11 05:44:32 PM PDT 24 |
996487190 ps |
| T84 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3846298361 |
|
|
Aug 11 05:44:09 PM PDT 24 |
Aug 11 05:45:02 PM PDT 24 |
7351947060 ps |
| T960 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3003705943 |
|
|
Aug 11 05:44:04 PM PDT 24 |
Aug 11 05:44:07 PM PDT 24 |
490935383 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.974544699 |
|
|
Aug 11 05:43:36 PM PDT 24 |
Aug 11 05:43:39 PM PDT 24 |
355383708 ps |
| T85 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2697447840 |
|
|
Aug 11 05:43:22 PM PDT 24 |
Aug 11 05:44:14 PM PDT 24 |
7264770100 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3037971043 |
|
|
Aug 11 05:43:58 PM PDT 24 |
Aug 11 05:43:59 PM PDT 24 |
12169246 ps |
| T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1754211054 |
|
|
Aug 11 05:43:48 PM PDT 24 |
Aug 11 05:43:49 PM PDT 24 |
30385508 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4273540516 |
|
|
Aug 11 05:43:56 PM PDT 24 |
Aug 11 05:44:01 PM PDT 24 |
1264206066 ps |
| T964 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2584622914 |
|
|
Aug 11 05:44:04 PM PDT 24 |
Aug 11 05:44:06 PM PDT 24 |
101505331 ps |
| T965 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2817720575 |
|
|
Aug 11 05:43:35 PM PDT 24 |
Aug 11 05:43:36 PM PDT 24 |
40907862 ps |
| T87 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1714393251 |
|
|
Aug 11 05:43:58 PM PDT 24 |
Aug 11 05:43:58 PM PDT 24 |
95200750 ps |
| T966 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4054976100 |
|
|
Aug 11 05:44:23 PM PDT 24 |
Aug 11 05:44:27 PM PDT 24 |
139470551 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3228132761 |
|
|
Aug 11 05:43:34 PM PDT 24 |
Aug 11 05:43:38 PM PDT 24 |
404120044 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.91617599 |
|
|
Aug 11 05:44:03 PM PDT 24 |
Aug 11 05:44:07 PM PDT 24 |
2607653157 ps |
| T969 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.521937634 |
|
|
Aug 11 05:44:04 PM PDT 24 |
Aug 11 05:44:05 PM PDT 24 |
29506171 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2940550114 |
|
|
Aug 11 05:44:04 PM PDT 24 |
Aug 11 05:44:05 PM PDT 24 |
30167910 ps |
| T99 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1615271522 |
|
|
Aug 11 05:44:12 PM PDT 24 |
Aug 11 05:44:13 PM PDT 24 |
31813637 ps |
| T95 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1392841330 |
|
|
Aug 11 05:44:02 PM PDT 24 |
Aug 11 05:44:03 PM PDT 24 |
23734113 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2788995177 |
|
|
Aug 11 05:43:21 PM PDT 24 |
Aug 11 05:43:22 PM PDT 24 |
65542366 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1363082960 |
|
|
Aug 11 05:44:01 PM PDT 24 |
Aug 11 05:44:02 PM PDT 24 |
39779436 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.966576482 |
|
|
Aug 11 05:44:30 PM PDT 24 |
Aug 11 05:44:33 PM PDT 24 |
388657007 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3490263826 |
|
|
Aug 11 05:43:41 PM PDT 24 |
Aug 11 05:43:42 PM PDT 24 |
73343551 ps |
| T975 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3680677715 |
|
|
Aug 11 05:43:53 PM PDT 24 |
Aug 11 05:43:54 PM PDT 24 |
12891137 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2534703468 |
|
|
Aug 11 05:43:49 PM PDT 24 |
Aug 11 05:43:50 PM PDT 24 |
12562303 ps |
| T977 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.146987980 |
|
|
Aug 11 05:44:09 PM PDT 24 |
Aug 11 05:44:14 PM PDT 24 |
2111932351 ps |
| T127 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1031810622 |
|
|
Aug 11 05:44:12 PM PDT 24 |
Aug 11 05:44:15 PM PDT 24 |
3108917694 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1607107513 |
|
|
Aug 11 05:44:14 PM PDT 24 |
Aug 11 05:44:15 PM PDT 24 |
17314878 ps |
| T96 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.850130509 |
|
|
Aug 11 05:44:25 PM PDT 24 |
Aug 11 05:44:50 PM PDT 24 |
3721704191 ps |
| T979 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.638006983 |
|
|
Aug 11 05:44:27 PM PDT 24 |
Aug 11 05:44:31 PM PDT 24 |
1430300978 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3126169469 |
|
|
Aug 11 05:44:24 PM PDT 24 |
Aug 11 05:44:25 PM PDT 24 |
26697166 ps |
| T97 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3212033541 |
|
|
Aug 11 05:44:09 PM PDT 24 |
Aug 11 05:44:40 PM PDT 24 |
14773222684 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.30112708 |
|
|
Aug 11 05:43:44 PM PDT 24 |
Aug 11 05:43:46 PM PDT 24 |
68804576 ps |
| T131 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3636078003 |
|
|
Aug 11 05:43:57 PM PDT 24 |
Aug 11 05:43:59 PM PDT 24 |
228724278 ps |
| T982 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1791127321 |
|
|
Aug 11 05:43:56 PM PDT 24 |
Aug 11 05:44:00 PM PDT 24 |
124442214 ps |
| T983 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4077956468 |
|
|
Aug 11 05:44:01 PM PDT 24 |
Aug 11 05:44:02 PM PDT 24 |
15257419 ps |
| T984 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2453749319 |
|
|
Aug 11 05:44:16 PM PDT 24 |
Aug 11 05:44:17 PM PDT 24 |
36235666 ps |
| T985 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3657349653 |
|
|
Aug 11 05:44:10 PM PDT 24 |
Aug 11 05:44:14 PM PDT 24 |
363168281 ps |
| T986 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4055395752 |
|
|
Aug 11 05:44:18 PM PDT 24 |
Aug 11 05:44:18 PM PDT 24 |
50437928 ps |
| T136 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3597439246 |
|
|
Aug 11 05:43:34 PM PDT 24 |
Aug 11 05:43:37 PM PDT 24 |
262872235 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.824771521 |
|
|
Aug 11 05:43:34 PM PDT 24 |
Aug 11 05:43:35 PM PDT 24 |
44667880 ps |
| T988 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1976105108 |
|
|
Aug 11 05:43:21 PM PDT 24 |
Aug 11 05:43:22 PM PDT 24 |
25219120 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.96643340 |
|
|
Aug 11 05:43:19 PM PDT 24 |
Aug 11 05:43:20 PM PDT 24 |
70555693 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2051248130 |
|
|
Aug 11 05:43:37 PM PDT 24 |
Aug 11 05:43:37 PM PDT 24 |
53447282 ps |
| T100 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3436825813 |
|
|
Aug 11 05:43:50 PM PDT 24 |
Aug 11 05:44:16 PM PDT 24 |
3907249572 ps |
| T990 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2764469186 |
|
|
Aug 11 05:44:30 PM PDT 24 |
Aug 11 05:44:34 PM PDT 24 |
1178159641 ps |
| T991 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1787678000 |
|
|
Aug 11 05:44:02 PM PDT 24 |
Aug 11 05:44:04 PM PDT 24 |
78194914 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3619347201 |
|
|
Aug 11 05:43:49 PM PDT 24 |
Aug 11 05:43:50 PM PDT 24 |
17173752 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3613663261 |
|
|
Aug 11 05:44:06 PM PDT 24 |
Aug 11 05:44:34 PM PDT 24 |
18434130029 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4065546226 |
|
|
Aug 11 05:43:41 PM PDT 24 |
Aug 11 05:43:45 PM PDT 24 |
1314475273 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2223884902 |
|
|
Aug 11 05:43:21 PM PDT 24 |
Aug 11 05:43:24 PM PDT 24 |
1627833367 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.288435315 |
|
|
Aug 11 05:44:24 PM PDT 24 |
Aug 11 05:44:25 PM PDT 24 |
35161430 ps |
| T997 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1823758906 |
|
|
Aug 11 05:43:49 PM PDT 24 |
Aug 11 05:43:52 PM PDT 24 |
511354179 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2902309135 |
|
|
Aug 11 05:43:21 PM PDT 24 |
Aug 11 05:44:00 PM PDT 24 |
73728294209 ps |
| T999 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3789646192 |
|
|
Aug 11 05:44:26 PM PDT 24 |
Aug 11 05:44:26 PM PDT 24 |
26754627 ps |
| T133 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1837457889 |
|
|
Aug 11 05:43:54 PM PDT 24 |
Aug 11 05:43:57 PM PDT 24 |
611471351 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3065521959 |
|
|
Aug 11 05:43:28 PM PDT 24 |
Aug 11 05:44:18 PM PDT 24 |
29568942155 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1293623770 |
|
|
Aug 11 05:43:48 PM PDT 24 |
Aug 11 05:43:52 PM PDT 24 |
1427153175 ps |
| T1002 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.123363112 |
|
|
Aug 11 05:43:46 PM PDT 24 |
Aug 11 05:43:47 PM PDT 24 |
56102687 ps |
| T1003 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.949187808 |
|
|
Aug 11 05:44:03 PM PDT 24 |
Aug 11 05:44:05 PM PDT 24 |
47322478 ps |