Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	356398666	1			T1	17012		T2	267070		T3	196606
instr_valid_dis	307990646	1			T1	17012		T2	120886		T3	196606
instr_en	31333869	1			T2	55542		T11	207140		T12	61418

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13927192	1			T2	20000		T11	65456		T12	106778
sram_ifetch_valid_disable	314708484	1			T1	17012		T2	154086		T3	196606
sram_ifetch_enable	27762990	1			T2	92984		T11	145178		T12	25078

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	356398666	1			T1	17012		T2	267070		T3	196606
hw_debug_en_valid_off	318056842	1			T1	17012		T2	131136		T3	196606
hw_debug_en_on	23962384	1			T2	69012		T11	73706		T12	44

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	314708484	1			T1	17012		T2	154086		T3	196606
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	294164718	1			T1	17012		T2	115822		T3	196606
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	15183365	1			T2	94		T11	71262		T12	1866
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	8511732	1			T12	106778		T29	78042		T20	91088
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1750400	1			T12	18834		T20	91088		T25	14548
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	5709938	1			T12	52808		T29	78042		T25	6970
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3647164	1			T2	20000		T11	27354		T20	37364
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1533220	1			T20	37364		T25	19894		T66	92864
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1444012	1			T2	20000		T11	27354		T69	39774
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9824176	1			T2	49012		T11	36298		T29	33506
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3719896	1			T2	21692		T20	81276		T25	878906
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3801884	1			T2	94		T11	36298		T29	33506

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8250432	1			T2	35448		T11	108524		T12	6744
lc_exec_en	10491044	1			T11	10054		T12	44		T29	59544
valid_exec_dis	306550110	1			T1	17012		T2	43216		T3	196606
invalid_exec_dis	41690182	1			T2	112984		T11	210634		T12	131856