Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	147626343	1			T1	1613		T2	58056		T3	98303
triple_byte_access	2891286	1			T1	1358		T2	1197		T4	2919
halfword_access	4423541	1			T1	2044		T2	1762		T4	4416
byte_access	6153547	1			T1	2775		T2	2316		T4	5865
zero_access	1826490	1			T1	716		T2	580		T4	1429

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81279699

1

T1

4295

T2

37100

T3

32768

auto[1]

81641508

1

T1

4211

T2

26811

T3

65535

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	73505007	1			T1	787		T2	33641		T3	32768
auto[0]	triple_byte_access	1386924	1			T1	689		T2	687		T4	1473
auto[0]	halfword_access	2167913	1			T1	1050		T2	1072		T4	2216
auto[0]	byte_access	3144244	1			T1	1400		T2	1365		T4	2945
auto[0]	zero_access	1075611	1			T1	369		T2	335		T4	751
auto[1]	word_access	74121336	1			T1	826		T2	24415		T3	65535
auto[1]	triple_byte_access	1504362	1			T1	669		T2	510		T4	1446
auto[1]	halfword_access	2255628	1			T1	994		T2	690		T4	2200
auto[1]	byte_access	3009303	1			T1	1375		T2	951		T4	2920
auto[1]	zero_access	750879	1			T1	347		T2	245		T4	678