| T795 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3211232068 |
|
|
Aug 12 05:40:43 PM PDT 24 |
Aug 12 05:41:15 PM PDT 24 |
1944096264 ps |
| T796 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3638466219 |
|
|
Aug 12 05:39:19 PM PDT 24 |
Aug 12 05:39:23 PM PDT 24 |
703126204 ps |
| T797 |
/workspace/coverage/default/19.sram_ctrl_bijection.3938431458 |
|
|
Aug 12 05:39:55 PM PDT 24 |
Aug 12 05:57:21 PM PDT 24 |
70271966023 ps |
| T798 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.3325265269 |
|
|
Aug 12 05:41:06 PM PDT 24 |
Aug 12 05:42:47 PM PDT 24 |
16943498969 ps |
| T799 |
/workspace/coverage/default/19.sram_ctrl_alert_test.210176000 |
|
|
Aug 12 05:39:58 PM PDT 24 |
Aug 12 05:39:59 PM PDT 24 |
15079816 ps |
| T800 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.4105674838 |
|
|
Aug 12 05:39:09 PM PDT 24 |
Aug 12 05:45:29 PM PDT 24 |
6079393270 ps |
| T801 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1701523342 |
|
|
Aug 12 05:39:38 PM PDT 24 |
Aug 12 05:41:00 PM PDT 24 |
1740112945 ps |
| T802 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1948603956 |
|
|
Aug 12 05:40:51 PM PDT 24 |
Aug 12 06:38:51 PM PDT 24 |
46312276223 ps |
| T803 |
/workspace/coverage/default/9.sram_ctrl_bijection.832517652 |
|
|
Aug 12 05:39:43 PM PDT 24 |
Aug 12 05:59:15 PM PDT 24 |
16571646738 ps |
| T804 |
/workspace/coverage/default/27.sram_ctrl_regwen.2276050739 |
|
|
Aug 12 05:39:56 PM PDT 24 |
Aug 12 05:45:35 PM PDT 24 |
5556183470 ps |
| T805 |
/workspace/coverage/default/25.sram_ctrl_executable.2533821638 |
|
|
Aug 12 05:40:11 PM PDT 24 |
Aug 12 05:54:30 PM PDT 24 |
24185144676 ps |
| T806 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1242596888 |
|
|
Aug 12 05:41:01 PM PDT 24 |
Aug 12 05:42:30 PM PDT 24 |
2727658736 ps |
| T807 |
/workspace/coverage/default/26.sram_ctrl_bijection.2723134661 |
|
|
Aug 12 05:40:09 PM PDT 24 |
Aug 12 06:28:40 PM PDT 24 |
792944328247 ps |
| T808 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.2050942742 |
|
|
Aug 12 05:40:51 PM PDT 24 |
Aug 12 05:42:00 PM PDT 24 |
827085983 ps |
| T809 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.53185521 |
|
|
Aug 12 05:39:13 PM PDT 24 |
Aug 12 05:40:21 PM PDT 24 |
882932466 ps |
| T810 |
/workspace/coverage/default/3.sram_ctrl_bijection.1995646897 |
|
|
Aug 12 05:39:11 PM PDT 24 |
Aug 12 05:52:46 PM PDT 24 |
13242614267 ps |
| T811 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.3361921582 |
|
|
Aug 12 05:41:30 PM PDT 24 |
Aug 12 05:42:13 PM PDT 24 |
2882858407 ps |
| T812 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3861004246 |
|
|
Aug 12 05:41:41 PM PDT 24 |
Aug 12 05:45:57 PM PDT 24 |
13762909908 ps |
| T813 |
/workspace/coverage/default/0.sram_ctrl_smoke.380075673 |
|
|
Aug 12 05:38:57 PM PDT 24 |
Aug 12 05:41:23 PM PDT 24 |
473878007 ps |
| T814 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.2697359914 |
|
|
Aug 12 05:39:58 PM PDT 24 |
Aug 12 05:42:15 PM PDT 24 |
12939243795 ps |
| T815 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.917021209 |
|
|
Aug 12 05:39:22 PM PDT 24 |
Aug 12 05:43:15 PM PDT 24 |
8721124408 ps |
| T816 |
/workspace/coverage/default/49.sram_ctrl_executable.3636053354 |
|
|
Aug 12 05:42:05 PM PDT 24 |
Aug 12 06:06:24 PM PDT 24 |
26760130880 ps |
| T817 |
/workspace/coverage/default/24.sram_ctrl_bijection.3649400674 |
|
|
Aug 12 05:40:01 PM PDT 24 |
Aug 12 06:25:25 PM PDT 24 |
191747656659 ps |
| T818 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3302387657 |
|
|
Aug 12 05:39:18 PM PDT 24 |
Aug 12 05:39:18 PM PDT 24 |
95765291 ps |
| T819 |
/workspace/coverage/default/38.sram_ctrl_bijection.4003770991 |
|
|
Aug 12 05:40:51 PM PDT 24 |
Aug 12 06:00:44 PM PDT 24 |
18295545360 ps |
| T820 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.646761695 |
|
|
Aug 12 05:39:07 PM PDT 24 |
Aug 12 05:40:59 PM PDT 24 |
64232049471 ps |
| T821 |
/workspace/coverage/default/22.sram_ctrl_regwen.2040021572 |
|
|
Aug 12 05:39:55 PM PDT 24 |
Aug 12 05:59:06 PM PDT 24 |
239185214515 ps |
| T822 |
/workspace/coverage/default/13.sram_ctrl_partial_access.627354583 |
|
|
Aug 12 05:39:19 PM PDT 24 |
Aug 12 05:39:26 PM PDT 24 |
616337648 ps |
| T823 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2528776601 |
|
|
Aug 12 05:41:25 PM PDT 24 |
Aug 12 05:49:33 PM PDT 24 |
81759070846 ps |
| T824 |
/workspace/coverage/default/2.sram_ctrl_executable.2628235895 |
|
|
Aug 12 05:39:12 PM PDT 24 |
Aug 12 05:48:37 PM PDT 24 |
17694375735 ps |
| T825 |
/workspace/coverage/default/18.sram_ctrl_smoke.1430203341 |
|
|
Aug 12 05:39:42 PM PDT 24 |
Aug 12 05:41:04 PM PDT 24 |
4691670845 ps |
| T826 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.457111721 |
|
|
Aug 12 05:41:30 PM PDT 24 |
Aug 12 05:42:58 PM PDT 24 |
9808762940 ps |
| T827 |
/workspace/coverage/default/37.sram_ctrl_regwen.610941276 |
|
|
Aug 12 05:40:45 PM PDT 24 |
Aug 12 06:08:20 PM PDT 24 |
12345797623 ps |
| T828 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3340659568 |
|
|
Aug 12 05:40:03 PM PDT 24 |
Aug 12 05:40:07 PM PDT 24 |
6668204928 ps |
| T829 |
/workspace/coverage/default/36.sram_ctrl_partial_access.2613523315 |
|
|
Aug 12 05:40:43 PM PDT 24 |
Aug 12 05:40:56 PM PDT 24 |
2004714901 ps |
| T830 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1378985369 |
|
|
Aug 12 05:40:12 PM PDT 24 |
Aug 12 05:42:40 PM PDT 24 |
7785577637 ps |
| T831 |
/workspace/coverage/default/49.sram_ctrl_bijection.483585865 |
|
|
Aug 12 05:42:04 PM PDT 24 |
Aug 12 06:23:15 PM PDT 24 |
144853101362 ps |
| T832 |
/workspace/coverage/default/24.sram_ctrl_executable.1330862177 |
|
|
Aug 12 05:39:50 PM PDT 24 |
Aug 12 05:54:16 PM PDT 24 |
13436841726 ps |
| T833 |
/workspace/coverage/default/14.sram_ctrl_alert_test.102975025 |
|
|
Aug 12 05:39:40 PM PDT 24 |
Aug 12 05:39:41 PM PDT 24 |
18497117 ps |
| T834 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3543975615 |
|
|
Aug 12 05:39:26 PM PDT 24 |
Aug 12 05:46:18 PM PDT 24 |
11472776773 ps |
| T835 |
/workspace/coverage/default/25.sram_ctrl_smoke.2540207523 |
|
|
Aug 12 05:40:06 PM PDT 24 |
Aug 12 05:40:14 PM PDT 24 |
11439167214 ps |
| T836 |
/workspace/coverage/default/30.sram_ctrl_smoke.993208862 |
|
|
Aug 12 05:40:08 PM PDT 24 |
Aug 12 05:40:51 PM PDT 24 |
1438936279 ps |
| T837 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.1798084763 |
|
|
Aug 12 05:40:09 PM PDT 24 |
Aug 12 05:40:34 PM PDT 24 |
13513375307 ps |
| T838 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.760066648 |
|
|
Aug 12 05:40:53 PM PDT 24 |
Aug 12 05:47:29 PM PDT 24 |
5934002323 ps |
| T839 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1566925152 |
|
|
Aug 12 05:41:10 PM PDT 24 |
Aug 12 05:43:45 PM PDT 24 |
2741330428 ps |
| T840 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.546387047 |
|
|
Aug 12 05:40:44 PM PDT 24 |
Aug 12 05:44:26 PM PDT 24 |
12868001741 ps |
| T841 |
/workspace/coverage/default/41.sram_ctrl_smoke.1473755260 |
|
|
Aug 12 05:41:10 PM PDT 24 |
Aug 12 05:43:45 PM PDT 24 |
1325287692 ps |
| T842 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3037404637 |
|
|
Aug 12 05:39:21 PM PDT 24 |
Aug 12 06:35:14 PM PDT 24 |
147511558773 ps |
| T843 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.368710276 |
|
|
Aug 12 05:40:53 PM PDT 24 |
Aug 12 05:42:10 PM PDT 24 |
2461311944 ps |
| T844 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3113149404 |
|
|
Aug 12 05:39:48 PM PDT 24 |
Aug 12 05:40:22 PM PDT 24 |
3094519239 ps |
| T845 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2338802460 |
|
|
Aug 12 05:42:09 PM PDT 24 |
Aug 12 05:47:31 PM PDT 24 |
59982827395 ps |
| T846 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2934742649 |
|
|
Aug 12 05:39:23 PM PDT 24 |
Aug 12 05:46:00 PM PDT 24 |
12042661844 ps |
| T847 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.75992425 |
|
|
Aug 12 05:40:59 PM PDT 24 |
Aug 12 05:41:46 PM PDT 24 |
3094655707 ps |
| T848 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2400258091 |
|
|
Aug 12 05:40:07 PM PDT 24 |
Aug 12 05:44:34 PM PDT 24 |
16831190163 ps |
| T849 |
/workspace/coverage/default/46.sram_ctrl_partial_access.17121773 |
|
|
Aug 12 05:41:38 PM PDT 24 |
Aug 12 05:41:44 PM PDT 24 |
612147632 ps |
| T850 |
/workspace/coverage/default/8.sram_ctrl_partial_access.1786365372 |
|
|
Aug 12 05:39:41 PM PDT 24 |
Aug 12 05:39:52 PM PDT 24 |
842525489 ps |
| T851 |
/workspace/coverage/default/35.sram_ctrl_smoke.1538221138 |
|
|
Aug 12 05:40:36 PM PDT 24 |
Aug 12 05:40:54 PM PDT 24 |
1199618925 ps |
| T852 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1448185987 |
|
|
Aug 12 05:40:37 PM PDT 24 |
Aug 12 05:45:41 PM PDT 24 |
10721032414 ps |
| T853 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3964794478 |
|
|
Aug 12 05:39:13 PM PDT 24 |
Aug 12 05:39:14 PM PDT 24 |
55531859 ps |
| T854 |
/workspace/coverage/default/6.sram_ctrl_executable.2615361724 |
|
|
Aug 12 05:39:14 PM PDT 24 |
Aug 12 05:57:10 PM PDT 24 |
62269537422 ps |
| T855 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.555210330 |
|
|
Aug 12 05:39:47 PM PDT 24 |
Aug 12 05:39:51 PM PDT 24 |
1259555697 ps |
| T856 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1680568991 |
|
|
Aug 12 05:39:25 PM PDT 24 |
Aug 12 05:40:47 PM PDT 24 |
3201017839 ps |
| T857 |
/workspace/coverage/default/28.sram_ctrl_regwen.4116183241 |
|
|
Aug 12 05:39:59 PM PDT 24 |
Aug 12 05:44:41 PM PDT 24 |
20437724321 ps |
| T858 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1907261930 |
|
|
Aug 12 05:40:52 PM PDT 24 |
Aug 12 05:42:19 PM PDT 24 |
31908166853 ps |
| T859 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2487669574 |
|
|
Aug 12 05:39:24 PM PDT 24 |
Aug 12 05:42:29 PM PDT 24 |
2141423750 ps |
| T860 |
/workspace/coverage/default/22.sram_ctrl_bijection.601212759 |
|
|
Aug 12 05:39:56 PM PDT 24 |
Aug 12 06:12:22 PM PDT 24 |
652610324680 ps |
| T861 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.260565118 |
|
|
Aug 12 05:39:47 PM PDT 24 |
Aug 12 05:41:55 PM PDT 24 |
2189831357 ps |
| T862 |
/workspace/coverage/default/35.sram_ctrl_partial_access.4145941742 |
|
|
Aug 12 05:40:39 PM PDT 24 |
Aug 12 05:41:11 PM PDT 24 |
761156488 ps |
| T863 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2779315721 |
|
|
Aug 12 05:39:42 PM PDT 24 |
Aug 12 06:12:50 PM PDT 24 |
19645267045 ps |
| T864 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.146694043 |
|
|
Aug 12 05:41:41 PM PDT 24 |
Aug 12 05:44:27 PM PDT 24 |
6920830160 ps |
| T865 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3662937725 |
|
|
Aug 12 05:40:05 PM PDT 24 |
Aug 12 05:41:05 PM PDT 24 |
1814394407 ps |
| T866 |
/workspace/coverage/default/40.sram_ctrl_regwen.320577881 |
|
|
Aug 12 05:41:03 PM PDT 24 |
Aug 12 05:57:38 PM PDT 24 |
44920404232 ps |
| T867 |
/workspace/coverage/default/29.sram_ctrl_stress_all.4080977582 |
|
|
Aug 12 05:40:08 PM PDT 24 |
Aug 12 06:50:22 PM PDT 24 |
210167176097 ps |
| T868 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.548646716 |
|
|
Aug 12 05:40:10 PM PDT 24 |
Aug 12 05:40:21 PM PDT 24 |
5271306292 ps |
| T869 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2838189976 |
|
|
Aug 12 05:39:36 PM PDT 24 |
Aug 12 05:39:40 PM PDT 24 |
1168130397 ps |
| T870 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1179224348 |
|
|
Aug 12 05:41:18 PM PDT 24 |
Aug 12 05:47:13 PM PDT 24 |
29193960544 ps |
| T871 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.1486022456 |
|
|
Aug 12 05:40:13 PM PDT 24 |
Aug 12 06:03:52 PM PDT 24 |
54214119402 ps |
| T872 |
/workspace/coverage/default/17.sram_ctrl_stress_all.707762292 |
|
|
Aug 12 05:39:38 PM PDT 24 |
Aug 12 06:50:31 PM PDT 24 |
38070855943 ps |
| T873 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1047575894 |
|
|
Aug 12 05:39:38 PM PDT 24 |
Aug 12 07:50:05 PM PDT 24 |
248261404447 ps |
| T874 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.1089417502 |
|
|
Aug 12 05:40:01 PM PDT 24 |
Aug 12 05:40:04 PM PDT 24 |
398204302 ps |
| T875 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.2666351092 |
|
|
Aug 12 05:40:52 PM PDT 24 |
Aug 12 05:58:42 PM PDT 24 |
29154559594 ps |
| T876 |
/workspace/coverage/default/9.sram_ctrl_smoke.3428459198 |
|
|
Aug 12 05:39:13 PM PDT 24 |
Aug 12 05:39:42 PM PDT 24 |
654306743 ps |
| T877 |
/workspace/coverage/default/45.sram_ctrl_smoke.720993213 |
|
|
Aug 12 05:41:28 PM PDT 24 |
Aug 12 05:41:35 PM PDT 24 |
698391088 ps |
| T878 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.214565279 |
|
|
Aug 12 05:39:38 PM PDT 24 |
Aug 12 05:40:21 PM PDT 24 |
7496217180 ps |
| T879 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3538452477 |
|
|
Aug 12 05:40:44 PM PDT 24 |
Aug 12 05:41:43 PM PDT 24 |
20756145870 ps |
| T880 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3775864213 |
|
|
Aug 12 05:39:59 PM PDT 24 |
Aug 12 05:56:52 PM PDT 24 |
18953302500 ps |
| T881 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1756673863 |
|
|
Aug 12 05:39:53 PM PDT 24 |
Aug 12 05:44:25 PM PDT 24 |
17570639948 ps |
| T882 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.292588610 |
|
|
Aug 12 05:39:57 PM PDT 24 |
Aug 12 05:42:00 PM PDT 24 |
7904157116 ps |
| T883 |
/workspace/coverage/default/46.sram_ctrl_stress_all.750835729 |
|
|
Aug 12 05:41:50 PM PDT 24 |
Aug 12 06:42:43 PM PDT 24 |
422892957450 ps |
| T884 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.4274342409 |
|
|
Aug 12 05:39:27 PM PDT 24 |
Aug 12 05:39:45 PM PDT 24 |
1399983256 ps |
| T885 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1597116771 |
|
|
Aug 12 05:41:25 PM PDT 24 |
Aug 12 05:41:48 PM PDT 24 |
724744037 ps |
| T886 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3123886362 |
|
|
Aug 12 05:41:29 PM PDT 24 |
Aug 12 05:41:33 PM PDT 24 |
1372554012 ps |
| T887 |
/workspace/coverage/default/41.sram_ctrl_executable.364901679 |
|
|
Aug 12 05:41:08 PM PDT 24 |
Aug 12 05:58:53 PM PDT 24 |
23669228834 ps |
| T888 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.741820449 |
|
|
Aug 12 05:39:57 PM PDT 24 |
Aug 12 05:40:01 PM PDT 24 |
351623032 ps |
| T889 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3648660632 |
|
|
Aug 12 05:39:53 PM PDT 24 |
Aug 12 05:48:23 PM PDT 24 |
20228755591 ps |
| T890 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4273276694 |
|
|
Aug 12 05:39:16 PM PDT 24 |
Aug 12 05:39:54 PM PDT 24 |
1254006108 ps |
| T891 |
/workspace/coverage/default/19.sram_ctrl_smoke.3183977283 |
|
|
Aug 12 05:39:40 PM PDT 24 |
Aug 12 05:39:57 PM PDT 24 |
524014376 ps |
| T892 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.975554836 |
|
|
Aug 12 05:39:44 PM PDT 24 |
Aug 12 05:40:05 PM PDT 24 |
9974475646 ps |
| T893 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.563560414 |
|
|
Aug 12 05:41:00 PM PDT 24 |
Aug 12 05:41:04 PM PDT 24 |
1969996778 ps |
| T894 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.625131746 |
|
|
Aug 12 05:39:40 PM PDT 24 |
Aug 12 05:41:10 PM PDT 24 |
787819501 ps |
| T895 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3001627468 |
|
|
Aug 12 05:41:55 PM PDT 24 |
Aug 12 05:41:56 PM PDT 24 |
16568755 ps |
| T896 |
/workspace/coverage/default/17.sram_ctrl_regwen.387244652 |
|
|
Aug 12 05:40:00 PM PDT 24 |
Aug 12 05:58:49 PM PDT 24 |
31646794339 ps |
| T897 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1214464837 |
|
|
Aug 12 05:41:01 PM PDT 24 |
Aug 12 05:41:02 PM PDT 24 |
11066158 ps |
| T898 |
/workspace/coverage/default/35.sram_ctrl_alert_test.939130215 |
|
|
Aug 12 05:40:37 PM PDT 24 |
Aug 12 05:40:38 PM PDT 24 |
11873354 ps |
| T899 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.768269661 |
|
|
Aug 12 05:39:44 PM PDT 24 |
Aug 12 05:39:59 PM PDT 24 |
1336600558 ps |
| T900 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3782399365 |
|
|
Aug 12 05:39:24 PM PDT 24 |
Aug 12 05:39:32 PM PDT 24 |
2924048662 ps |
| T901 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3192124457 |
|
|
Aug 12 05:40:30 PM PDT 24 |
Aug 12 05:40:45 PM PDT 24 |
924290931 ps |
| T902 |
/workspace/coverage/default/33.sram_ctrl_smoke.2912813944 |
|
|
Aug 12 05:40:23 PM PDT 24 |
Aug 12 05:40:28 PM PDT 24 |
408357504 ps |
| T903 |
/workspace/coverage/default/16.sram_ctrl_bijection.3336021593 |
|
|
Aug 12 05:39:28 PM PDT 24 |
Aug 12 06:21:03 PM PDT 24 |
498515833987 ps |
| T904 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.773212367 |
|
|
Aug 12 05:41:02 PM PDT 24 |
Aug 12 05:41:06 PM PDT 24 |
1350620562 ps |
| T905 |
/workspace/coverage/default/40.sram_ctrl_smoke.3329772525 |
|
|
Aug 12 05:41:04 PM PDT 24 |
Aug 12 05:41:12 PM PDT 24 |
1723491792 ps |
| T906 |
/workspace/coverage/default/26.sram_ctrl_partial_access.826216250 |
|
|
Aug 12 05:39:58 PM PDT 24 |
Aug 12 05:40:25 PM PDT 24 |
1260797290 ps |
| T907 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2921619561 |
|
|
Aug 12 05:40:21 PM PDT 24 |
Aug 12 05:40:56 PM PDT 24 |
1968773168 ps |
| T908 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2930679110 |
|
|
Aug 12 05:40:08 PM PDT 24 |
Aug 12 05:47:49 PM PDT 24 |
75875784157 ps |
| T909 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2756668524 |
|
|
Aug 12 05:41:19 PM PDT 24 |
Aug 12 05:42:52 PM PDT 24 |
2788755214 ps |
| T910 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1700752618 |
|
|
Aug 12 05:40:10 PM PDT 24 |
Aug 12 05:40:13 PM PDT 24 |
1401138757 ps |
| T911 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2050464753 |
|
|
Aug 12 05:41:50 PM PDT 24 |
Aug 12 05:42:06 PM PDT 24 |
840697688 ps |
| T912 |
/workspace/coverage/default/27.sram_ctrl_alert_test.145981481 |
|
|
Aug 12 05:40:03 PM PDT 24 |
Aug 12 05:40:04 PM PDT 24 |
21659670 ps |
| T913 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1455985097 |
|
|
Aug 12 05:40:51 PM PDT 24 |
Aug 12 05:43:46 PM PDT 24 |
10343958703 ps |
| T914 |
/workspace/coverage/default/28.sram_ctrl_partial_access.312463523 |
|
|
Aug 12 05:40:12 PM PDT 24 |
Aug 12 05:40:19 PM PDT 24 |
2710440764 ps |
| T915 |
/workspace/coverage/default/8.sram_ctrl_stress_all.4153967581 |
|
|
Aug 12 05:39:26 PM PDT 24 |
Aug 12 07:19:59 PM PDT 24 |
263845725689 ps |
| T916 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.4016347075 |
|
|
Aug 12 05:40:36 PM PDT 24 |
Aug 12 05:41:57 PM PDT 24 |
1561273843 ps |
| T917 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2721778946 |
|
|
Aug 12 05:40:22 PM PDT 24 |
Aug 12 05:59:47 PM PDT 24 |
11718418698 ps |
| T918 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2659698060 |
|
|
Aug 12 05:39:03 PM PDT 24 |
Aug 12 05:39:06 PM PDT 24 |
360614358 ps |
| T919 |
/workspace/coverage/default/35.sram_ctrl_regwen.4170094288 |
|
|
Aug 12 05:40:44 PM PDT 24 |
Aug 12 05:46:37 PM PDT 24 |
33657090306 ps |
| T920 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.818365574 |
|
|
Aug 12 05:39:24 PM PDT 24 |
Aug 12 05:39:46 PM PDT 24 |
719635652 ps |
| T921 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2051889446 |
|
|
Aug 12 05:42:06 PM PDT 24 |
Aug 12 05:43:18 PM PDT 24 |
3865139800 ps |
| T922 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.508839393 |
|
|
Aug 12 05:41:24 PM PDT 24 |
Aug 12 05:58:01 PM PDT 24 |
21229331815 ps |
| T923 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.885204874 |
|
|
Aug 12 05:39:50 PM PDT 24 |
Aug 12 05:44:59 PM PDT 24 |
18774380483 ps |
| T924 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.987153496 |
|
|
Aug 12 05:40:01 PM PDT 24 |
Aug 12 05:46:35 PM PDT 24 |
7172607370 ps |
| T925 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1164911331 |
|
|
Aug 12 05:41:43 PM PDT 24 |
Aug 12 05:42:07 PM PDT 24 |
1503147762 ps |
| T926 |
/workspace/coverage/default/42.sram_ctrl_regwen.1496864563 |
|
|
Aug 12 05:41:15 PM PDT 24 |
Aug 12 05:49:51 PM PDT 24 |
21583209551 ps |
| T927 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1067916545 |
|
|
Aug 12 05:39:28 PM PDT 24 |
Aug 12 05:42:47 PM PDT 24 |
64437763842 ps |
| T928 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1001538983 |
|
|
Aug 12 05:39:46 PM PDT 24 |
Aug 12 05:46:32 PM PDT 24 |
32997039518 ps |
| T929 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2151265556 |
|
|
Aug 12 05:40:05 PM PDT 24 |
Aug 12 05:40:06 PM PDT 24 |
12848262 ps |
| T930 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1194821911 |
|
|
Aug 12 05:42:00 PM PDT 24 |
Aug 12 05:44:40 PM PDT 24 |
1674184295 ps |
| T931 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3291476267 |
|
|
Aug 12 05:40:13 PM PDT 24 |
Aug 12 05:47:56 PM PDT 24 |
10236995615 ps |
| T932 |
/workspace/coverage/default/5.sram_ctrl_regwen.24051346 |
|
|
Aug 12 05:39:01 PM PDT 24 |
Aug 12 05:48:19 PM PDT 24 |
1556931738 ps |
| T933 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1599812897 |
|
|
Aug 12 05:39:18 PM PDT 24 |
Aug 12 05:39:54 PM PDT 24 |
6475205927 ps |
| T934 |
/workspace/coverage/default/47.sram_ctrl_executable.1488550874 |
|
|
Aug 12 05:41:49 PM PDT 24 |
Aug 12 05:56:02 PM PDT 24 |
7191876618 ps |
| T935 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2488638073 |
|
|
Aug 12 05:40:33 PM PDT 24 |
Aug 12 05:54:32 PM PDT 24 |
34667680262 ps |
| T936 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3647143045 |
|
|
Aug 12 05:40:21 PM PDT 24 |
Aug 12 06:41:46 PM PDT 24 |
555331706495 ps |
| T937 |
/workspace/coverage/default/28.sram_ctrl_bijection.3567876925 |
|
|
Aug 12 05:40:05 PM PDT 24 |
Aug 12 06:01:51 PM PDT 24 |
303935702989 ps |
| T938 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3313936634 |
|
|
Aug 12 05:39:43 PM PDT 24 |
Aug 12 05:39:44 PM PDT 24 |
39893165 ps |
| T939 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1969320691 |
|
|
Aug 12 05:40:09 PM PDT 24 |
Aug 12 05:48:44 PM PDT 24 |
8998992306 ps |
| T940 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2489207672 |
|
|
Aug 12 05:41:31 PM PDT 24 |
Aug 12 05:44:10 PM PDT 24 |
3243359215 ps |
| T941 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.906644649 |
|
|
Aug 12 05:39:55 PM PDT 24 |
Aug 12 06:00:27 PM PDT 24 |
42312960324 ps |
| T942 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2114860548 |
|
|
Aug 12 05:40:18 PM PDT 24 |
Aug 12 05:42:56 PM PDT 24 |
4383222099 ps |
| T943 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1621429735 |
|
|
Aug 12 05:39:16 PM PDT 24 |
Aug 12 05:40:38 PM PDT 24 |
51943643201 ps |
| T944 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.454040532 |
|
|
Aug 12 05:40:30 PM PDT 24 |
Aug 12 05:47:16 PM PDT 24 |
23067484761 ps |
| T945 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2822906400 |
|
|
Aug 12 05:41:25 PM PDT 24 |
Aug 12 05:42:34 PM PDT 24 |
46219073447 ps |
| T946 |
/workspace/coverage/default/4.sram_ctrl_smoke.3443180676 |
|
|
Aug 12 05:39:01 PM PDT 24 |
Aug 12 05:39:40 PM PDT 24 |
4027985748 ps |
| T947 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.3139637890 |
|
|
Aug 12 05:39:17 PM PDT 24 |
Aug 12 05:41:29 PM PDT 24 |
8970175488 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2983695210 |
|
|
Aug 12 05:38:16 PM PDT 24 |
Aug 12 05:38:19 PM PDT 24 |
369828428 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.142871086 |
|
|
Aug 12 05:38:24 PM PDT 24 |
Aug 12 05:38:27 PM PDT 24 |
141918585 ps |
| T72 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2178413760 |
|
|
Aug 12 05:38:06 PM PDT 24 |
Aug 12 05:38:09 PM PDT 24 |
225148662 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4232999282 |
|
|
Aug 12 05:38:42 PM PDT 24 |
Aug 12 05:38:45 PM PDT 24 |
774869236 ps |
| T73 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1990933527 |
|
|
Aug 12 05:38:20 PM PDT 24 |
Aug 12 05:38:22 PM PDT 24 |
357780093 ps |
| T75 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3673188149 |
|
|
Aug 12 05:38:25 PM PDT 24 |
Aug 12 05:38:25 PM PDT 24 |
34548782 ps |
| T88 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2820493259 |
|
|
Aug 12 05:38:22 PM PDT 24 |
Aug 12 05:39:19 PM PDT 24 |
15698761248 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3310606155 |
|
|
Aug 12 05:38:24 PM PDT 24 |
Aug 12 05:38:29 PM PDT 24 |
371771916 ps |
| T120 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3119075177 |
|
|
Aug 12 05:38:21 PM PDT 24 |
Aug 12 05:38:21 PM PDT 24 |
48180897 ps |
| T952 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.513737055 |
|
|
Aug 12 05:38:09 PM PDT 24 |
Aug 12 05:38:13 PM PDT 24 |
364013972 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4143684878 |
|
|
Aug 12 05:38:06 PM PDT 24 |
Aug 12 05:38:15 PM PDT 24 |
131756301 ps |
| T89 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1018089825 |
|
|
Aug 12 05:38:17 PM PDT 24 |
Aug 12 05:38:18 PM PDT 24 |
36683648 ps |
| T127 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2803071148 |
|
|
Aug 12 05:38:09 PM PDT 24 |
Aug 12 05:38:10 PM PDT 24 |
62125616 ps |
| T90 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1114083391 |
|
|
Aug 12 05:38:23 PM PDT 24 |
Aug 12 05:39:14 PM PDT 24 |
54272535270 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3933479041 |
|
|
Aug 12 05:38:24 PM PDT 24 |
Aug 12 05:38:28 PM PDT 24 |
34260033 ps |
| T955 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.343756681 |
|
|
Aug 12 05:38:32 PM PDT 24 |
Aug 12 05:38:36 PM PDT 24 |
29749059 ps |
| T74 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2562520191 |
|
|
Aug 12 05:38:18 PM PDT 24 |
Aug 12 05:38:21 PM PDT 24 |
145566936 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3264140323 |
|
|
Aug 12 05:38:13 PM PDT 24 |
Aug 12 05:38:16 PM PDT 24 |
175656242 ps |
| T133 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.6485624 |
|
|
Aug 12 05:38:10 PM PDT 24 |
Aug 12 05:38:12 PM PDT 24 |
823758616 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2437751771 |
|
|
Aug 12 05:38:44 PM PDT 24 |
Aug 12 05:38:47 PM PDT 24 |
1248941482 ps |
| T91 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1627206637 |
|
|
Aug 12 05:38:15 PM PDT 24 |
Aug 12 05:38:16 PM PDT 24 |
30824290 ps |
| T958 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.765579661 |
|
|
Aug 12 05:38:27 PM PDT 24 |
Aug 12 05:38:30 PM PDT 24 |
146026912 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1443568576 |
|
|
Aug 12 05:38:30 PM PDT 24 |
Aug 12 05:38:33 PM PDT 24 |
343319310 ps |
| T92 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3767053042 |
|
|
Aug 12 05:38:29 PM PDT 24 |
Aug 12 05:38:30 PM PDT 24 |
52418068 ps |
| T134 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3632402764 |
|
|
Aug 12 05:38:43 PM PDT 24 |
Aug 12 05:38:45 PM PDT 24 |
180293646 ps |
| T960 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2907601104 |
|
|
Aug 12 05:38:24 PM PDT 24 |
Aug 12 05:38:28 PM PDT 24 |
1179835411 ps |
| T128 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3145508397 |
|
|
Aug 12 05:38:18 PM PDT 24 |
Aug 12 05:38:19 PM PDT 24 |
14202437 ps |
| T93 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.270648354 |
|
|
Aug 12 05:38:24 PM PDT 24 |
Aug 12 05:39:15 PM PDT 24 |
7258624261 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4282827246 |
|
|
Aug 12 05:38:09 PM PDT 24 |
Aug 12 05:38:09 PM PDT 24 |
30764696 ps |
| T962 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.247029406 |
|
|
Aug 12 05:38:35 PM PDT 24 |
Aug 12 05:38:43 PM PDT 24 |
37180901 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.196358669 |
|
|
Aug 12 05:38:09 PM PDT 24 |
Aug 12 05:38:10 PM PDT 24 |
27254226 ps |
| T135 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3885159642 |
|
|
Aug 12 05:38:19 PM PDT 24 |
Aug 12 05:38:21 PM PDT 24 |
123524754 ps |
| T963 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2772235056 |
|
|
Aug 12 05:38:33 PM PDT 24 |
Aug 12 05:38:38 PM PDT 24 |
1057161916 ps |
| T964 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4108372678 |
|
|
Aug 12 05:38:11 PM PDT 24 |
Aug 12 05:38:15 PM PDT 24 |
359810079 ps |
| T965 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1079222444 |
|
|
Aug 12 05:38:35 PM PDT 24 |
Aug 12 05:38:37 PM PDT 24 |
188740376 ps |
| T121 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3666686080 |
|
|
Aug 12 05:38:08 PM PDT 24 |
Aug 12 05:38:08 PM PDT 24 |
16959243 ps |
| T966 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1661793871 |
|
|
Aug 12 05:38:47 PM PDT 24 |
Aug 12 05:38:51 PM PDT 24 |
701982088 ps |
| T95 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1887570968 |
|
|
Aug 12 05:38:22 PM PDT 24 |
Aug 12 05:38:53 PM PDT 24 |
10270463338 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3711417295 |
|
|
Aug 12 05:38:24 PM PDT 24 |
Aug 12 05:38:29 PM PDT 24 |
1477643851 ps |
| T96 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1715605820 |
|
|
Aug 12 05:38:24 PM PDT 24 |
Aug 12 05:38:25 PM PDT 24 |
12691965 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3202620188 |
|
|
Aug 12 05:38:21 PM PDT 24 |
Aug 12 05:38:23 PM PDT 24 |
257687182 ps |
| T97 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4119403337 |
|
|
Aug 12 05:38:07 PM PDT 24 |
Aug 12 05:38:39 PM PDT 24 |
7556035236 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.983448444 |
|
|
Aug 12 05:38:06 PM PDT 24 |
Aug 12 05:38:36 PM PDT 24 |
3834595068 ps |
| T111 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3215339579 |
|
|
Aug 12 05:38:20 PM PDT 24 |
Aug 12 05:38:22 PM PDT 24 |
43244457 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3012811830 |
|
|
Aug 12 05:38:22 PM PDT 24 |
Aug 12 05:38:52 PM PDT 24 |
3850491305 ps |
| T970 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4031001853 |
|
|
Aug 12 05:38:08 PM PDT 24 |
Aug 12 05:38:11 PM PDT 24 |
378182946 ps |
| T136 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.270795961 |
|
|
Aug 12 05:38:02 PM PDT 24 |
Aug 12 05:38:05 PM PDT 24 |
407002047 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1965590480 |
|
|
Aug 12 05:38:20 PM PDT 24 |
Aug 12 05:38:24 PM PDT 24 |
587058739 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2402375494 |
|
|
Aug 12 05:38:10 PM PDT 24 |
Aug 12 05:38:13 PM PDT 24 |
1212565989 ps |
| T99 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4252933793 |
|
|
Aug 12 05:38:34 PM PDT 24 |
Aug 12 05:39:03 PM PDT 24 |
3842697769 ps |
| T137 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.828170732 |
|
|
Aug 12 05:38:05 PM PDT 24 |
Aug 12 05:38:07 PM PDT 24 |
92557973 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1422364763 |
|
|
Aug 12 05:38:20 PM PDT 24 |
Aug 12 05:38:21 PM PDT 24 |
15984101 ps |
| T974 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.623603073 |
|
|
Aug 12 05:38:27 PM PDT 24 |
Aug 12 05:38:31 PM PDT 24 |
744911449 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3343101852 |
|
|
Aug 12 05:38:13 PM PDT 24 |
Aug 12 05:38:17 PM PDT 24 |
158936383 ps |
| T976 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.372526700 |
|
|
Aug 12 05:38:36 PM PDT 24 |
Aug 12 05:38:37 PM PDT 24 |
20184921 ps |
| T977 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2089447803 |
|
|
Aug 12 05:38:19 PM PDT 24 |
Aug 12 05:38:22 PM PDT 24 |
351316127 ps |
| T138 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3149595994 |
|
|
Aug 12 05:38:20 PM PDT 24 |
Aug 12 05:38:22 PM PDT 24 |
358495775 ps |
| T978 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2131215345 |
|
|
Aug 12 05:38:36 PM PDT 24 |
Aug 12 05:38:37 PM PDT 24 |
47171293 ps |
| T979 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1529648402 |
|
|
Aug 12 05:38:34 PM PDT 24 |
Aug 12 05:38:38 PM PDT 24 |
1439564794 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3001744507 |
|
|
Aug 12 05:38:06 PM PDT 24 |
Aug 12 05:38:06 PM PDT 24 |
53138296 ps |
| T100 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3684799504 |
|
|
Aug 12 05:38:32 PM PDT 24 |
Aug 12 05:38:32 PM PDT 24 |
30977280 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1897465744 |
|
|
Aug 12 05:38:08 PM PDT 24 |
Aug 12 05:38:09 PM PDT 24 |
16670434 ps |
| T982 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3259006810 |
|
|
Aug 12 05:38:26 PM PDT 24 |
Aug 12 05:38:31 PM PDT 24 |
1390242402 ps |
| T101 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3622653838 |
|
|
Aug 12 05:38:33 PM PDT 24 |
Aug 12 05:38:34 PM PDT 24 |
67712294 ps |
| T983 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.725270275 |
|
|
Aug 12 05:38:21 PM PDT 24 |
Aug 12 05:38:24 PM PDT 24 |
27033264 ps |
| T984 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1040921180 |
|
|
Aug 12 05:38:27 PM PDT 24 |
Aug 12 05:38:33 PM PDT 24 |
75284985 ps |
| T985 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2475467349 |
|
|
Aug 12 05:38:18 PM PDT 24 |
Aug 12 05:38:22 PM PDT 24 |
366175559 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.887346286 |
|
|
Aug 12 05:38:18 PM PDT 24 |
Aug 12 05:38:20 PM PDT 24 |
2141346229 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3230844564 |
|
|
Aug 12 05:38:08 PM PDT 24 |
Aug 12 05:38:08 PM PDT 24 |
25104672 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2266009433 |
|
|
Aug 12 05:38:26 PM PDT 24 |
Aug 12 05:38:28 PM PDT 24 |
248155072 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1681115926 |
|
|
Aug 12 05:38:07 PM PDT 24 |
Aug 12 05:38:09 PM PDT 24 |
145921767 ps |
| T103 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1682178324 |
|
|
Aug 12 05:38:18 PM PDT 24 |
Aug 12 05:38:19 PM PDT 24 |
13974652 ps |
| T989 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.657254089 |
|
|
Aug 12 05:38:22 PM PDT 24 |
Aug 12 05:38:23 PM PDT 24 |
97837404 ps |
| T990 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2227878281 |
|
|
Aug 12 05:38:19 PM PDT 24 |
Aug 12 05:38:20 PM PDT 24 |
20824161 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1110072624 |
|
|
Aug 12 05:38:26 PM PDT 24 |
Aug 12 05:38:29 PM PDT 24 |
255562421 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2875692737 |
|
|
Aug 12 05:38:35 PM PDT 24 |
Aug 12 05:39:33 PM PDT 24 |
29371420454 ps |
| T993 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2139276075 |
|
|
Aug 12 05:38:15 PM PDT 24 |
Aug 12 05:38:15 PM PDT 24 |
103511966 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4095471087 |
|
|
Aug 12 05:38:26 PM PDT 24 |
Aug 12 05:38:29 PM PDT 24 |
1272715857 ps |
| T104 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.773144936 |
|
|
Aug 12 05:38:18 PM PDT 24 |
Aug 12 05:38:19 PM PDT 24 |
34686931 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2412322401 |
|
|
Aug 12 05:38:10 PM PDT 24 |
Aug 12 05:38:16 PM PDT 24 |
25327769 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2779243390 |
|
|
Aug 12 05:38:21 PM PDT 24 |
Aug 12 05:38:22 PM PDT 24 |
15984161 ps |
| T997 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.657907312 |
|
|
Aug 12 05:38:08 PM PDT 24 |
Aug 12 05:38:11 PM PDT 24 |
716630677 ps |
| T998 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1937997952 |
|
|
Aug 12 05:38:08 PM PDT 24 |
Aug 12 05:38:09 PM PDT 24 |
65098197 ps |
| T999 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2081053905 |
|
|
Aug 12 05:38:06 PM PDT 24 |
Aug 12 05:38:07 PM PDT 24 |
53587788 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.216323821 |
|
|
Aug 12 05:38:10 PM PDT 24 |
Aug 12 05:38:11 PM PDT 24 |
17384038 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2602550185 |
|
|
Aug 12 05:38:06 PM PDT 24 |
Aug 12 05:38:08 PM PDT 24 |
141251777 ps |
| T1002 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2639697484 |
|
|
Aug 12 05:38:15 PM PDT 24 |
Aug 12 05:38:17 PM PDT 24 |
77707770 ps |
| T1003 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1059321594 |
|
|
Aug 12 05:38:36 PM PDT 24 |
Aug 12 05:38:37 PM PDT 24 |
23211072 ps |
| T112 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3458690757 |
|
|
Aug 12 05:38:27 PM PDT 24 |
Aug 12 05:38:27 PM PDT 24 |
19207511 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.369640749 |
|
|
Aug 12 05:38:07 PM PDT 24 |
Aug 12 05:38:08 PM PDT 24 |
22022619 ps |
| T1005 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4001958384 |
|
|
Aug 12 05:38:29 PM PDT 24 |
Aug 12 05:38:30 PM PDT 24 |
22460047 ps |
| T1006 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1204966150 |
|
|
Aug 12 05:38:22 PM PDT 24 |
Aug 12 05:38:28 PM PDT 24 |
173373444 ps |
| T1007 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3646208834 |
|
|
Aug 12 05:37:59 PM PDT 24 |
Aug 12 05:38:01 PM PDT 24 |
268936065 ps |
| T1008 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.8374784 |
|
|
Aug 12 05:38:07 PM PDT 24 |
Aug 12 05:38:08 PM PDT 24 |
20757163 ps |
| T1009 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4124546748 |
|
|
Aug 12 05:38:13 PM PDT 24 |
Aug 12 05:38:18 PM PDT 24 |
573044728 ps |
| T143 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3055063222 |
|
|
Aug 12 05:38:33 PM PDT 24 |
Aug 12 05:38:36 PM PDT 24 |
652194410 ps |
| T1010 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2350435646 |
|
|
Aug 12 05:38:25 PM PDT 24 |
Aug 12 05:38:26 PM PDT 24 |
40125581 ps |