Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16537833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

145390493

1

T1

160218

T2

98303

T3

458752

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	79597756	1			T1	87955		T2	32768		T3	229376
values[0x0]	39512717	1			T1	42440		T2	32910		T3	114680
values[0x1]	42817853	1			T1	45748		T2	32625		T3	114696

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8404735	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

153523591

1

T1

168338

T2

98303

T3

458752

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	520965	1			T1	680		T2	427		T4	734
valid_sources[0x01]	524254	1			T1	671		T2	402		T4	714
valid_sources[0x02]	617130	1			T1	671		T2	604		T4	721
valid_sources[0x03]	568063	1			T1	676		T2	378		T4	743
valid_sources[0x04]	526765	1			T1	718		T2	263		T4	737
valid_sources[0x05]	529756	1			T1	679		T2	579		T4	682
valid_sources[0x06]	543369	1			T1	705		T2	364		T4	713
valid_sources[0x07]	1437758	1			T1	676		T2	420		T4	776
valid_sources[0x08]	521509	1			T1	711		T2	332		T4	699
valid_sources[0x09]	523939	1			T1	685		T2	450		T4	747
valid_sources[0x0a]	508023	1			T1	648		T2	267		T4	701
valid_sources[0x0b]	516315	1			T1	703		T2	300		T4	721
valid_sources[0x0c]	557795	1			T1	636		T2	439		T4	684
valid_sources[0x0d]	613207	1			T1	682		T2	291		T4	724
valid_sources[0x0e]	1486432	1			T1	690		T2	322		T4	690
valid_sources[0x0f]	496878	1			T1	666		T2	417		T4	737
valid_sources[0x10]	536332	1			T1	724		T2	411		T4	699
valid_sources[0x11]	593771	1			T1	687		T2	253		T4	736
valid_sources[0x12]	524244	1			T1	647		T2	328		T4	741
valid_sources[0x13]	501741	1			T1	724		T2	397		T4	735
valid_sources[0x14]	526837	1			T1	705		T2	393		T4	672
valid_sources[0x15]	516758	1			T1	643		T2	300		T4	706
valid_sources[0x16]	536299	1			T1	641		T2	432		T4	684
valid_sources[0x17]	569881	1			T1	668		T2	181		T4	735
valid_sources[0x18]	505438	1			T1	681		T2	271		T4	773
valid_sources[0x19]	571915	1			T1	664		T2	458		T4	712
valid_sources[0x1a]	576219	1			T1	644		T2	414		T4	695
valid_sources[0x1b]	531011	1			T1	702		T2	527		T4	718
valid_sources[0x1c]	549999	1			T1	684		T2	441		T4	707
valid_sources[0x1d]	516457	1			T1	682		T2	278		T4	751
valid_sources[0x1e]	521411	1			T1	714		T2	406		T4	724
valid_sources[0x1f]	520721	1			T1	716		T2	348		T4	763
valid_sources[0x20]	1502496	1			T1	680		T2	409		T4	679
valid_sources[0x21]	513538	1			T1	644		T2	434		T4	704
valid_sources[0x22]	532754	1			T1	738		T2	398		T4	736
valid_sources[0x23]	522684	1			T1	658		T2	327		T4	744
valid_sources[0x24]	499455	1			T1	679		T2	549		T4	664
valid_sources[0x25]	567031	1			T1	650		T2	370		T4	669
valid_sources[0x26]	1176665	1			T1	668		T2	482		T4	756
valid_sources[0x27]	551417	1			T1	649		T2	506		T4	678
valid_sources[0x28]	567973	1			T1	670		T2	389		T4	708
valid_sources[0x29]	502063	1			T1	683		T2	365		T4	743
valid_sources[0x2a]	549812	1			T1	715		T2	485		T4	748
valid_sources[0x2b]	596145	1			T1	736		T2	270		T4	707
valid_sources[0x2c]	537659	1			T1	665		T2	413		T4	742
valid_sources[0x2d]	567377	1			T1	652		T2	554		T4	740
valid_sources[0x2e]	1370602	1			T1	673		T2	259		T4	771
valid_sources[0x2f]	552421	1			T1	669		T2	569		T4	719
valid_sources[0x30]	507699	1			T1	728		T2	376		T4	703
valid_sources[0x31]	2574040	1			T1	696		T2	476		T4	710
valid_sources[0x32]	509312	1			T1	686		T2	474		T4	714
valid_sources[0x33]	537659	1			T1	715		T2	443		T4	709
valid_sources[0x34]	544298	1			T1	709		T2	257		T4	742
valid_sources[0x35]	508066	1			T1	716		T2	352		T4	687
valid_sources[0x36]	501662	1			T1	705		T2	286		T4	695
valid_sources[0x37]	518313	1			T1	714		T2	414		T4	668
valid_sources[0x38]	496953	1			T1	655		T2	318		T4	734
valid_sources[0x39]	606431	1			T1	682		T2	406		T4	699
valid_sources[0x3a]	515973	1			T1	753		T2	239		T4	733
valid_sources[0x3b]	530519	1			T1	688		T2	455		T4	763
valid_sources[0x3c]	508722	1			T1	737		T2	336		T4	722
valid_sources[0x3d]	512190	1			T1	688		T2	388		T4	730
valid_sources[0x3e]	499169	1			T1	730		T2	426		T4	801
valid_sources[0x3f]	563234	1			T1	659		T2	457		T4	750
valid_sources[0x40]	516777	1			T1	694		T2	373		T4	733
valid_sources[0x41]	501972	1			T1	641		T2	319		T4	716
valid_sources[0x42]	520840	1			T1	736		T2	201		T4	752
valid_sources[0x43]	508273	1			T1	693		T2	239		T4	684
valid_sources[0x44]	537753	1			T1	711		T2	315		T4	775
valid_sources[0x45]	2956834	1			T1	664		T2	281		T4	647
valid_sources[0x46]	526142	1			T1	684		T2	334		T4	725
valid_sources[0x47]	532849	1			T1	707		T2	366		T4	725
valid_sources[0x48]	515807	1			T1	709		T2	447		T4	682
valid_sources[0x49]	525355	1			T1	672		T2	485		T4	766
valid_sources[0x4a]	521341	1			T1	686		T2	414		T4	689
valid_sources[0x4b]	565198	1			T1	662		T2	529		T4	735
valid_sources[0x4c]	567123	1			T1	661		T2	339		T4	721
valid_sources[0x4d]	546445	1			T1	743		T2	434		T4	775
valid_sources[0x4e]	548985	1			T1	623		T2	505		T4	706
valid_sources[0x4f]	2070941	1			T1	688		T2	526		T4	715
valid_sources[0x50]	497162	1			T1	722		T2	459		T4	732
valid_sources[0x51]	511278	1			T1	698		T2	235		T4	735
valid_sources[0x52]	527897	1			T1	682		T2	436		T4	752
valid_sources[0x53]	521057	1			T1	711		T2	281		T4	737
valid_sources[0x54]	528898	1			T1	675		T2	324		T4	759
valid_sources[0x55]	518634	1			T1	651		T2	411		T4	679
valid_sources[0x56]	516557	1			T1	692		T2	364		T4	682
valid_sources[0x57]	535436	1			T1	702		T2	333		T4	737
valid_sources[0x58]	507554	1			T1	699		T2	486		T4	717
valid_sources[0x59]	497203	1			T1	699		T2	453		T4	733
valid_sources[0x5a]	539348	1			T1	702		T2	614		T4	664
valid_sources[0x5b]	556116	1			T1	673		T2	435		T4	740
valid_sources[0x5c]	536481	1			T1	699		T2	429		T4	658
valid_sources[0x5d]	548063	1			T1	691		T2	613		T4	707
valid_sources[0x5e]	529947	1			T1	692		T2	498		T4	717
valid_sources[0x5f]	553055	1			T1	689		T2	374		T4	733
valid_sources[0x60]	529535	1			T1	667		T2	396		T4	732
valid_sources[0x61]	597985	1			T1	670		T2	384		T4	712
valid_sources[0x62]	508054	1			T1	709		T2	254		T4	720
valid_sources[0x63]	508764	1			T1	658		T2	431		T4	698
valid_sources[0x64]	549929	1			T1	663		T2	306		T4	755
valid_sources[0x65]	503735	1			T1	714		T2	403		T4	683
valid_sources[0x66]	540175	1			T1	730		T2	409		T4	719
valid_sources[0x67]	504426	1			T1	737		T2	718		T4	744
valid_sources[0x68]	547057	1			T1	695		T2	472		T4	724
valid_sources[0x69]	1366233	1			T1	735		T2	498		T3	458752
valid_sources[0x6a]	515881	1			T1	696		T2	506		T4	681
valid_sources[0x6b]	520326	1			T1	637		T2	333		T4	831
valid_sources[0x6c]	522740	1			T1	706		T2	397		T4	770
valid_sources[0x6d]	2007063	1			T1	756		T2	423		T4	682
valid_sources[0x6e]	531419	1			T1	692		T2	268		T4	693
valid_sources[0x6f]	3595348	1			T1	679		T2	466		T4	767
valid_sources[0x70]	512946	1			T1	730		T2	318		T4	753
valid_sources[0x71]	518151	1			T1	715		T2	414		T4	708
valid_sources[0x72]	514132	1			T1	690		T2	408		T4	747
valid_sources[0x73]	538159	1			T1	690		T2	357		T4	725
valid_sources[0x74]	546261	1			T1	687		T2	471		T4	710
valid_sources[0x75]	556579	1			T1	723		T2	382		T4	761
valid_sources[0x76]	494873	1			T1	662		T2	226		T4	714
valid_sources[0x77]	1476719	1			T1	706		T2	293		T4	685
valid_sources[0x78]	597953	1			T1	677		T2	360		T4	685
valid_sources[0x79]	513478	1			T1	673		T2	273		T4	741
valid_sources[0x7a]	522321	1			T1	684		T2	447		T4	636
valid_sources[0x7b]	542025	1			T1	697		T2	520		T4	705
valid_sources[0x7c]	538824	1			T1	675		T2	313		T4	696
valid_sources[0x7d]	751998	1			T1	681		T2	495		T4	700
valid_sources[0x7e]	513123	1			T1	670		T2	280		T4	779
valid_sources[0x7f]	554220	1			T1	701		T2	382		T4	720
valid_sources[0x80]	523179	1			T1	666		T2	297		T4	669

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71281236

1

T1

80051

T2

32768

T3

229376

values[0x0]

all_enables

biggest_size

37048125

1

T1

40087

T2

32910

T3

114680

values[0x1]

all_enables

biggest_size

37061132

1

T1

40080

T2

32625

T3

114696

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

166554

1

T1

26

T2

11

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57364	1			T1	18		T7	61		T25	662
values[0x0]	74585	1			T1	38		T2	19		T3	2
values[0x1]	79433	1			T1	36		T2	19		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34516	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

176866

1

T1

33

T2

15

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	856	1			T7	1		T45	1		T58	4
valid_sources[0x01]	858	1			T5	2		T7	2		T25	19
valid_sources[0x02]	554	1			T28	2		T155	1		T26	3
valid_sources[0x03]	628	1			T7	10		T45	1		T46	1
valid_sources[0x04]	622	1			T26	9		T53	2		T147	3
valid_sources[0x05]	681	1			T5	1		T7	5		T45	3
valid_sources[0x06]	704	1			T7	2		T79	2		T26	13
valid_sources[0x07]	727	1			T7	2		T25	1		T58	2
valid_sources[0x08]	940	1			T10	1		T25	14		T28	1
valid_sources[0x09]	625	1			T7	1		T45	3		T82	1
valid_sources[0x0a]	765	1			T2	2		T28	1		T26	2
valid_sources[0x0b]	775	1			T155	1		T26	12		T27	46
valid_sources[0x0c]	733	1			T7	8		T49	3		T26	13
valid_sources[0x0d]	569	1			T58	1		T49	3		T26	4
valid_sources[0x0e]	796	1			T14	1		T7	4		T25	71
valid_sources[0x0f]	850	1			T2	1		T5	1		T25	11
valid_sources[0x10]	754	1			T155	1		T15	2		T26	11
valid_sources[0x11]	950	1			T45	1		T61	69		T26	13
valid_sources[0x12]	639	1			T26	9		T53	2		T154	1
valid_sources[0x13]	816	1			T7	2		T82	1		T28	4
valid_sources[0x14]	716	1			T7	2		T25	2		T29	1
valid_sources[0x15]	813	1			T25	3		T45	2		T26	14
valid_sources[0x16]	685	1			T25	4		T155	2		T58	2
valid_sources[0x17]	834	1			T25	1		T26	11		T16	1
valid_sources[0x18]	609	1			T58	1		T49	7		T26	11
valid_sources[0x19]	787	1			T2	2		T7	2		T49	1
valid_sources[0x1a]	643	1			T26	15		T23	1		T147	3
valid_sources[0x1b]	677	1			T28	3		T145	1		T49	1
valid_sources[0x1c]	1089	1			T7	2		T25	7		T26	13
valid_sources[0x1d]	940	1			T7	3		T25	300		T58	1
valid_sources[0x1e]	1673	1			T7	5		T25	1		T49	3
valid_sources[0x1f]	892	1			T7	1		T28	1		T145	1
valid_sources[0x20]	996	1			T25	210		T26	11		T53	1
valid_sources[0x21]	956	1			T145	2		T49	1		T26	15
valid_sources[0x22]	730	1			T26	9		T84	1		T147	1
valid_sources[0x23]	559	1			T25	16		T45	2		T46	1
valid_sources[0x24]	904	1			T46	1		T26	13		T53	1
valid_sources[0x25]	560	1			T26	6		T84	1		T85	1
valid_sources[0x26]	627	1			T26	8		T53	2		T147	3
valid_sources[0x27]	654	1			T25	2		T46	1		T156	2
valid_sources[0x28]	762	1			T7	2		T28	1		T155	1
valid_sources[0x29]	759	1			T5	1		T45	1		T46	1
valid_sources[0x2a]	914	1			T14	1		T25	2		T45	1
valid_sources[0x2b]	860	1			T26	6		T154	1		T74	1
valid_sources[0x2c]	743	1			T83	1		T28	1		T49	4
valid_sources[0x2d]	713	1			T7	6		T25	48		T26	10
valid_sources[0x2e]	761	1			T2	1		T25	1		T49	1
valid_sources[0x2f]	820	1			T25	178		T26	12		T23	1
valid_sources[0x30]	576	1			T7	5		T145	1		T49	4
valid_sources[0x31]	901	1			T2	2		T7	1		T25	1
valid_sources[0x32]	795	1			T83	1		T117	1		T49	11
valid_sources[0x33]	1650	1			T28	2		T26	7		T23	1
valid_sources[0x34]	745	1			T7	2		T145	1		T26	8
valid_sources[0x35]	931	1			T1	92		T10	1		T7	1
valid_sources[0x36]	667	1			T5	2		T14	3		T7	7
valid_sources[0x37]	701	1			T28	2		T26	9		T53	2
valid_sources[0x38]	544	1			T7	1		T26	11		T16	1
valid_sources[0x39]	538	1			T7	3		T46	1		T28	1
valid_sources[0x3a]	952	1			T5	1		T25	13		T45	1
valid_sources[0x3b]	730	1			T13	1		T145	1		T49	4
valid_sources[0x3c]	1018	1			T5	1		T7	1		T26	16
valid_sources[0x3d]	1022	1			T46	1		T58	1		T49	4
valid_sources[0x3e]	767	1			T58	1		T26	4		T84	1
valid_sources[0x3f]	1089	1			T7	1		T58	1		T49	2
valid_sources[0x40]	972	1			T7	3		T25	3		T26	5
valid_sources[0x41]	892	1			T5	1		T25	61		T28	1
valid_sources[0x42]	918	1			T5	1		T7	1		T25	57
valid_sources[0x43]	938	1			T49	6		T26	13		T84	1
valid_sources[0x44]	675	1			T5	1		T82	1		T145	1
valid_sources[0x45]	655	1			T28	3		T49	9		T26	12
valid_sources[0x46]	639	1			T7	1		T58	1		T49	2
valid_sources[0x47]	1011	1			T5	1		T25	26		T28	3
valid_sources[0x48]	551	1			T58	2		T26	14		T27	3
valid_sources[0x49]	967	1			T25	21		T58	1		T49	1
valid_sources[0x4a]	761	1			T7	1		T25	1		T26	7
valid_sources[0x4b]	747	1			T12	1		T25	9		T28	3
valid_sources[0x4c]	1286	1			T7	1		T25	55		T145	1
valid_sources[0x4d]	1363	1			T5	1		T81	1		T26	12
valid_sources[0x4e]	641	1			T7	1		T28	1		T49	1
valid_sources[0x4f]	964	1			T5	1		T7	1		T58	1
valid_sources[0x50]	916	1			T2	2		T7	1		T25	1
valid_sources[0x51]	943	1			T7	1		T26	8		T84	1
valid_sources[0x52]	980	1			T26	9		T85	2		T53	2
valid_sources[0x53]	506	1			T2	2		T14	1		T28	3
valid_sources[0x54]	878	1			T5	1		T7	1		T58	3
valid_sources[0x55]	708	1			T5	1		T7	2		T145	1
valid_sources[0x56]	1014	1			T28	1		T26	9		T53	1
valid_sources[0x57]	886	1			T26	6		T23	1		T27	74
valid_sources[0x58]	981	1			T49	1		T26	7		T84	1
valid_sources[0x59]	1144	1			T25	16		T45	1		T46	1
valid_sources[0x5a]	1026	1			T7	1		T45	1		T156	1
valid_sources[0x5b]	815	1			T45	1		T26	9		T53	1
valid_sources[0x5c]	567	1			T5	1		T20	8		T7	7
valid_sources[0x5d]	619	1			T7	2		T25	1		T28	1
valid_sources[0x5e]	1043	1			T14	1		T45	1		T26	13
valid_sources[0x5f]	769	1			T58	2		T49	2		T26	4
valid_sources[0x60]	870	1			T2	1		T7	2		T45	2
valid_sources[0x61]	803	1			T25	3		T28	1		T49	2
valid_sources[0x62]	569	1			T3	7		T7	1		T45	1
valid_sources[0x63]	808	1			T10	1		T25	1		T45	1
valid_sources[0x64]	775	1			T26	11		T23	4		T74	4
valid_sources[0x65]	1000	1			T25	49		T156	1		T26	7
valid_sources[0x66]	1162	1			T25	4		T155	1		T59	1
valid_sources[0x67]	757	1			T13	1		T25	1		T145	1
valid_sources[0x68]	585	1			T5	1		T26	9		T53	1
valid_sources[0x69]	1058	1			T25	23		T58	3		T49	2
valid_sources[0x6a]	968	1			T49	8		T26	7		T84	1
valid_sources[0x6b]	823	1			T26	6		T37	1		T157	2
valid_sources[0x6c]	889	1			T83	1		T58	1		T26	13
valid_sources[0x6d]	826	1			T25	55		T145	1		T49	4
valid_sources[0x6e]	744	1			T7	1		T8	52		T49	11
valid_sources[0x6f]	837	1			T5	1		T20	2		T7	1
valid_sources[0x70]	732	1			T7	11		T25	49		T49	1
valid_sources[0x71]	768	1			T7	4		T155	1		T58	1
valid_sources[0x72]	809	1			T7	2		T25	1		T58	1
valid_sources[0x73]	694	1			T7	2		T25	37		T28	2
valid_sources[0x74]	985	1			T7	4		T155	1		T49	8
valid_sources[0x75]	945	1			T26	8		T158	1		T159	2
valid_sources[0x76]	904	1			T7	2		T155	1		T26	14
valid_sources[0x77]	586	1			T13	1		T7	2		T49	4
valid_sources[0x78]	1229	1			T25	3		T82	1		T26	7
valid_sources[0x79]	674	1			T11	1		T7	1		T25	1
valid_sources[0x7a]	965	1			T7	2		T25	22		T28	3
valid_sources[0x7b]	779	1			T46	1		T28	1		T155	1
valid_sources[0x7c]	636	1			T20	3		T25	3		T28	1
valid_sources[0x7d]	713	1			T5	2		T25	46		T160	1
valid_sources[0x7e]	647	1			T26	13		T53	2		T147	6
valid_sources[0x7f]	779	1			T7	1		T25	3		T28	1
valid_sources[0x80]	1445	1			T28	2		T26	8		T74	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44375

1

T1

6

T7

28

T25

587

values[0x0]

all_enables

biggest_size

62683

1

T1

16

T2

6

T3

1

values[0x1]

all_enables

biggest_size

59496

1

T1

4

T2

5

T6

1