Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16437071

1

T1

13521

T4

16772

T5

18610

full_word

142023978

1

T1

135883

T2

98303

T3

458752

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	158460739	1			T1	149404		T2	98303		T3	458752
auto[TlIntgErrCmd]	87	1			T68	2		T69	2		T70	7
auto[TlIntgErrData]	117	1			T68	6		T69	7		T70	7
auto[TlIntgErrBoth]	106	1			T68	2		T69	11		T70	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76029628

1

T1

61216

T2

32768

T3

229376

auto[1]

82431421

1

T1

88188

T2

65535

T3

229376

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8034592	1			T1	5500		T4	8432		T5	9169
auto[TlIntgErrNone]	partial	auto[1]	8402189	1			T1	8021		T4	8340		T5	9441
auto[TlIntgErrNone]	full_word	auto[0]	67994888	1			T1	55716		T2	32768		T3	229376
auto[TlIntgErrNone]	full_word	auto[1]	74029070	1			T1	80167		T2	65535		T3	229376
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T68	1		T70	2		T136	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T68	1		T69	2		T70	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T70	1		T138	1		T137	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T140	1		T141	1		-	-
auto[TlIntgErrData]	partial	auto[0]	50	1			T68	3		T69	4		T136	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T68	2		T69	3		T70	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T70	1		T136	1		T139	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T68	1		T70	1		T142	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T68	1		T69	3		T70	4
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T68	1		T69	8		T70	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T143	1		T144	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T70	1		-	-		-	-