Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	815153	1			T1	42		T42	17239		T7	430
auto[1]	10527584	1			T1	586		T4	76270		T6	915
auto[2]	617333	1			T1	38		T42	15010		T7	256
auto[3]	10272501	1			T1	438		T4	76740		T6	923

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14355622	1			T1	792		T4	127499		T6	1838
auto[1]	2029089	1			T1	114		T4	12123		T5	9780
auto[2]	2086363	1			T1	166		T4	12205		T5	9545
auto[3]	3761497	1			T1	32		T4	1183		T5	954

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9468844

1

T1

1104

T6

1838

T5

121062

auto[1]

12763727

1

T4

153010

T5

2

T11

224281

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	294428	1			T1	28		T7	356		T82	210
auto[0]	auto[0]	auto[1]	31108	1			T1	7		T7	37		T43	25
auto[0]	auto[0]	auto[2]	31287	1			T1	5		T7	36		T43	22
auto[0]	auto[0]	auto[3]	41275	1			T1	2		T7	1		T43	4267
auto[0]	auto[1]	auto[0]	3395697	1			T1	452		T6	915		T5	50588
auto[0]	auto[1]	auto[1]	349237	1			T1	73		T5	4630		T13	3
auto[0]	auto[1]	auto[2]	370858	1			T1	50		T5	4912		T11	1
auto[0]	auto[1]	auto[3]	366982	1			T1	11		T5	493		T44	28
auto[0]	auto[2]	auto[0]	201736	1			T43	3		T21	8092		T150	12044
auto[0]	auto[2]	auto[1]	22972	1			T43	373		T21	792		T150	1231
auto[0]	auto[2]	auto[2]	26220	1			T1	33		T7	232		T43	24
auto[0]	auto[2]	auto[3]	29825	1			T1	5		T7	24		T43	2684
auto[0]	auto[3]	auto[0]	3257091	1			T1	312		T6	923		T5	50195
auto[0]	auto[3]	auto[1]	352750	1			T1	34		T5	5150		T13	1
auto[0]	auto[3]	auto[2]	362083	1			T1	78		T5	4633		T44	124
auto[0]	auto[3]	auto[3]	335295	1			T1	14		T5	461		T44	27
auto[1]	auto[0]	auto[0]	13788	1			T42	602		T148	428		T151	1
auto[1]	auto[0]	auto[1]	61596	1			T42	2552		T148	1912		T149	566
auto[1]	auto[0]	auto[2]	62497	1			T42	2585		T148	1889		T149	564
auto[1]	auto[0]	auto[3]	279174	1			T42	11500		T43	3		T148	8897
auto[1]	auto[1]	auto[0]	3593030	1			T4	63499		T11	92536		T13	59852
auto[1]	auto[1]	auto[1]	608311	1			T4	5735		T11	9263		T13	5934
auto[1]	auto[1]	auto[2]	582851	1			T4	6465		T11	9193		T13	6028
auto[1]	auto[1]	auto[3]	1260618	1			T4	571		T11	914		T13	624
auto[1]	auto[2]	auto[0]	9494	1			T42	371		T150	1		T148	272
auto[1]	auto[2]	auto[1]	41256	1			T42	1527		T148	1203		T151	1
auto[1]	auto[2]	auto[2]	51934	1			T42	2310		T148	2066		T149	534
auto[1]	auto[2]	auto[3]	233896	1			T42	10802		T148	9543		T149	2351
auto[1]	auto[3]	auto[0]	3590358	1			T4	64000		T5	2		T11	92791
auto[1]	auto[3]	auto[1]	561859	1			T4	6388		T11	9316		T13	6044
auto[1]	auto[3]	auto[2]	598633	1			T4	5740		T11	9313		T13	6118
auto[1]	auto[3]	auto[3]	1214432	1			T4	612		T11	955		T13	641