Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1081044402	253519	0	0
ctrl_regwen_rd_A	1081044402	4903	0	0
exec_rd_A	1081044402	4395	0	0
exec_regwen_rd_A	1081044402	5012	0	0
readback_rd_A	1081044402	3193	0	0
readback_regwen_rd_A	1081044402	2982	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081044402	253519	0	0
T8	874583	0	0	0
T25	51507	4060	0	0
T26	0	3456	0	0
T27	0	5994	0	0
T45	163644	0	0	0
T46	783940	0	0	0
T51	0	4359	0	0
T55	0	2506	0	0
T64	0	4229	0	0
T74	0	1716	0	0
T75	0	3913	0	0
T76	0	5294	0	0
T77	0	2369	0	0
T78	78039	0	0	0
T79	170942	0	0	0
T80	33892	0	0	0
T81	432006	0	0	0
T82	102576	0	0	0
T83	770529	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081044402	4903	0	0
T31	33757	0	0	0
T51	0	302	0	0
T52	0	521	0	0
T55	58811	121	0	0
T77	0	284	0	0
T119	0	212	0	0
T120	0	236	0	0
T121	0	204	0	0
T122	0	82	0	0
T123	0	85	0	0
T124	0	200	0	0
T125	439373	0	0	0
T126	506889	0	0	0
T127	422054	0	0	0
T128	594280	0	0	0
T129	262901	0	0	0
T130	138306	0	0	0
T131	544813	0	0	0
T132	161574	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081044402	4395	0	0
T31	33757	0	0	0
T51	0	334	0	0
T52	0	429	0	0
T55	58811	224	0	0
T77	0	253	0	0
T119	0	241	0	0
T120	0	186	0	0
T121	0	137	0	0
T122	0	63	0	0
T123	0	115	0	0
T124	0	206	0	0
T125	439373	0	0	0
T126	506889	0	0	0
T127	422054	0	0	0
T128	594280	0	0	0
T129	262901	0	0	0
T130	138306	0	0	0
T131	544813	0	0	0
T132	161574	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081044402	5012	0	0
T31	33757	0	0	0
T51	0	354	0	0
T52	0	612	0	0
T55	58811	201	0	0
T77	0	204	0	0
T119	0	289	0	0
T120	0	250	0	0
T121	0	225	0	0
T122	0	72	0	0
T123	0	110	0	0
T124	0	269	0	0
T125	439373	0	0	0
T126	506889	0	0	0
T127	422054	0	0	0
T128	594280	0	0	0
T129	262901	0	0	0
T130	138306	0	0	0
T131	544813	0	0	0
T132	161574	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081044402	3193	0	0
T31	33757	0	0	0
T51	0	305	0	0
T52	0	541	0	0
T55	58811	187	0	0
T77	0	206	0	0
T119	0	198	0	0
T120	0	139	0	0
T121	0	205	0	0
T122	0	48	0	0
T123	0	134	0	0
T124	0	157	0	0
T125	439373	0	0	0
T126	506889	0	0	0
T127	422054	0	0	0
T128	594280	0	0	0
T129	262901	0	0	0
T130	138306	0	0	0
T131	544813	0	0	0
T132	161574	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081044402	2982	0	0
T31	33757	0	0	0
T51	0	199	0	0
T52	0	523	0	0
T55	58811	226	0	0
T77	0	182	0	0
T119	0	253	0	0
T120	0	178	0	0
T121	0	211	0	0
T122	0	39	0	0
T123	0	106	0	0
T124	0	169	0	0
T125	439373	0	0	0
T126	506889	0	0	0
T127	422054	0	0	0
T128	594280	0	0	0
T129	262901	0	0	0
T130	138306	0	0	0
T131	544813	0	0	0
T132	161574	0	0	0