Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
40.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	3	6	66.67
Crosses	16	12	4	25.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	2	1	33.33	100	1	1	0
lc_hw_debug_en_cp	3	1	2	66.67	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	12	4	25.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	70572	1			T1	2652		T3	40		T6	1252
instr_valid_dis	65456	1			T1	2652		T3	31		T6	1252
instr_en	643	1			T3	4		T9	1		T13	10

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	2	1	33.33

User Defined Bins for en_sram_ifetch_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sram_ifetch_invalid_disable	0	1	1
sram_ifetch_enable	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

sram_ifetch_valid_disable

70572

1

T1

2652

T3

40

T6

1252

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for lc_hw_debug_en_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
hw_debug_en_on	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

hw_debug_en_invalid_off

70572

1

T1

2652

T3

40

T6

1252

hw_debug_en_valid_off

70572

1

T1

2652

T3

40

T6

1252

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	12	4	25.00	9
Automatically Generated Cross Bins	12	9	3	25.00	9
User Defined Cross Bins	4	3	1	25.00

Automatically Generated Cross Bins for executable_cross

Element holes

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	NUMBER	STATUS
[hw_debug_en_valid_off]	[sram_ifetch_invalid_disable]	*	--	--	3
[hw_debug_en_on]	[sram_ifetch_invalid_disable , sram_ifetch_valid_disable]	*	--	--	6

Covered bins

lc_hw_debug_en_cp

en_sram_ifetch_cp

csr_exec_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

hw_debug_en_invalid_off

sram_ifetch_valid_disable

instr_invalid_dis

70572

1

T1

2652

T3

40

T6

1252

hw_debug_en_invalid_off

sram_ifetch_valid_disable

instr_valid_dis

65456

1

T1

2652

T3

31

T6

1252

hw_debug_en_invalid_off

sram_ifetch_valid_disable

instr_en

643

1

T3

4

T9

1

T13

10

User Defined Cross Bins for executable_cross

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
csr_exec_en	0	1	1
lc_exec_en	0	1	1
invalid_exec_dis	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid_exec_dis

70572

1

T1

2652

T3

40

T6

1252