| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 46.89 | 25.31 | 31.86 | 68.11 | 0.00 | 27.34 | 98.47 | 77.15 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 41.47 | 41.47 | 24.61 | 24.61 | 27.73 | 27.73 | 79.30 | 79.30 | 0.00 | 0.00 | 25.36 | 25.36 | 95.42 | 95.42 | 37.84 | 37.84 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3758691869 |
| 47.06 | 5.60 | 25.27 | 0.65 | 30.33 | 2.61 | 93.31 | 14.01 | 0.00 | 0.00 | 27.01 | 1.66 | 98.14 | 2.71 | 55.39 | 17.55 | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3253409874 |
| 49.97 | 2.91 | 25.43 | 0.16 | 31.16 | 0.83 | 95.33 | 2.02 | 0.00 | 0.00 | 27.73 | 0.71 | 98.31 | 0.17 | 71.85 | 16.45 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2917671866 |
| 50.81 | 0.84 | 25.43 | 0.00 | 31.28 | 0.12 | 97.25 | 1.92 | 0.00 | 0.00 | 27.73 | 0.00 | 98.47 | 0.17 | 75.50 | 3.66 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1309939197 |
| 50.91 | 0.10 | 25.43 | 0.00 | 31.28 | 0.00 | 97.25 | 0.00 | 0.00 | 0.00 | 27.73 | 0.00 | 98.47 | 0.00 | 76.23 | 0.73 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3968560375 |
| 51.01 | 0.10 | 25.43 | 0.00 | 31.40 | 0.12 | 97.25 | 0.00 | 0.00 | 0.00 | 27.73 | 0.00 | 98.47 | 0.00 | 76.78 | 0.55 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3207291894 |
| 51.05 | 0.04 | 25.43 | 0.00 | 31.52 | 0.12 | 97.25 | 0.00 | 0.00 | 0.00 | 27.73 | 0.00 | 98.47 | 0.00 | 76.97 | 0.18 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3563456684 |
| 51.08 | 0.03 | 25.43 | 0.00 | 31.52 | 0.00 | 97.25 | 0.00 | 0.00 | 0.00 | 27.73 | 0.00 | 98.47 | 0.00 | 77.15 | 0.18 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2473938133 |
| 51.09 | 0.02 | 25.43 | 0.00 | 31.64 | 0.12 | 97.25 | 0.00 | 0.00 | 0.00 | 27.73 | 0.00 | 98.47 | 0.00 | 77.15 | 0.00 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2790913853 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4115902326 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1065968568 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3533084836 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3797353807 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3348994109 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.490016663 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2779905574 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2020458347 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.881601450 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.102522426 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2781590421 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3030503996 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1494741152 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.310651822 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2193820960 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3918731343 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.567785373 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1650124396 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2784132323 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3111526418 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.812835215 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3498231672 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.505447268 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1850952148 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1599606257 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1920358957 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3514215196 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1141725328 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.125270078 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.287221022 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4248742486 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3091433846 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2109233609 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2161952648 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2705209244 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.485278456 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.998765780 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2505604007 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3288318315 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2453204032 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4233950115 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1454869260 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1323180701 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.357688410 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.182017819 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1956062942 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3285239831 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1747099071 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1285880048 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1894872294 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.307335971 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4084067863 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4024639185 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3702212724 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2133414591 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.909560830 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.108976716 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3303787037 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3792765563 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4184601870 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1496385439 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2611820597 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3154554769 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2139543058 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3492753963 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.364548627 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2869559633 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3685460478 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.270559863 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.238951965 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.654945784 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1581787519 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.390741253 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.366098039 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2386453333 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2262521476 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1549008335 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1251456156 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2239103305 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3278025147 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3321192993 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.449914305 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.625795982 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.685477494 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1358244769 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1643687704 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1203295712 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.206589917 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1979443137 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3121884465 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2930940900 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.831422017 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4290316602 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1221534790 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2373282745 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3500015929 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2741659246 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2794339442 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1811818630 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.328125305 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2392768414 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1119815002 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2359177586 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3528763687 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3944499702 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.311092805 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.307211248 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.344998529 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3409664381 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3543312059 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1047437464 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.182792202 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3636406035 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2192127848 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2683516772 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2340744070 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3875067528 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1496969902 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2370454730 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3576313661 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3957133249 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1058928546 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2430921136 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3315763271 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1019549770 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2208780937 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4024639185 | Aug 14 04:27:23 PM PDT 24 | Aug 14 04:27:26 PM PDT 24 | 150691667 ps | ||
| T2 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1221534790 | Aug 14 04:27:08 PM PDT 24 | Aug 14 04:27:09 PM PDT 24 | 40625628 ps | ||
| T3 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3348994109 | Aug 14 04:27:09 PM PDT 24 | Aug 14 04:27:38 PM PDT 24 | 3738731533 ps | ||
| T6 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3207291894 | Aug 14 04:28:14 PM PDT 24 | Aug 14 04:28:17 PM PDT 24 | 30541930 ps | ||
| T4 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.311092805 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:28:08 PM PDT 24 | 29299475753 ps | ||
| T5 | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.108976716 | Aug 14 04:27:27 PM PDT 24 | Aug 14 04:27:57 PM PDT 24 | 17651427052 ps | ||
| T9 | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3253409874 | Aug 14 04:27:20 PM PDT 24 | Aug 14 04:28:12 PM PDT 24 | 14429776497 ps | ||
| T10 | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.307211248 | Aug 14 04:27:20 PM PDT 24 | Aug 14 04:27:21 PM PDT 24 | 50308896 ps | ||
| T7 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3758691869 | Aug 14 04:27:24 PM PDT 24 | Aug 14 04:27:28 PM PDT 24 | 1435717011 ps | ||
| T11 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2192127848 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:21 PM PDT 24 | 139061561 ps | ||
| T18 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1141725328 | Aug 14 04:27:45 PM PDT 24 | Aug 14 04:27:46 PM PDT 24 | 11762099 ps | ||
| T12 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1599606257 | Aug 14 04:27:34 PM PDT 24 | Aug 14 04:27:37 PM PDT 24 | 85564084 ps | ||
| T8 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2340744070 | Aug 14 04:27:12 PM PDT 24 | Aug 14 04:27:15 PM PDT 24 | 360434580 ps | ||
| T13 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2741659246 | Aug 14 04:27:17 PM PDT 24 | Aug 14 04:27:20 PM PDT 24 | 679480987 ps | ||
| T25 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.881601450 | Aug 14 04:27:23 PM PDT 24 | Aug 14 04:27:26 PM PDT 24 | 180187721 ps | ||
| T14 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1309939197 | Aug 14 04:27:11 PM PDT 24 | Aug 14 04:27:14 PM PDT 24 | 152177646 ps | ||
| T26 | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4233950115 | Aug 14 04:27:24 PM PDT 24 | Aug 14 04:27:26 PM PDT 24 | 111402549 ps | ||
| T15 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3918731343 | Aug 14 04:27:28 PM PDT 24 | Aug 14 04:27:32 PM PDT 24 | 1447318640 ps | ||
| T27 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1549008335 | Aug 14 04:27:21 PM PDT 24 | Aug 14 04:27:22 PM PDT 24 | 12196152 ps | ||
| T37 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.831422017 | Aug 14 04:27:14 PM PDT 24 | Aug 14 04:27:15 PM PDT 24 | 41438060 ps | ||
| T30 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.366098039 | Aug 14 04:27:23 PM PDT 24 | Aug 14 04:27:25 PM PDT 24 | 177283588 ps | ||
| T36 | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3315763271 | Aug 14 04:27:17 PM PDT 24 | Aug 14 04:27:17 PM PDT 24 | 18902625 ps | ||
| T19 | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.505447268 | Aug 14 04:27:32 PM PDT 24 | Aug 14 04:28:03 PM PDT 24 | 24655747044 ps | ||
| T16 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2109233609 | Aug 14 04:27:24 PM PDT 24 | Aug 14 04:27:27 PM PDT 24 | 355545983 ps | ||
| T17 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2208780937 | Aug 14 04:27:25 PM PDT 24 | Aug 14 04:27:27 PM PDT 24 | 328282413 ps | ||
| T28 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4248742486 | Aug 14 04:27:19 PM PDT 24 | Aug 14 04:27:24 PM PDT 24 | 291728120 ps | ||
| T31 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.102522426 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:19 PM PDT 24 | 12572226 ps | ||
| T40 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2193820960 | Aug 14 04:27:16 PM PDT 24 | Aug 14 04:27:17 PM PDT 24 | 333857368 ps | ||
| T32 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3685460478 | Aug 14 04:27:19 PM PDT 24 | Aug 14 04:27:19 PM PDT 24 | 13833637 ps | ||
| T20 | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.328125305 | Aug 14 04:27:22 PM PDT 24 | Aug 14 04:28:17 PM PDT 24 | 14721861520 ps | ||
| T41 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2790913853 | Aug 14 04:27:08 PM PDT 24 | Aug 14 04:27:09 PM PDT 24 | 23949738 ps | ||
| T29 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2917671866 | Aug 14 04:27:14 PM PDT 24 | Aug 14 04:27:16 PM PDT 24 | 309737288 ps | ||
| T61 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2930940900 | Aug 14 04:27:12 PM PDT 24 | Aug 14 04:27:15 PM PDT 24 | 301375878 ps | ||
| T62 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.182017819 | Aug 14 04:27:30 PM PDT 24 | Aug 14 04:27:31 PM PDT 24 | 20310415 ps | ||
| T63 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.310651822 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:16 PM PDT 24 | 25245517 ps | ||
| T42 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3543312059 | Aug 14 04:27:41 PM PDT 24 | Aug 14 04:27:45 PM PDT 24 | 2689711907 ps | ||
| T64 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3563456684 | Aug 14 04:27:13 PM PDT 24 | Aug 14 04:27:18 PM PDT 24 | 1415190654 ps | ||
| T65 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1065968568 | Aug 14 04:27:20 PM PDT 24 | Aug 14 04:27:21 PM PDT 24 | 47340240 ps | ||
| T21 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1643687704 | Aug 14 04:27:13 PM PDT 24 | Aug 14 04:27:46 PM PDT 24 | 26432954808 ps | ||
| T66 | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1850952148 | Aug 14 04:27:23 PM PDT 24 | Aug 14 04:27:24 PM PDT 24 | 97187579 ps | ||
| T43 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1019549770 | Aug 14 04:27:34 PM PDT 24 | Aug 14 04:27:36 PM PDT 24 | 197927022 ps | ||
| T22 | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1251456156 | Aug 14 04:27:21 PM PDT 24 | Aug 14 04:27:51 PM PDT 24 | 4401946376 ps | ||
| T67 | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4084067863 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:18 PM PDT 24 | 16089994 ps | ||
| T68 | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2239103305 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:16 PM PDT 24 | 26483071 ps | ||
| T69 | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2784132323 | Aug 14 04:27:23 PM PDT 24 | Aug 14 04:27:23 PM PDT 24 | 58698631 ps | ||
| T70 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3797353807 | Aug 14 04:27:31 PM PDT 24 | Aug 14 04:27:32 PM PDT 24 | 13424210 ps | ||
| T33 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3875067528 | Aug 14 04:27:29 PM PDT 24 | Aug 14 04:27:29 PM PDT 24 | 12140785 ps | ||
| T71 | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3288318315 | Aug 14 04:27:20 PM PDT 24 | Aug 14 04:27:20 PM PDT 24 | 12402049 ps | ||
| T44 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1285880048 | Aug 14 04:27:33 PM PDT 24 | Aug 14 04:27:36 PM PDT 24 | 351458795 ps | ||
| T72 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2794339442 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:19 PM PDT 24 | 1361184540 ps | ||
| T73 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4290316602 | Aug 14 04:27:14 PM PDT 24 | Aug 14 04:27:18 PM PDT 24 | 717976886 ps | ||
| T34 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2611820597 | Aug 14 04:27:27 PM PDT 24 | Aug 14 04:27:28 PM PDT 24 | 13336950 ps | ||
| T45 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2779905574 | Aug 14 04:27:06 PM PDT 24 | Aug 14 04:27:10 PM PDT 24 | 465134934 ps | ||
| T54 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.364548627 | Aug 14 04:27:19 PM PDT 24 | Aug 14 04:27:22 PM PDT 24 | 176479143 ps | ||
| T74 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3321192993 | Aug 14 04:27:27 PM PDT 24 | Aug 14 04:27:29 PM PDT 24 | 105269805 ps | ||
| T58 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3091433846 | Aug 14 04:27:34 PM PDT 24 | Aug 14 04:27:36 PM PDT 24 | 382955381 ps | ||
| T75 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.287221022 | Aug 14 04:27:17 PM PDT 24 | Aug 14 04:27:18 PM PDT 24 | 20957167 ps | ||
| T23 | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1956062942 | Aug 14 04:27:30 PM PDT 24 | Aug 14 04:27:59 PM PDT 24 | 14206270771 ps | ||
| T76 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3514215196 | Aug 14 04:27:39 PM PDT 24 | Aug 14 04:27:44 PM PDT 24 | 4318469712 ps | ||
| T24 | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1494741152 | Aug 14 04:27:13 PM PDT 24 | Aug 14 04:28:08 PM PDT 24 | 7399778006 ps | ||
| T77 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1119815002 | Aug 14 04:27:24 PM PDT 24 | Aug 14 04:27:29 PM PDT 24 | 281731935 ps | ||
| T78 | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2392768414 | Aug 14 04:27:21 PM PDT 24 | Aug 14 04:27:22 PM PDT 24 | 17974177 ps | ||
| T79 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2020458347 | Aug 14 04:27:24 PM PDT 24 | Aug 14 04:27:26 PM PDT 24 | 13907706 ps | ||
| T53 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1979443137 | Aug 14 04:27:11 PM PDT 24 | Aug 14 04:27:13 PM PDT 24 | 163452626 ps | ||
| T80 | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3285239831 | Aug 14 04:27:20 PM PDT 24 | Aug 14 04:27:20 PM PDT 24 | 67176369 ps | ||
| T81 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3278025147 | Aug 14 04:27:08 PM PDT 24 | Aug 14 04:27:12 PM PDT 24 | 100770551 ps | ||
| T82 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2373282745 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:19 PM PDT 24 | 33101105 ps | ||
| T83 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1454869260 | Aug 14 04:27:21 PM PDT 24 | Aug 14 04:27:23 PM PDT 24 | 43369407 ps | ||
| T84 | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2370454730 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:16 PM PDT 24 | 39368377 ps | ||
| T49 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1581787519 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:17 PM PDT 24 | 131477756 ps | ||
| T85 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3957133249 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:22 PM PDT 24 | 704325038 ps | ||
| T86 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3111526418 | Aug 14 04:27:20 PM PDT 24 | Aug 14 04:27:23 PM PDT 24 | 431469083 ps | ||
| T38 | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1496969902 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:28:06 PM PDT 24 | 14681263980 ps | ||
| T87 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.206589917 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:18 PM PDT 24 | 92804950 ps | ||
| T88 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3533084836 | Aug 14 04:27:25 PM PDT 24 | Aug 14 04:27:29 PM PDT 24 | 363633957 ps | ||
| T89 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.449914305 | Aug 14 04:27:28 PM PDT 24 | Aug 14 04:27:29 PM PDT 24 | 16527928 ps | ||
| T56 | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2359177586 | Aug 14 04:27:16 PM PDT 24 | Aug 14 04:27:17 PM PDT 24 | 319463898 ps | ||
| T90 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1047437464 | Aug 14 04:27:19 PM PDT 24 | Aug 14 04:27:20 PM PDT 24 | 30688990 ps | ||
| T59 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1747099071 | Aug 14 04:27:16 PM PDT 24 | Aug 14 04:27:19 PM PDT 24 | 285889282 ps | ||
| T46 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3492753963 | Aug 14 04:27:29 PM PDT 24 | Aug 14 04:27:32 PM PDT 24 | 391286181 ps | ||
| T91 | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.490016663 | Aug 14 04:27:21 PM PDT 24 | Aug 14 04:27:22 PM PDT 24 | 84594114 ps | ||
| T92 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.685477494 | Aug 14 04:27:30 PM PDT 24 | Aug 14 04:27:31 PM PDT 24 | 23172423 ps | ||
| T93 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4115902326 | Aug 14 04:27:20 PM PDT 24 | Aug 14 04:27:21 PM PDT 24 | 55673459 ps | ||
| T94 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.357688410 | Aug 14 04:27:35 PM PDT 24 | Aug 14 04:27:38 PM PDT 24 | 347659712 ps | ||
| T95 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.567785373 | Aug 14 04:27:19 PM PDT 24 | Aug 14 04:27:20 PM PDT 24 | 12444884 ps | ||
| T55 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3702212724 | Aug 14 04:27:22 PM PDT 24 | Aug 14 04:27:24 PM PDT 24 | 167425956 ps | ||
| T35 | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1650124396 | Aug 14 04:27:27 PM PDT 24 | Aug 14 04:28:15 PM PDT 24 | 7179870259 ps | ||
| T57 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2683516772 | Aug 14 04:27:17 PM PDT 24 | Aug 14 04:27:20 PM PDT 24 | 184028554 ps | ||
| T96 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1358244769 | Aug 14 04:27:01 PM PDT 24 | Aug 14 04:27:02 PM PDT 24 | 49524180 ps | ||
| T39 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.307335971 | Aug 14 04:27:23 PM PDT 24 | Aug 14 04:28:16 PM PDT 24 | 13805475127 ps | ||
| T97 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.998765780 | Aug 14 04:27:27 PM PDT 24 | Aug 14 04:27:31 PM PDT 24 | 186229066 ps | ||
| T98 | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2430921136 | Aug 14 04:27:17 PM PDT 24 | Aug 14 04:27:44 PM PDT 24 | 5280670586 ps | ||
| T99 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1811818630 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:15 PM PDT 24 | 17167813 ps | ||
| T100 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2781590421 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:19 PM PDT 24 | 2005545337 ps | ||
| T101 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3498231672 | Aug 14 04:27:35 PM PDT 24 | Aug 14 04:27:36 PM PDT 24 | 26259225 ps | ||
| T102 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2453204032 | Aug 14 04:27:13 PM PDT 24 | Aug 14 04:27:39 PM PDT 24 | 3739769341 ps | ||
| T103 | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1323180701 | Aug 14 04:27:29 PM PDT 24 | Aug 14 04:27:31 PM PDT 24 | 154201184 ps | ||
| T104 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2869559633 | Aug 14 04:27:20 PM PDT 24 | Aug 14 04:27:24 PM PDT 24 | 702330387 ps | ||
| T105 | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.238951965 | Aug 14 04:27:31 PM PDT 24 | Aug 14 04:27:32 PM PDT 24 | 18876912 ps | ||
| T106 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2386453333 | Aug 14 04:27:21 PM PDT 24 | Aug 14 04:27:22 PM PDT 24 | 49785323 ps | ||
| T47 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3528763687 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:22 PM PDT 24 | 727828980 ps | ||
| T48 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2262521476 | Aug 14 04:27:28 PM PDT 24 | Aug 14 04:27:32 PM PDT 24 | 1328454417 ps | ||
| T107 | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2705209244 | Aug 14 04:27:31 PM PDT 24 | Aug 14 04:28:28 PM PDT 24 | 7287479322 ps | ||
| T108 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3030503996 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:16 PM PDT 24 | 17703529 ps | ||
| T109 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2133414591 | Aug 14 04:28:35 PM PDT 24 | Aug 14 04:28:40 PM PDT 24 | 373057934 ps | ||
| T110 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.625795982 | Aug 14 04:27:19 PM PDT 24 | Aug 14 04:27:21 PM PDT 24 | 241106108 ps | ||
| T111 | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1894872294 | Aug 14 04:27:32 PM PDT 24 | Aug 14 04:27:33 PM PDT 24 | 19141907 ps | ||
| T112 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.654945784 | Aug 14 04:27:16 PM PDT 24 | Aug 14 04:27:18 PM PDT 24 | 42588503 ps | ||
| T113 | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.270559863 | Aug 14 04:27:33 PM PDT 24 | Aug 14 04:28:05 PM PDT 24 | 16735257609 ps | ||
| T114 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3121884465 | Aug 14 04:27:07 PM PDT 24 | Aug 14 04:27:08 PM PDT 24 | 19670251 ps | ||
| T115 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3792765563 | Aug 14 04:28:14 PM PDT 24 | Aug 14 04:28:17 PM PDT 24 | 87189177 ps | ||
| T116 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2161952648 | Aug 14 04:27:13 PM PDT 24 | Aug 14 04:27:14 PM PDT 24 | 24195610 ps | ||
| T60 | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2505604007 | Aug 14 04:27:41 PM PDT 24 | Aug 14 04:27:43 PM PDT 24 | 312674759 ps | ||
| T117 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3576313661 | Aug 14 04:27:27 PM PDT 24 | Aug 14 04:27:31 PM PDT 24 | 430742910 ps | ||
| T118 | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.125270078 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:56 PM PDT 24 | 30770327155 ps | ||
| T119 | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.182792202 | Aug 14 04:27:34 PM PDT 24 | Aug 14 04:28:03 PM PDT 24 | 4358014735 ps | ||
| T120 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.909560830 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:19 PM PDT 24 | 11321815 ps | ||
| T50 | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2473938133 | Aug 14 04:27:14 PM PDT 24 | Aug 14 04:27:16 PM PDT 24 | 110421303 ps | ||
| T121 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3154554769 | Aug 14 04:27:14 PM PDT 24 | Aug 14 04:27:41 PM PDT 24 | 3709046297 ps | ||
| T51 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3968560375 | Aug 14 04:27:23 PM PDT 24 | Aug 14 04:27:25 PM PDT 24 | 565097672 ps | ||
| T122 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1496385439 | Aug 14 04:27:27 PM PDT 24 | Aug 14 04:27:30 PM PDT 24 | 375782840 ps | ||
| T123 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3500015929 | Aug 14 04:27:24 PM PDT 24 | Aug 14 04:27:26 PM PDT 24 | 1355974802 ps | ||
| T124 | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1203295712 | Aug 14 04:27:14 PM PDT 24 | Aug 14 04:27:14 PM PDT 24 | 59145496 ps | ||
| T125 | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.812835215 | Aug 14 04:27:21 PM PDT 24 | Aug 14 04:27:25 PM PDT 24 | 371459098 ps | ||
| T52 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3409664381 | Aug 14 04:27:11 PM PDT 24 | Aug 14 04:27:14 PM PDT 24 | 1036211295 ps | ||
| T126 | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3636406035 | Aug 14 04:27:33 PM PDT 24 | Aug 14 04:27:34 PM PDT 24 | 208207158 ps | ||
| T127 | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2139543058 | Aug 14 04:27:36 PM PDT 24 | Aug 14 04:27:37 PM PDT 24 | 18163729 ps | ||
| T128 | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3303787037 | Aug 14 04:27:23 PM PDT 24 | Aug 14 04:27:24 PM PDT 24 | 85099417 ps | ||
| T129 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.390741253 | Aug 14 04:27:10 PM PDT 24 | Aug 14 04:27:11 PM PDT 24 | 35269331 ps | ||
| T130 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1058928546 | Aug 14 04:27:15 PM PDT 24 | Aug 14 04:27:16 PM PDT 24 | 46200555 ps | ||
| T131 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4184601870 | Aug 14 04:27:39 PM PDT 24 | Aug 14 04:27:41 PM PDT 24 | 217513169 ps | ||
| T132 | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.485278456 | Aug 14 04:27:17 PM PDT 24 | Aug 14 04:27:18 PM PDT 24 | 29923016 ps | ||
| T133 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1920358957 | Aug 14 04:27:18 PM PDT 24 | Aug 14 04:27:19 PM PDT 24 | 84126248 ps | ||
| T134 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.344998529 | Aug 14 04:27:27 PM PDT 24 | Aug 14 04:27:30 PM PDT 24 | 188993986 ps | ||
| T135 | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3944499702 | Aug 14 04:27:25 PM PDT 24 | Aug 14 04:27:26 PM PDT 24 | 36188853 ps |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3758691869 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1435717011 ps |
| CPU time | 3.85 seconds |
| Started | Aug 14 04:27:24 PM PDT 24 |
| Finished | Aug 14 04:27:28 PM PDT 24 |
| Peak memory | 213508 kb |
| Host | smart-0acacee8-4df4-4e86-bbb6-7bebdd96fb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758691869 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3758691869 |
| Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3253409874 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 14429776497 ps |
| CPU time | 51.87 seconds |
| Started | Aug 14 04:27:20 PM PDT 24 |
| Finished | Aug 14 04:28:12 PM PDT 24 |
| Peak memory | 202440 kb |
| Host | smart-33aaf3a0-77ed-4a68-b25d-827cd89e64d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253409874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3253409874 |
| Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2917671866 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 309737288 ps |
| CPU time | 2.53 seconds |
| Started | Aug 14 04:27:14 PM PDT 24 |
| Finished | Aug 14 04:27:16 PM PDT 24 |
| Peak memory | 202328 kb |
| Host | smart-329ff7b4-c404-468b-920a-1c35aa143ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917671866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.2917671866 |
| Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1309939197 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 152177646 ps |
| CPU time | 2.94 seconds |
| Started | Aug 14 04:27:11 PM PDT 24 |
| Finished | Aug 14 04:27:14 PM PDT 24 |
| Peak memory | 210756 kb |
| Host | smart-3487294a-185c-41b3-b22c-dd68e9b351f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309939197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.1309939197 |
| Directory | /workspace/1.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3968560375 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 565097672 ps |
| CPU time | 1.45 seconds |
| Started | Aug 14 04:27:23 PM PDT 24 |
| Finished | Aug 14 04:27:25 PM PDT 24 |
| Peak memory | 202308 kb |
| Host | smart-d11a619e-2e6e-4167-ae62-6f84434e4eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968560375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.3968560375 |
| Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3207291894 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 30541930 ps |
| CPU time | 2.01 seconds |
| Started | Aug 14 04:28:14 PM PDT 24 |
| Finished | Aug 14 04:28:17 PM PDT 24 |
| Peak memory | 201348 kb |
| Host | smart-414c1614-172c-4cfc-ae7a-96fad4448409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207291894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.3207291894 |
| Directory | /workspace/15.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3563456684 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1415190654 ps |
| CPU time | 4.84 seconds |
| Started | Aug 14 04:27:13 PM PDT 24 |
| Finished | Aug 14 04:27:18 PM PDT 24 |
| Peak memory | 210536 kb |
| Host | smart-c7e0d8a8-b204-4fe2-859f-deee41ef3b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563456684 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3563456684 |
| Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2473938133 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 110421303 ps |
| CPU time | 1.51 seconds |
| Started | Aug 14 04:27:14 PM PDT 24 |
| Finished | Aug 14 04:27:16 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-b8c3ecf4-bf83-44b8-a3dd-0a4bbd01d307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473938133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.2473938133 |
| Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2790913853 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 23949738 ps |
| CPU time | 0.68 seconds |
| Started | Aug 14 04:27:08 PM PDT 24 |
| Finished | Aug 14 04:27:09 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-2e8835f5-7beb-4429-a27d-0a4a5bc1bef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790913853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.2790913853 |
| Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4115902326 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 55673459 ps |
| CPU time | 0.67 seconds |
| Started | Aug 14 04:27:20 PM PDT 24 |
| Finished | Aug 14 04:27:21 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-fcd78616-90af-44da-b14d-57670be3deed |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115902326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.4115902326 |
| Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1065968568 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 47340240 ps |
| CPU time | 1.16 seconds |
| Started | Aug 14 04:27:20 PM PDT 24 |
| Finished | Aug 14 04:27:21 PM PDT 24 |
| Peak memory | 202316 kb |
| Host | smart-cf71a06c-d3db-4185-8d65-3b51e06f8eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065968568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.1065968568 |
| Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3533084836 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 363633957 ps |
| CPU time | 3.92 seconds |
| Started | Aug 14 04:27:25 PM PDT 24 |
| Finished | Aug 14 04:27:29 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-e47f11f8-f1fc-4ec7-b99d-94d78af3195f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533084836 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3533084836 |
| Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3797353807 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 13424210 ps |
| CPU time | 0.64 seconds |
| Started | Aug 14 04:27:31 PM PDT 24 |
| Finished | Aug 14 04:27:32 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-a8ee2cd1-cacf-4c45-9100-577b2d9470ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797353807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.3797353807 |
| Directory | /workspace/0.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3348994109 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3738731533 ps |
| CPU time | 28.5 seconds |
| Started | Aug 14 04:27:09 PM PDT 24 |
| Finished | Aug 14 04:27:38 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-fb687131-b5aa-4277-887a-dfd1730c71bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348994109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3348994109 |
| Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.490016663 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 84594114 ps |
| CPU time | 0.82 seconds |
| Started | Aug 14 04:27:21 PM PDT 24 |
| Finished | Aug 14 04:27:22 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-a5f4da5e-fd83-4387-b642-960f89d5dce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490016663 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.490016663 |
| Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2779905574 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 465134934 ps |
| CPU time | 4.1 seconds |
| Started | Aug 14 04:27:06 PM PDT 24 |
| Finished | Aug 14 04:27:10 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-d3ac36c8-cf2f-4157-a975-e56b196f3f90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779905574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.2779905574 |
| Directory | /workspace/0.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2020458347 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 13907706 ps |
| CPU time | 0.68 seconds |
| Started | Aug 14 04:27:24 PM PDT 24 |
| Finished | Aug 14 04:27:26 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-32b34015-92f9-44c6-9f3a-2c52cb8404a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020458347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.2020458347 |
| Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.881601450 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 180187721 ps |
| CPU time | 2.22 seconds |
| Started | Aug 14 04:27:23 PM PDT 24 |
| Finished | Aug 14 04:27:26 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-838f61cc-ea84-4106-9469-ebbf60bd3d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881601450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.881601450 |
| Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.102522426 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12572226 ps |
| CPU time | 0.65 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:19 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-e02f7ef1-444c-4d4c-8ca5-f994d76b03ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102522426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_reset.102522426 |
| Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2781590421 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2005545337 ps |
| CPU time | 3.38 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:19 PM PDT 24 |
| Peak memory | 210316 kb |
| Host | smart-e18bbbb0-bf15-4239-b64c-223a3299c4ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781590421 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2781590421 |
| Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3030503996 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 17703529 ps |
| CPU time | 0.61 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:16 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-e6342898-4913-454c-8fc3-bf539526cf84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030503996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3030503996 |
| Directory | /workspace/1.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1494741152 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7399778006 ps |
| CPU time | 54.82 seconds |
| Started | Aug 14 04:27:13 PM PDT 24 |
| Finished | Aug 14 04:28:08 PM PDT 24 |
| Peak memory | 202524 kb |
| Host | smart-87632c0f-498e-4e33-9aeb-fb00f5b89a59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494741152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1494741152 |
| Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.310651822 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 25245517 ps |
| CPU time | 0.7 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:16 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-c8f5210f-b7c6-4440-92a8-275e51121175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310651822 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.310651822 |
| Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2193820960 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 333857368 ps |
| CPU time | 1.5 seconds |
| Started | Aug 14 04:27:16 PM PDT 24 |
| Finished | Aug 14 04:27:17 PM PDT 24 |
| Peak memory | 210224 kb |
| Host | smart-29e5596e-6c65-4fd2-b071-0aec298d24e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193820960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.2193820960 |
| Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3918731343 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1447318640 ps |
| CPU time | 3.68 seconds |
| Started | Aug 14 04:27:28 PM PDT 24 |
| Finished | Aug 14 04:27:32 PM PDT 24 |
| Peak memory | 210560 kb |
| Host | smart-30b4f6c4-115d-4cb7-b4f6-54f9b2d321cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918731343 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3918731343 |
| Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.567785373 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 12444884 ps |
| CPU time | 0.67 seconds |
| Started | Aug 14 04:27:19 PM PDT 24 |
| Finished | Aug 14 04:27:20 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-cf3539b2-5580-49ca-9def-779b8a3d5555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567785373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_csr_rw.567785373 |
| Directory | /workspace/10.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1650124396 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7179870259 ps |
| CPU time | 48.55 seconds |
| Started | Aug 14 04:27:27 PM PDT 24 |
| Finished | Aug 14 04:28:15 PM PDT 24 |
| Peak memory | 202448 kb |
| Host | smart-9a6192f3-c68b-40a6-9428-5642a3c1396e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650124396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.1650124396 |
| Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2784132323 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 58698631 ps |
| CPU time | 0.7 seconds |
| Started | Aug 14 04:27:23 PM PDT 24 |
| Finished | Aug 14 04:27:23 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-cb2688a9-ba37-41a2-849f-bf1ec930ee32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784132323 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2784132323 |
| Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3111526418 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 431469083 ps |
| CPU time | 2.39 seconds |
| Started | Aug 14 04:27:20 PM PDT 24 |
| Finished | Aug 14 04:27:23 PM PDT 24 |
| Peak memory | 210532 kb |
| Host | smart-341b64e0-b375-424a-a80e-3c5c1193c29b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111526418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.3111526418 |
| Directory | /workspace/10.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.812835215 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 371459098 ps |
| CPU time | 3.57 seconds |
| Started | Aug 14 04:27:21 PM PDT 24 |
| Finished | Aug 14 04:27:25 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-4b1edd98-edb1-4bd1-b702-9ff34374e7f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812835215 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.812835215 |
| Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3498231672 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 26259225 ps |
| CPU time | 0.67 seconds |
| Started | Aug 14 04:27:35 PM PDT 24 |
| Finished | Aug 14 04:27:36 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-705f0df4-067c-49da-ad4e-3b586df263b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498231672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.3498231672 |
| Directory | /workspace/11.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.505447268 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 24655747044 ps |
| CPU time | 30.12 seconds |
| Started | Aug 14 04:27:32 PM PDT 24 |
| Finished | Aug 14 04:28:03 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-bbfa94cc-854a-46f6-a45a-3959116d21ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505447268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.505447268 |
| Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1850952148 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 97187579 ps |
| CPU time | 0.74 seconds |
| Started | Aug 14 04:27:23 PM PDT 24 |
| Finished | Aug 14 04:27:24 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-117baee7-a53b-47b3-b69e-a72f1cc5b552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850952148 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1850952148 |
| Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1599606257 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 85564084 ps |
| CPU time | 2.09 seconds |
| Started | Aug 14 04:27:34 PM PDT 24 |
| Finished | Aug 14 04:27:37 PM PDT 24 |
| Peak memory | 210584 kb |
| Host | smart-1fde448f-fe80-44c1-93c3-c8a705090cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599606257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1599606257 |
| Directory | /workspace/11.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1920358957 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 84126248 ps |
| CPU time | 1.45 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:19 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-0c5b022c-c5bc-4092-ab86-39bda83dbcd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920358957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.1920358957 |
| Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3514215196 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 4318469712 ps |
| CPU time | 4.27 seconds |
| Started | Aug 14 04:27:39 PM PDT 24 |
| Finished | Aug 14 04:27:44 PM PDT 24 |
| Peak memory | 210588 kb |
| Host | smart-16dcc688-20f6-46f3-9d9b-35df5339962a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514215196 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3514215196 |
| Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1141725328 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11762099 ps |
| CPU time | 0.63 seconds |
| Started | Aug 14 04:27:45 PM PDT 24 |
| Finished | Aug 14 04:27:46 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-f3bf9b4f-22c2-458b-b074-f0a5cfed7f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141725328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.1141725328 |
| Directory | /workspace/12.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.125270078 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 30770327155 ps |
| CPU time | 37.87 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:56 PM PDT 24 |
| Peak memory | 202428 kb |
| Host | smart-5bda86f7-5113-4994-a0c4-fdb2a8a9dd01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125270078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.125270078 |
| Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.287221022 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 20957167 ps |
| CPU time | 0.74 seconds |
| Started | Aug 14 04:27:17 PM PDT 24 |
| Finished | Aug 14 04:27:18 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-6597d067-539a-431f-b4cd-bbdd3d7209b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287221022 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.287221022 |
| Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4248742486 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 291728120 ps |
| CPU time | 4.28 seconds |
| Started | Aug 14 04:27:19 PM PDT 24 |
| Finished | Aug 14 04:27:24 PM PDT 24 |
| Peak memory | 210528 kb |
| Host | smart-5b1f93ef-ca98-4216-88b3-fb63ddc864bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248742486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.4248742486 |
| Directory | /workspace/12.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3091433846 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 382955381 ps |
| CPU time | 2.36 seconds |
| Started | Aug 14 04:27:34 PM PDT 24 |
| Finished | Aug 14 04:27:36 PM PDT 24 |
| Peak memory | 210440 kb |
| Host | smart-0348b67b-f879-420c-9f8e-14b3c9a1177c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091433846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.3091433846 |
| Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2109233609 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 355545983 ps |
| CPU time | 3.17 seconds |
| Started | Aug 14 04:27:24 PM PDT 24 |
| Finished | Aug 14 04:27:27 PM PDT 24 |
| Peak memory | 210332 kb |
| Host | smart-9ae999ad-edbe-4ac5-b367-384e56c19edf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109233609 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2109233609 |
| Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2161952648 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 24195610 ps |
| CPU time | 0.67 seconds |
| Started | Aug 14 04:27:13 PM PDT 24 |
| Finished | Aug 14 04:27:14 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-f5dd9c6a-d8bb-44f7-ba29-f0e2ad1e3849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161952648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.2161952648 |
| Directory | /workspace/13.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2705209244 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 7287479322 ps |
| CPU time | 56.76 seconds |
| Started | Aug 14 04:27:31 PM PDT 24 |
| Finished | Aug 14 04:28:28 PM PDT 24 |
| Peak memory | 202504 kb |
| Host | smart-8cce5d09-47a5-43f0-8a45-19a3550afe11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705209244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2705209244 |
| Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.485278456 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 29923016 ps |
| CPU time | 0.82 seconds |
| Started | Aug 14 04:27:17 PM PDT 24 |
| Finished | Aug 14 04:27:18 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-911d1cca-9ca3-4865-b3d1-c06bef609d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485278456 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.485278456 |
| Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.998765780 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 186229066 ps |
| CPU time | 3.64 seconds |
| Started | Aug 14 04:27:27 PM PDT 24 |
| Finished | Aug 14 04:27:31 PM PDT 24 |
| Peak memory | 210572 kb |
| Host | smart-6649b78b-a908-497b-b762-56e7ed4ae70f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998765780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.998765780 |
| Directory | /workspace/13.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2505604007 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 312674759 ps |
| CPU time | 2.2 seconds |
| Started | Aug 14 04:27:41 PM PDT 24 |
| Finished | Aug 14 04:27:43 PM PDT 24 |
| Peak memory | 210412 kb |
| Host | smart-d6509cae-5617-4f2e-b255-c0c88e959811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505604007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.2505604007 |
| Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3288318315 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 12402049 ps |
| CPU time | 0.64 seconds |
| Started | Aug 14 04:27:20 PM PDT 24 |
| Finished | Aug 14 04:27:20 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-2c2421ba-6013-4236-b262-46dd01cabf0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288318315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.3288318315 |
| Directory | /workspace/14.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2453204032 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3739769341 ps |
| CPU time | 25.75 seconds |
| Started | Aug 14 04:27:13 PM PDT 24 |
| Finished | Aug 14 04:27:39 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-a545b64e-424d-4e8f-bddf-040bc0470f2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453204032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2453204032 |
| Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4233950115 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 111402549 ps |
| CPU time | 0.73 seconds |
| Started | Aug 14 04:27:24 PM PDT 24 |
| Finished | Aug 14 04:27:26 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-74e896e1-452e-4a80-815e-94c568f954ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233950115 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.4233950115 |
| Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1454869260 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 43369407 ps |
| CPU time | 2.04 seconds |
| Started | Aug 14 04:27:21 PM PDT 24 |
| Finished | Aug 14 04:27:23 PM PDT 24 |
| Peak memory | 210516 kb |
| Host | smart-1471a27c-5f85-4679-b5f8-7145357a98d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454869260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.1454869260 |
| Directory | /workspace/14.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1323180701 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 154201184 ps |
| CPU time | 2.11 seconds |
| Started | Aug 14 04:27:29 PM PDT 24 |
| Finished | Aug 14 04:27:31 PM PDT 24 |
| Peak memory | 210496 kb |
| Host | smart-04143612-d5bd-48ca-9b3c-66d0fc908e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323180701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.1323180701 |
| Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.357688410 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 347659712 ps |
| CPU time | 3.11 seconds |
| Started | Aug 14 04:27:35 PM PDT 24 |
| Finished | Aug 14 04:27:38 PM PDT 24 |
| Peak memory | 210324 kb |
| Host | smart-94b82805-0030-4380-9254-2e14160872ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357688410 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.357688410 |
| Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.182017819 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 20310415 ps |
| CPU time | 0.66 seconds |
| Started | Aug 14 04:27:30 PM PDT 24 |
| Finished | Aug 14 04:27:31 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-be8a7809-7b2d-44cd-aec5-bbd0b673753b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182017819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_csr_rw.182017819 |
| Directory | /workspace/15.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1956062942 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14206270771 ps |
| CPU time | 28.96 seconds |
| Started | Aug 14 04:27:30 PM PDT 24 |
| Finished | Aug 14 04:27:59 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-9dd9607a-7196-4282-95e0-320aa4363124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956062942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1956062942 |
| Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3285239831 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 67176369 ps |
| CPU time | 0.72 seconds |
| Started | Aug 14 04:27:20 PM PDT 24 |
| Finished | Aug 14 04:27:20 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-7650e575-bc40-4b70-a566-366eafe71b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285239831 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3285239831 |
| Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1747099071 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 285889282 ps |
| CPU time | 2.03 seconds |
| Started | Aug 14 04:27:16 PM PDT 24 |
| Finished | Aug 14 04:27:19 PM PDT 24 |
| Peak memory | 210468 kb |
| Host | smart-f0efaa94-2d68-4c22-8692-b6ca2aa4851e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747099071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.1747099071 |
| Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1285880048 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 351458795 ps |
| CPU time | 3.66 seconds |
| Started | Aug 14 04:27:33 PM PDT 24 |
| Finished | Aug 14 04:27:36 PM PDT 24 |
| Peak memory | 210404 kb |
| Host | smart-fcbbf82a-1265-4137-8fd9-2620256ec3d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285880048 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1285880048 |
| Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1894872294 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 19141907 ps |
| CPU time | 0.66 seconds |
| Started | Aug 14 04:27:32 PM PDT 24 |
| Finished | Aug 14 04:27:33 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-d0206f78-711c-4159-b1ab-843577b84b37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894872294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1894872294 |
| Directory | /workspace/16.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.307335971 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13805475127 ps |
| CPU time | 52.36 seconds |
| Started | Aug 14 04:27:23 PM PDT 24 |
| Finished | Aug 14 04:28:16 PM PDT 24 |
| Peak memory | 202464 kb |
| Host | smart-6a417afd-4160-44fd-a739-cb04f7756965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307335971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.307335971 |
| Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4084067863 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 16089994 ps |
| CPU time | 0.67 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:18 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-46750190-f940-40e8-913a-6b17920211ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084067863 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.4084067863 |
| Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4024639185 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 150691667 ps |
| CPU time | 3.45 seconds |
| Started | Aug 14 04:27:23 PM PDT 24 |
| Finished | Aug 14 04:27:26 PM PDT 24 |
| Peak memory | 202308 kb |
| Host | smart-d7b6fec2-afed-4101-bb5b-3e391c900a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024639185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.4024639185 |
| Directory | /workspace/16.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3702212724 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 167425956 ps |
| CPU time | 2.05 seconds |
| Started | Aug 14 04:27:22 PM PDT 24 |
| Finished | Aug 14 04:27:24 PM PDT 24 |
| Peak memory | 210528 kb |
| Host | smart-364c4301-e32a-4691-99f2-f6ff1e3a8681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702212724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.3702212724 |
| Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2133414591 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 373057934 ps |
| CPU time | 4.8 seconds |
| Started | Aug 14 04:28:35 PM PDT 24 |
| Finished | Aug 14 04:28:40 PM PDT 24 |
| Peak memory | 210600 kb |
| Host | smart-86898d0c-7c90-4371-bfbc-52fcfe97de27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133414591 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2133414591 |
| Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.909560830 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 11321815 ps |
| CPU time | 0.65 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:19 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-f2c4b7b7-64f7-49a6-864f-d04a949ab06e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909560830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.909560830 |
| Directory | /workspace/17.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.108976716 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 17651427052 ps |
| CPU time | 30.21 seconds |
| Started | Aug 14 04:27:27 PM PDT 24 |
| Finished | Aug 14 04:27:57 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-fd465d42-c570-4047-9c01-312b335444b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108976716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.108976716 |
| Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3303787037 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 85099417 ps |
| CPU time | 0.71 seconds |
| Started | Aug 14 04:27:23 PM PDT 24 |
| Finished | Aug 14 04:27:24 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-96a0b932-d523-448d-ae15-ee387bac3ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303787037 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3303787037 |
| Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3792765563 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 87189177 ps |
| CPU time | 2.02 seconds |
| Started | Aug 14 04:28:14 PM PDT 24 |
| Finished | Aug 14 04:28:17 PM PDT 24 |
| Peak memory | 201532 kb |
| Host | smart-a2f6e494-3939-4898-9874-de4cb5670533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792765563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.3792765563 |
| Directory | /workspace/17.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4184601870 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 217513169 ps |
| CPU time | 1.49 seconds |
| Started | Aug 14 04:27:39 PM PDT 24 |
| Finished | Aug 14 04:27:41 PM PDT 24 |
| Peak memory | 210524 kb |
| Host | smart-498a48d2-38b1-4484-bab9-1689088660ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184601870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.4184601870 |
| Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1496385439 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 375782840 ps |
| CPU time | 3.18 seconds |
| Started | Aug 14 04:27:27 PM PDT 24 |
| Finished | Aug 14 04:27:30 PM PDT 24 |
| Peak memory | 210320 kb |
| Host | smart-2006b309-b21f-4942-8737-0c708a584c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496385439 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1496385439 |
| Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2611820597 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13336950 ps |
| CPU time | 0.67 seconds |
| Started | Aug 14 04:27:27 PM PDT 24 |
| Finished | Aug 14 04:27:28 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-494a368c-b9db-4bb5-b413-c63d8b44d0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611820597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.2611820597 |
| Directory | /workspace/18.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3154554769 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3709046297 ps |
| CPU time | 26.77 seconds |
| Started | Aug 14 04:27:14 PM PDT 24 |
| Finished | Aug 14 04:27:41 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-f007b89e-5c68-43b7-ada4-339d698d0923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154554769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3154554769 |
| Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2139543058 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 18163729 ps |
| CPU time | 0.71 seconds |
| Started | Aug 14 04:27:36 PM PDT 24 |
| Finished | Aug 14 04:27:37 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-02348c05-690f-4381-b5ac-54837346d592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139543058 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.2139543058 |
| Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3492753963 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 391286181 ps |
| CPU time | 2.54 seconds |
| Started | Aug 14 04:27:29 PM PDT 24 |
| Finished | Aug 14 04:27:32 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-34c35ee8-07f1-407b-87e4-342784a4ddbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492753963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3492753963 |
| Directory | /workspace/18.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.364548627 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 176479143 ps |
| CPU time | 2.06 seconds |
| Started | Aug 14 04:27:19 PM PDT 24 |
| Finished | Aug 14 04:27:22 PM PDT 24 |
| Peak memory | 210512 kb |
| Host | smart-3f009f09-40d5-44b5-97fa-23a7045069e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364548627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.sram_ctrl_tl_intg_err.364548627 |
| Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2869559633 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 702330387 ps |
| CPU time | 4.2 seconds |
| Started | Aug 14 04:27:20 PM PDT 24 |
| Finished | Aug 14 04:27:24 PM PDT 24 |
| Peak memory | 211784 kb |
| Host | smart-e0f0f63f-13fa-40eb-83b0-c70a95fc333c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869559633 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.2869559633 |
| Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3685460478 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13833637 ps |
| CPU time | 0.67 seconds |
| Started | Aug 14 04:27:19 PM PDT 24 |
| Finished | Aug 14 04:27:19 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-1e35dae7-9b72-4e87-b878-9fb235648745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685460478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.3685460478 |
| Directory | /workspace/19.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.270559863 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 16735257609 ps |
| CPU time | 31.37 seconds |
| Started | Aug 14 04:27:33 PM PDT 24 |
| Finished | Aug 14 04:28:05 PM PDT 24 |
| Peak memory | 202492 kb |
| Host | smart-499d2b6f-c552-46c8-92ae-87e4980c2a8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270559863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.270559863 |
| Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.238951965 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 18876912 ps |
| CPU time | 0.74 seconds |
| Started | Aug 14 04:27:31 PM PDT 24 |
| Finished | Aug 14 04:27:32 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-f29035ca-2a92-4f27-baab-89f32a80d68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238951965 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.238951965 |
| Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.654945784 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 42588503 ps |
| CPU time | 2.11 seconds |
| Started | Aug 14 04:27:16 PM PDT 24 |
| Finished | Aug 14 04:27:18 PM PDT 24 |
| Peak memory | 202356 kb |
| Host | smart-fb304e27-4f9b-4edb-b9c3-fb608c025fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654945784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.654945784 |
| Directory | /workspace/19.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1581787519 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 131477756 ps |
| CPU time | 1.51 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:17 PM PDT 24 |
| Peak memory | 210440 kb |
| Host | smart-61a27b49-ff87-4cdb-9ed3-6d91a37c2c75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581787519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.1581787519 |
| Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.390741253 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 35269331 ps |
| CPU time | 0.67 seconds |
| Started | Aug 14 04:27:10 PM PDT 24 |
| Finished | Aug 14 04:27:11 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-a82d41b6-1596-4386-b83c-7f8f41c5b03b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390741253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.390741253 |
| Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.366098039 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 177283588 ps |
| CPU time | 1.9 seconds |
| Started | Aug 14 04:27:23 PM PDT 24 |
| Finished | Aug 14 04:27:25 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-d38e7228-f30e-4fee-aab8-ba662a8f1ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366098039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.366098039 |
| Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2386453333 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 49785323 ps |
| CPU time | 0.65 seconds |
| Started | Aug 14 04:27:21 PM PDT 24 |
| Finished | Aug 14 04:27:22 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-7d925e8f-6db8-4da4-a0c2-40d25ea56043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386453333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.2386453333 |
| Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2262521476 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1328454417 ps |
| CPU time | 4.22 seconds |
| Started | Aug 14 04:27:28 PM PDT 24 |
| Finished | Aug 14 04:27:32 PM PDT 24 |
| Peak memory | 210540 kb |
| Host | smart-84e56d53-d250-4737-9408-c4c003f5313c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262521476 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2262521476 |
| Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1549008335 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12196152 ps |
| CPU time | 0.65 seconds |
| Started | Aug 14 04:27:21 PM PDT 24 |
| Finished | Aug 14 04:27:22 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-62167f3b-1601-4d59-a090-f48b9c2a15cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549008335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.1549008335 |
| Directory | /workspace/2.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1251456156 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4401946376 ps |
| CPU time | 29.68 seconds |
| Started | Aug 14 04:27:21 PM PDT 24 |
| Finished | Aug 14 04:27:51 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-314b78b8-20a2-4bdf-9f44-ce0aab64140c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251456156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1251456156 |
| Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2239103305 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26483071 ps |
| CPU time | 0.69 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:16 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-7464d6f6-00fc-4e2d-95ab-efa48744138f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239103305 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.2239103305 |
| Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3278025147 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 100770551 ps |
| CPU time | 3.16 seconds |
| Started | Aug 14 04:27:08 PM PDT 24 |
| Finished | Aug 14 04:27:12 PM PDT 24 |
| Peak memory | 202380 kb |
| Host | smart-2e249854-1c24-409c-b60b-d07190ba670d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278025147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.3278025147 |
| Directory | /workspace/2.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3321192993 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 105269805 ps |
| CPU time | 1.53 seconds |
| Started | Aug 14 04:27:27 PM PDT 24 |
| Finished | Aug 14 04:27:29 PM PDT 24 |
| Peak memory | 210512 kb |
| Host | smart-73b7844b-292f-41a6-9395-bb26030d8734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321192993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.3321192993 |
| Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.449914305 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 16527928 ps |
| CPU time | 0.74 seconds |
| Started | Aug 14 04:27:28 PM PDT 24 |
| Finished | Aug 14 04:27:29 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-3ea808be-2da1-4df3-885d-c7720dc5ab90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449914305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.449914305 |
| Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.625795982 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 241106108 ps |
| CPU time | 1.45 seconds |
| Started | Aug 14 04:27:19 PM PDT 24 |
| Finished | Aug 14 04:27:21 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-744c6bb8-0419-4a70-af2e-87ad7df64456 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625795982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_bash.625795982 |
| Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.685477494 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 23172423 ps |
| CPU time | 0.68 seconds |
| Started | Aug 14 04:27:30 PM PDT 24 |
| Finished | Aug 14 04:27:31 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-0a531225-9c5a-49ea-92ea-3102b5f5d565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685477494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.685477494 |
| Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1358244769 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 49524180 ps |
| CPU time | 0.65 seconds |
| Started | Aug 14 04:27:01 PM PDT 24 |
| Finished | Aug 14 04:27:02 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-a5a21666-c9c1-4dc1-80b2-1364bab252b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358244769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.1358244769 |
| Directory | /workspace/3.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1643687704 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 26432954808 ps |
| CPU time | 32.25 seconds |
| Started | Aug 14 04:27:13 PM PDT 24 |
| Finished | Aug 14 04:27:46 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-da80b141-d852-41a5-b515-d405c7d91d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643687704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1643687704 |
| Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1203295712 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 59145496 ps |
| CPU time | 0.72 seconds |
| Started | Aug 14 04:27:14 PM PDT 24 |
| Finished | Aug 14 04:27:14 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-78d2145d-e905-4df5-8992-353656b12517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203295712 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1203295712 |
| Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.206589917 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 92804950 ps |
| CPU time | 2.93 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:18 PM PDT 24 |
| Peak memory | 210512 kb |
| Host | smart-8544e459-36ac-4d8c-a5de-674389147aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206589917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.206589917 |
| Directory | /workspace/3.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1979443137 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 163452626 ps |
| CPU time | 1.38 seconds |
| Started | Aug 14 04:27:11 PM PDT 24 |
| Finished | Aug 14 04:27:13 PM PDT 24 |
| Peak memory | 210476 kb |
| Host | smart-e6cf18c0-0bbd-4319-af97-02dfc5184876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979443137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.1979443137 |
| Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3121884465 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 19670251 ps |
| CPU time | 0.74 seconds |
| Started | Aug 14 04:27:07 PM PDT 24 |
| Finished | Aug 14 04:27:08 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-7f7c3a3d-028f-405c-927e-380bfe22e86f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121884465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.3121884465 |
| Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2930940900 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 301375878 ps |
| CPU time | 2.25 seconds |
| Started | Aug 14 04:27:12 PM PDT 24 |
| Finished | Aug 14 04:27:15 PM PDT 24 |
| Peak memory | 202328 kb |
| Host | smart-bd20a385-5ef7-4877-be8a-65f783455f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930940900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.2930940900 |
| Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.831422017 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 41438060 ps |
| CPU time | 0.69 seconds |
| Started | Aug 14 04:27:14 PM PDT 24 |
| Finished | Aug 14 04:27:15 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-ed9fc5e8-bc24-452c-9be2-ddceb9c57e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831422017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_reset.831422017 |
| Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4290316602 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 717976886 ps |
| CPU time | 3.81 seconds |
| Started | Aug 14 04:27:14 PM PDT 24 |
| Finished | Aug 14 04:27:18 PM PDT 24 |
| Peak memory | 210324 kb |
| Host | smart-3b530d8a-d324-4100-90a5-7cb09c8d8884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290316602 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.4290316602 |
| Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1221534790 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 40625628 ps |
| CPU time | 0.66 seconds |
| Started | Aug 14 04:27:08 PM PDT 24 |
| Finished | Aug 14 04:27:09 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-746b8021-453b-4de5-9a68-dc4a5ea3df37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221534790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.1221534790 |
| Directory | /workspace/4.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2373282745 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 33101105 ps |
| CPU time | 0.71 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:19 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-88e3c07b-fa53-4247-8d81-492f621dadbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373282745 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2373282745 |
| Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3500015929 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1355974802 ps |
| CPU time | 2.49 seconds |
| Started | Aug 14 04:27:24 PM PDT 24 |
| Finished | Aug 14 04:27:26 PM PDT 24 |
| Peak memory | 210528 kb |
| Host | smart-3eadc088-e409-459b-aa61-4adbb69dcdf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500015929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.3500015929 |
| Directory | /workspace/4.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2741659246 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 679480987 ps |
| CPU time | 2.32 seconds |
| Started | Aug 14 04:27:17 PM PDT 24 |
| Finished | Aug 14 04:27:20 PM PDT 24 |
| Peak memory | 210516 kb |
| Host | smart-a17bd3e8-1429-4fd8-84ec-e077ad673f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741659246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2741659246 |
| Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2794339442 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1361184540 ps |
| CPU time | 3.41 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:19 PM PDT 24 |
| Peak memory | 201348 kb |
| Host | smart-3040671d-4b92-4636-bd96-c4db57fe34b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794339442 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2794339442 |
| Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1811818630 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 17167813 ps |
| CPU time | 0.63 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:15 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-a718e6f6-a8b1-457b-914c-54591be3c422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811818630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.1811818630 |
| Directory | /workspace/5.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.328125305 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14721861520 ps |
| CPU time | 55.21 seconds |
| Started | Aug 14 04:27:22 PM PDT 24 |
| Finished | Aug 14 04:28:17 PM PDT 24 |
| Peak memory | 202476 kb |
| Host | smart-eb424919-9d0b-4487-89c1-eab6513799ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328125305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.328125305 |
| Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2392768414 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 17974177 ps |
| CPU time | 0.71 seconds |
| Started | Aug 14 04:27:21 PM PDT 24 |
| Finished | Aug 14 04:27:22 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-8315a58d-26ee-4db7-b918-286ade0d921c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392768414 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2392768414 |
| Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1119815002 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 281731935 ps |
| CPU time | 4.7 seconds |
| Started | Aug 14 04:27:24 PM PDT 24 |
| Finished | Aug 14 04:27:29 PM PDT 24 |
| Peak memory | 210904 kb |
| Host | smart-6884528b-e4e4-49bc-b177-544e4b556f25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119815002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.1119815002 |
| Directory | /workspace/5.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2359177586 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 319463898 ps |
| CPU time | 1.4 seconds |
| Started | Aug 14 04:27:16 PM PDT 24 |
| Finished | Aug 14 04:27:17 PM PDT 24 |
| Peak memory | 210140 kb |
| Host | smart-0e59fe15-fa2c-4680-bdca-32251e544ff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359177586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.2359177586 |
| Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3528763687 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 727828980 ps |
| CPU time | 3.31 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:22 PM PDT 24 |
| Peak memory | 210264 kb |
| Host | smart-751cccb4-a6a9-41ed-b92b-f01fa5072e36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528763687 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3528763687 |
| Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3944499702 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 36188853 ps |
| CPU time | 0.63 seconds |
| Started | Aug 14 04:27:25 PM PDT 24 |
| Finished | Aug 14 04:27:26 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-285e7ad5-f991-43c0-bc1f-b23afceab68c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944499702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.3944499702 |
| Directory | /workspace/6.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.311092805 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 29299475753 ps |
| CPU time | 52.86 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:28:08 PM PDT 24 |
| Peak memory | 202512 kb |
| Host | smart-d373ca87-4e5b-4829-be4b-a81396aa94ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311092805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.311092805 |
| Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.307211248 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 50308896 ps |
| CPU time | 0.76 seconds |
| Started | Aug 14 04:27:20 PM PDT 24 |
| Finished | Aug 14 04:27:21 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-d7df0ba0-6d38-4dce-9800-9d67c73475be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307211248 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.307211248 |
| Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.344998529 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 188993986 ps |
| CPU time | 3.5 seconds |
| Started | Aug 14 04:27:27 PM PDT 24 |
| Finished | Aug 14 04:27:30 PM PDT 24 |
| Peak memory | 202316 kb |
| Host | smart-d2ce2fff-101d-45f6-ab65-aa4595327ad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344998529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.344998529 |
| Directory | /workspace/6.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3409664381 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1036211295 ps |
| CPU time | 2.47 seconds |
| Started | Aug 14 04:27:11 PM PDT 24 |
| Finished | Aug 14 04:27:14 PM PDT 24 |
| Peak memory | 210460 kb |
| Host | smart-b557fe37-e164-4d8b-8851-4c703772b044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409664381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.3409664381 |
| Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3543312059 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2689711907 ps |
| CPU time | 4.41 seconds |
| Started | Aug 14 04:27:41 PM PDT 24 |
| Finished | Aug 14 04:27:45 PM PDT 24 |
| Peak memory | 210812 kb |
| Host | smart-d85ffa89-9580-4bf6-b4ab-a97529193ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543312059 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3543312059 |
| Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1047437464 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 30688990 ps |
| CPU time | 0.64 seconds |
| Started | Aug 14 04:27:19 PM PDT 24 |
| Finished | Aug 14 04:27:20 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-fef17537-0cdb-4186-8dc5-d36d62d897ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047437464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.1047437464 |
| Directory | /workspace/7.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.182792202 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4358014735 ps |
| CPU time | 29.31 seconds |
| Started | Aug 14 04:27:34 PM PDT 24 |
| Finished | Aug 14 04:28:03 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-df9342c5-0ddf-4c56-b8c1-4aa9d0e987f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182792202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.182792202 |
| Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3636406035 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 208207158 ps |
| CPU time | 0.78 seconds |
| Started | Aug 14 04:27:33 PM PDT 24 |
| Finished | Aug 14 04:27:34 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-1c3d6b5e-a36a-4636-8981-1fe66361ea0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636406035 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3636406035 |
| Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2192127848 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 139061561 ps |
| CPU time | 2.7 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:21 PM PDT 24 |
| Peak memory | 202312 kb |
| Host | smart-75958671-3e53-415a-992f-7aaf5fe9c33e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192127848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2192127848 |
| Directory | /workspace/7.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2683516772 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 184028554 ps |
| CPU time | 2.26 seconds |
| Started | Aug 14 04:27:17 PM PDT 24 |
| Finished | Aug 14 04:27:20 PM PDT 24 |
| Peak memory | 210512 kb |
| Host | smart-912be7bf-c4d8-4fef-8b00-994614e1eb0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683516772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2683516772 |
| Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2340744070 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 360434580 ps |
| CPU time | 3.21 seconds |
| Started | Aug 14 04:27:12 PM PDT 24 |
| Finished | Aug 14 04:27:15 PM PDT 24 |
| Peak memory | 210324 kb |
| Host | smart-ea662737-6c2d-4f39-98d1-8ffdd2cb0640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340744070 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2340744070 |
| Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3875067528 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12140785 ps |
| CPU time | 0.68 seconds |
| Started | Aug 14 04:27:29 PM PDT 24 |
| Finished | Aug 14 04:27:29 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-912eca55-f6ca-4eb0-896a-98cba195d296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875067528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.3875067528 |
| Directory | /workspace/8.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1496969902 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14681263980 ps |
| CPU time | 50.97 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:28:06 PM PDT 24 |
| Peak memory | 202456 kb |
| Host | smart-3682efc1-662f-4412-b68c-9f4979cbd614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496969902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1496969902 |
| Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2370454730 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 39368377 ps |
| CPU time | 0.72 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:16 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-ab138678-2db4-4bae-9a5a-8708c3e987da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370454730 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2370454730 |
| Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3576313661 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 430742910 ps |
| CPU time | 3.92 seconds |
| Started | Aug 14 04:27:27 PM PDT 24 |
| Finished | Aug 14 04:27:31 PM PDT 24 |
| Peak memory | 210588 kb |
| Host | smart-4eeab9ed-ab98-4cfc-a100-4f261bd5def2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576313661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.3576313661 |
| Directory | /workspace/8.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3957133249 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 704325038 ps |
| CPU time | 3.65 seconds |
| Started | Aug 14 04:27:18 PM PDT 24 |
| Finished | Aug 14 04:27:22 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-c14bf1ef-c029-4e73-a59c-c2f326bcb146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957133249 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3957133249 |
| Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1058928546 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 46200555 ps |
| CPU time | 0.72 seconds |
| Started | Aug 14 04:27:15 PM PDT 24 |
| Finished | Aug 14 04:27:16 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-826acecb-26de-4d94-9307-4a47f45e2c6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058928546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.1058928546 |
| Directory | /workspace/9.sram_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2430921136 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 5280670586 ps |
| CPU time | 27.08 seconds |
| Started | Aug 14 04:27:17 PM PDT 24 |
| Finished | Aug 14 04:27:44 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-13bfb409-57dc-460e-b803-5068598e954e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430921136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2430921136 |
| Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3315763271 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 18902625 ps |
| CPU time | 0.7 seconds |
| Started | Aug 14 04:27:17 PM PDT 24 |
| Finished | Aug 14 04:27:17 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-6ff761c7-c0c1-47f2-a62b-0aef84861bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315763271 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3315763271 |
| Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1019549770 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 197927022 ps |
| CPU time | 1.89 seconds |
| Started | Aug 14 04:27:34 PM PDT 24 |
| Finished | Aug 14 04:27:36 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-fa5e4851-ba33-4d44-a99f-8b234a739595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019549770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.1019549770 |
| Directory | /workspace/9.sram_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2208780937 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 328282413 ps |
| CPU time | 1.54 seconds |
| Started | Aug 14 04:27:25 PM PDT 24 |
| Finished | Aug 14 04:27:27 PM PDT 24 |
| Peak memory | 210480 kb |
| Host | smart-40fea772-8fb0-41ff-b448-a7d5fe2d9c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208780937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.2208780937 |
| Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |