Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 1 3 75.00
Crosses 4 2 2 50.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
escalated_cp 2 1 1 50.00 100 1 1 2
key_seed_valid_cp 2 0 2 100.00 100 1 1 2


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::key_seed_valid_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_seed_valid_cross 4 2 2 50.00 100 1 1 0


Summary for Variable escalated_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for escalated_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 350 1 T3 11 T4 21 T5 11



Summary for Variable key_seed_valid_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_seed_valid_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 171 1 T3 5 T4 10 T5 3
auto[1] 179 1 T3 6 T4 11 T5 8



Summary for Cross key_seed_valid_cross

Samples crossed: key_seed_valid_cp escalated_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for key_seed_valid_cross

Element holes
key_seed_valid_cpescalated_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
key_seed_valid_cpescalated_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 171 1 T3 5 T4 10 T5 3
auto[1] auto[0] 179 1 T3 6 T4 11 T5 8

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