Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 16 0 16 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_exec_cp 3 0 3 100.00 100 1 1 0
en_sram_ifetch_cp 3 0 3 100.00 100 1 1 0
lc_hw_debug_en_cp 3 0 3 100.00 100 1 1 0


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
executable_cross 16 0 16 100.00 100 1 1 0


Summary for Variable csr_exec_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csr_exec_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
instr_invalid_dis 356651100 1 T1 353554 T2 17042 T3 441686
instr_valid_dis 314977223 1 T1 197884 T2 17042 T3 441686
instr_en 30814998 1 T1 101576 T4 132900 T6 334632



Summary for Variable en_sram_ifetch_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for en_sram_ifetch_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_ifetch_invalid_disable 10789802 1 T4 150600 T6 195166 T27 200156
sram_ifetch_valid_disable 315824002 1 T1 179320 T2 17042 T3 441686
sram_ifetch_enable 30037296 1 T1 174234 T4 72290 T6 265330



Summary for Variable lc_hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for lc_hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off 356651100 1 T1 353554 T2 17042 T3 441686
hw_debug_en_valid_off 315306286 1 T1 88656 T2 17042 T3 441686
hw_debug_en_on 28267716 1 T1 248392 T4 196836 T6 293514



Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 16 0 16 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for executable_cross

Bins
lc_hw_debug_en_cpen_sram_ifetch_cpcsr_exec_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_invalid_dis 315824002 1 T1 179320 T2 17042 T3 441686
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_valid_dis 300784511 1 T1 140952 T2 17042 T3 441686
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_en 10854938 1 T1 8758 T6 119074 T94 179324
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_invalid_dis 4174158 1 T6 78512 T27 89760 T94 32550
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_valid_dis 1576560 1 T6 42818 T94 1054 T41 84072
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_en 1746086 1 T6 35694 T27 89760 T94 31496
hw_debug_en_on sram_ifetch_invalid_disable instr_invalid_dis 4261894 1 T4 150600 T6 76444 T27 20886
hw_debug_en_on sram_ifetch_invalid_disable instr_valid_dis 1937640 1 T4 17700 T6 76444 T94 20000
hw_debug_en_on sram_ifetch_invalid_disable instr_en 1273834 1 T4 132900 T27 20886 T20 41670
hw_debug_en_on sram_ifetch_valid_disable instr_invalid_dis 9261014 1 T1 139774 T4 1224 T6 108694
hw_debug_en_on sram_ifetch_valid_disable instr_valid_dis 4115486 1 T1 112582 T4 1224 T6 42834
hw_debug_en_on sram_ifetch_valid_disable instr_en 3403272 1 T1 100 T6 65860 T94 11378


User Defined Cross Bins for executable_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
csr_exec_en 16322780 1 T1 92818 T6 139654 T27 104296
lc_exec_en 14744808 1 T1 108618 T4 45012 T6 108376
valid_exec_dis 309279410 1 T1 93960 T2 17042 T3 441686
invalid_exec_dis 40827098 1 T1 174234 T4 222890 T6 460496

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