Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	149158036	1			T1	85197		T2	6925		T3	40267
triple_byte_access	2697511	1			T1	1722		T2	307		T3	36161
halfword_access	4139132	1			T1	2575		T2	474		T3	53973
byte_access	5797641	1			T1	3541		T2	663		T3	72246
zero_access	1759195	1			T1	823		T2	152		T3	18196

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81492580

1

T1

59008

T2

4303

T3

110713

auto[1]

82058935

1

T1

34850

T2

4218

T3

110130

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	74163644	1			T1	53544		T2	3497		T3	19967
auto[0]	triple_byte_access	1283448	1			T1	1073		T2	168		T3	18114
auto[0]	halfword_access	2020699	1			T1	1656		T2	241		T3	26788
auto[0]	byte_access	2971625	1			T1	2231		T2	328		T3	36629
auto[0]	zero_access	1053164	1			T1	504		T2	69		T3	9215
auto[1]	word_access	74994392	1			T1	31653		T2	3428		T3	20300
auto[1]	triple_byte_access	1414063	1			T1	649		T2	139		T3	18047
auto[1]	halfword_access	2118433	1			T1	919		T2	233		T3	27185
auto[1]	byte_access	2826016	1			T1	1310		T2	335		T3	35617
auto[1]	zero_access	706031	1			T1	319		T2	83		T3	8981