Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	351473222	1			T2	449678		T3	1526		T4	141848
instr_valid_dis	317641658	1			T2	449678		T3	1526		T4	141848
instr_en	24193403	1			T24	13694		T25	104690		T28	53360

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15499118	1			T24	33628		T25	19404		T28	50934
sram_ifetch_valid_disable	308536310	1			T2	449678		T3	1526		T4	141848
sram_ifetch_enable	27437794	1			T25	49076		T28	46868		T29	75824

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	351473222	1			T2	449678		T3	1526		T4	141848
hw_debug_en_valid_off	305396682	1			T2	449678		T3	1526		T4	141848
hw_debug_en_on	30547798	1			T24	66		T25	7126		T28	20000

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	308536310	1			T2	449678		T3	1526		T4	141848
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	296996706	1			T2	449678		T3	1526		T4	141848
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8399491	1			T24	66		T25	43580		T28	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5785004	1			T24	13628		T25	244		T28	50934
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2190312	1			T25	244		T19	10292		T145	205952
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2677388	1			T24	13628		T28	33360		T79	14196
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7303594	1			T29	14438		T19	126032		T20	74622
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	4818916	1			T19	126032		T21	31272		T157	16798
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1447666	1			T21	70752		T166	15674		T161	9236
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10848790	1			T24	66		T29	7748		T79	40498
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6440328	1			T158	60100		T157	41278		T145	148646
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3342856	1			T24	66		T79	40498		T21	55340

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10964964	1			T25	41950		T79	77758		T158	34412
lc_exec_en	12395414	1			T25	7126		T28	20000		T29	55032
valid_exec_dis	304245376	1			T2	449678		T3	1526		T4	141848
invalid_exec_dis	42936912	1			T24	33628		T25	68480		T28	97802