Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.19 94.27 99.72 100.00 96.03 99.12 97.26


Total tests in report: 1034
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
69.21 69.21 90.11 90.11 68.25 68.25 89.46 89.46 23.81 23.81 78.20 78.20 92.98 92.98 41.68 41.68 /workspace/coverage/default/46.sram_ctrl_multiple_keys.4225790788
81.85 12.64 95.09 4.99 72.51 4.27 92.22 2.75 90.48 66.67 86.02 7.82 94.59 1.61 42.05 0.37 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.4041508785
89.22 7.37 96.16 1.06 81.40 8.89 95.63 3.41 90.48 0.00 88.39 2.37 96.78 2.19 75.69 33.64 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4051137241
92.75 3.53 97.47 1.31 85.90 4.50 96.11 0.48 100.00 9.52 92.18 3.79 96.78 0.00 80.80 5.12 /workspace/coverage/default/32.sram_ctrl_stress_all.1870555289
93.79 1.04 98.69 1.23 86.02 0.12 96.66 0.55 100.00 0.00 93.60 1.42 97.08 0.29 84.46 3.66 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3697317470
94.67 0.88 99.02 0.33 88.03 2.01 97.56 0.90 100.00 0.00 95.02 1.42 97.66 0.58 85.37 0.91 /workspace/coverage/default/3.sram_ctrl_sec_cm.2628839086
95.54 0.88 99.10 0.08 88.86 0.83 98.45 0.90 100.00 0.00 95.73 0.71 97.81 0.15 88.85 3.47 /workspace/coverage/default/32.sram_ctrl_regwen.1430087185
96.25 0.70 99.10 0.00 89.22 0.36 98.45 0.00 100.00 0.00 95.73 0.00 97.81 0.00 93.42 4.57 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.845814571
96.55 0.30 99.10 0.00 89.93 0.71 98.55 0.10 100.00 0.00 95.73 0.00 97.81 0.00 94.70 1.28 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1337290017
96.83 0.28 99.10 0.00 90.17 0.24 98.62 0.07 100.00 0.00 95.73 0.00 99.12 1.32 95.06 0.37 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3909360119
96.96 0.13 99.18 0.08 90.17 0.00 99.48 0.86 100.00 0.00 95.73 0.00 99.12 0.00 95.06 0.00 /workspace/coverage/default/17.sram_ctrl_ram_cfg.620744127
97.07 0.10 99.18 0.00 90.17 0.00 99.48 0.00 100.00 0.00 95.73 0.00 99.12 0.00 95.80 0.73 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4088061654
97.16 0.09 99.18 0.00 90.64 0.47 99.62 0.14 100.00 0.00 95.73 0.00 99.12 0.00 95.80 0.00 /workspace/coverage/default/17.sram_ctrl_alert_test.3060041413
97.24 0.08 99.18 0.00 90.76 0.12 99.62 0.00 100.00 0.00 96.21 0.47 99.12 0.00 95.80 0.00 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.36927832
97.32 0.08 99.18 0.00 90.76 0.00 99.62 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.34 0.55 /workspace/coverage/default/13.sram_ctrl_stress_all.3374658856
97.37 0.05 99.18 0.00 90.76 0.00 99.62 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.71 0.37 /workspace/coverage/default/8.sram_ctrl_regwen.1235119311
97.42 0.05 99.18 0.00 91.00 0.24 99.72 0.10 100.00 0.00 96.21 0.00 99.12 0.00 96.71 0.00 /workspace/coverage/default/17.sram_ctrl_lc_escalation.3342243594
97.45 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.89 0.18 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3052977227
97.47 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.07 0.18 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1499264747
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1486511854

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1218171060
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2629168752
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3578704907
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2886344231
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2844317323
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3565168692
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.200867026
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2656577255
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.62985981
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1933243975
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1142182403
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3265369259
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4246025515
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3660247857
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.737968490
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1564906940
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3827336943
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2190377943
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.769519861
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.671744003
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3617417453
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2305934619
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.778571409
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1177543665
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1427046755
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2647380445
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.307529189
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3645633780
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.493859476
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2171591183
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3202522801
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3786989645
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.850787119
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1714792688
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.496951717
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3491457706
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.764211927
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4055169563
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1440205899
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3849183839
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1355076173
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1245250319
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2093844202
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3280376816
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1132342580
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3125358010
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2467469528
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2846603491
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1867449567
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1398725787
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3282977829
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2989523615
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3987329710
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2828614896
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3072105619
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1385047548
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.925107304
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1627105464
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4264649026
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.686061776
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1371892443
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1618881237
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.650255285
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1298760155
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.93181730
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1831432086
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3466323417
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.490301984
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.106370572
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2747627208
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2892472551
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.291178180
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4171875271
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2720876528
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2505363858
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3755384407
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1010964990
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2854899854
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2550654818
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.106017402
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1643532189
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2804243799
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1903475424
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4263352662
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3142848496
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3288330975
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2280235012
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2955137887
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.396593872
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1721487439
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2692104749
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1467367548
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3615349524
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1471586715
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1919424971
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3551896538
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4175315540
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2234818110
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1164686195
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3262999928
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.39235922
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1170630212
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1769463497
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1162342825
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2472235039
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4129433548
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1056628498
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3943093627
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1609078250
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2501840113
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.691692208
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2176229880
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2969375327
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.838284836
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2237468137
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2786025696
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3097856616
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.627411362
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.663525220
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1183633781
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.447971032
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4105108666
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1730705384
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3837524349
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3791917137
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1433064448
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.583698259
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4125802853
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.564315291
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2519962640
/workspace/coverage/default/0.sram_ctrl_alert_test.3965513142
/workspace/coverage/default/0.sram_ctrl_bijection.2226977587
/workspace/coverage/default/0.sram_ctrl_executable.710318061
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3633406350
/workspace/coverage/default/0.sram_ctrl_max_throughput.2647038432
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.4135899579
/workspace/coverage/default/0.sram_ctrl_mem_walk.1023410033
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1280362687
/workspace/coverage/default/0.sram_ctrl_partial_access.1513885632
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3665376187
/workspace/coverage/default/0.sram_ctrl_ram_cfg.4193822097
/workspace/coverage/default/0.sram_ctrl_regwen.887811343
/workspace/coverage/default/0.sram_ctrl_sec_cm.1212127037
/workspace/coverage/default/0.sram_ctrl_smoke.1765719861
/workspace/coverage/default/0.sram_ctrl_stress_all.2565576072
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1529545236
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3192410257
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.50285490
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2053422154
/workspace/coverage/default/1.sram_ctrl_alert_test.2380653003
/workspace/coverage/default/1.sram_ctrl_bijection.1856480088
/workspace/coverage/default/1.sram_ctrl_executable.2043526646
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3945143318
/workspace/coverage/default/1.sram_ctrl_max_throughput.2818069758
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3217714415
/workspace/coverage/default/1.sram_ctrl_mem_walk.2844436418
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2455807923
/workspace/coverage/default/1.sram_ctrl_partial_access.828276173
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1344207709
/workspace/coverage/default/1.sram_ctrl_ram_cfg.21672027
/workspace/coverage/default/1.sram_ctrl_regwen.3524627763
/workspace/coverage/default/1.sram_ctrl_sec_cm.3379839781
/workspace/coverage/default/1.sram_ctrl_smoke.143691701
/workspace/coverage/default/1.sram_ctrl_stress_all.2389790123
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1495016052
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.4170797655
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3376008698
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3288188679
/workspace/coverage/default/10.sram_ctrl_alert_test.2280209348
/workspace/coverage/default/10.sram_ctrl_bijection.1691937803
/workspace/coverage/default/10.sram_ctrl_executable.3616528456
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1970540044
/workspace/coverage/default/10.sram_ctrl_max_throughput.2817195471
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2299527877
/workspace/coverage/default/10.sram_ctrl_mem_walk.1125609872
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1337654494
/workspace/coverage/default/10.sram_ctrl_partial_access.931589734
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2172454554
/workspace/coverage/default/10.sram_ctrl_ram_cfg.252511170
/workspace/coverage/default/10.sram_ctrl_regwen.1979804890
/workspace/coverage/default/10.sram_ctrl_smoke.952785318
/workspace/coverage/default/10.sram_ctrl_stress_all.1768580199
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1827242644
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3258300381
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3592745037
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2992589855
/workspace/coverage/default/11.sram_ctrl_alert_test.778146299
/workspace/coverage/default/11.sram_ctrl_bijection.2038176856
/workspace/coverage/default/11.sram_ctrl_executable.3262700540
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2416410192
/workspace/coverage/default/11.sram_ctrl_max_throughput.2781724008
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.712825922
/workspace/coverage/default/11.sram_ctrl_mem_walk.2527942266
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3781134902
/workspace/coverage/default/11.sram_ctrl_partial_access.2938604950
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2000673704
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2291342984
/workspace/coverage/default/11.sram_ctrl_regwen.918333847
/workspace/coverage/default/11.sram_ctrl_smoke.3463030650
/workspace/coverage/default/11.sram_ctrl_stress_all.4058927914
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3397908630
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3234235719
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/workspace/coverage/default/42.sram_ctrl_stress_all.968706334
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1485633312
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2276338432
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1060339322
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.4023858223
/workspace/coverage/default/43.sram_ctrl_alert_test.1609062464
/workspace/coverage/default/43.sram_ctrl_bijection.236838653
/workspace/coverage/default/43.sram_ctrl_executable.376299215
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2546276983
/workspace/coverage/default/43.sram_ctrl_max_throughput.4178766685
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2813400157
/workspace/coverage/default/43.sram_ctrl_mem_walk.3619592505
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2896485488
/workspace/coverage/default/43.sram_ctrl_partial_access.2545088037
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1312707067
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1423700423
/workspace/coverage/default/43.sram_ctrl_regwen.2056173345
/workspace/coverage/default/43.sram_ctrl_smoke.155862198
/workspace/coverage/default/43.sram_ctrl_stress_all.4147769371
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2954241209
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2796478389
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2339650068
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2420469615
/workspace/coverage/default/44.sram_ctrl_alert_test.3611133218
/workspace/coverage/default/44.sram_ctrl_bijection.2123432922
/workspace/coverage/default/44.sram_ctrl_executable.2051815958
/workspace/coverage/default/44.sram_ctrl_lc_escalation.685199370
/workspace/coverage/default/44.sram_ctrl_max_throughput.4173466245
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.603895875
/workspace/coverage/default/44.sram_ctrl_mem_walk.1569270511
/workspace/coverage/default/44.sram_ctrl_multiple_keys.270595132
/workspace/coverage/default/44.sram_ctrl_partial_access.3564115574
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1194211197
/workspace/coverage/default/44.sram_ctrl_ram_cfg.554573757
/workspace/coverage/default/44.sram_ctrl_regwen.337350282
/workspace/coverage/default/44.sram_ctrl_smoke.505825700
/workspace/coverage/default/44.sram_ctrl_stress_all.351579747
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3718133872
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1240400791
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.203860891
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3547723029
/workspace/coverage/default/45.sram_ctrl_alert_test.1519207724
/workspace/coverage/default/45.sram_ctrl_bijection.2351077275
/workspace/coverage/default/45.sram_ctrl_executable.1488420371
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3245064082
/workspace/coverage/default/45.sram_ctrl_max_throughput.1782953029
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2364511675
/workspace/coverage/default/45.sram_ctrl_mem_walk.20415571
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2298513988
/workspace/coverage/default/45.sram_ctrl_partial_access.4023598210
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3793065091
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2545340876
/workspace/coverage/default/45.sram_ctrl_regwen.1111652308
/workspace/coverage/default/45.sram_ctrl_smoke.2567727165
/workspace/coverage/default/45.sram_ctrl_stress_all.4265982505
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2443561907
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.910580764
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3086353697
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3519968559
/workspace/coverage/default/46.sram_ctrl_alert_test.77745821
/workspace/coverage/default/46.sram_ctrl_bijection.3728244557
/workspace/coverage/default/46.sram_ctrl_executable.3784612342
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2755774140
/workspace/coverage/default/46.sram_ctrl_max_throughput.3735583816
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1319562360
/workspace/coverage/default/46.sram_ctrl_mem_walk.308192221
/workspace/coverage/default/46.sram_ctrl_partial_access.2463219777
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1239137169
/workspace/coverage/default/46.sram_ctrl_regwen.1067351461
/workspace/coverage/default/46.sram_ctrl_smoke.4036844576
/workspace/coverage/default/46.sram_ctrl_stress_all.334827558
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.853927181
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.591254869
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3343648838
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1530241945
/workspace/coverage/default/47.sram_ctrl_alert_test.1371043171
/workspace/coverage/default/47.sram_ctrl_bijection.4145520792
/workspace/coverage/default/47.sram_ctrl_executable.3748003283
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1970635848
/workspace/coverage/default/47.sram_ctrl_max_throughput.3681825773
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3603629828
/workspace/coverage/default/47.sram_ctrl_mem_walk.1849185169
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3849627773
/workspace/coverage/default/47.sram_ctrl_partial_access.126131447
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1823730857
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2005403194
/workspace/coverage/default/47.sram_ctrl_regwen.1525298101
/workspace/coverage/default/47.sram_ctrl_smoke.464099513
/workspace/coverage/default/47.sram_ctrl_stress_all.1891495618
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1607694342
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.112813756
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2954775954
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3999558095
/workspace/coverage/default/48.sram_ctrl_alert_test.553440392
/workspace/coverage/default/48.sram_ctrl_bijection.3691235890
/workspace/coverage/default/48.sram_ctrl_executable.1248074260
/workspace/coverage/default/48.sram_ctrl_lc_escalation.88219024
/workspace/coverage/default/48.sram_ctrl_max_throughput.801151011
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.284703355
/workspace/coverage/default/48.sram_ctrl_mem_walk.2067049803
/workspace/coverage/default/48.sram_ctrl_multiple_keys.601242788
/workspace/coverage/default/48.sram_ctrl_partial_access.3140011072
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3377385005
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3250960243
/workspace/coverage/default/48.sram_ctrl_regwen.3660189698
/workspace/coverage/default/48.sram_ctrl_smoke.2748335729
/workspace/coverage/default/48.sram_ctrl_stress_all.1063390995
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1069287499
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2771336745
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3072367201
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1597085192
/workspace/coverage/default/49.sram_ctrl_alert_test.1978882270
/workspace/coverage/default/49.sram_ctrl_bijection.3259760050
/workspace/coverage/default/49.sram_ctrl_executable.4276380086
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1747674856
/workspace/coverage/default/49.sram_ctrl_max_throughput.2475068126
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3763699
/workspace/coverage/default/49.sram_ctrl_mem_walk.903535823
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1567399103
/workspace/coverage/default/49.sram_ctrl_partial_access.2278634109
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1008821118
/workspace/coverage/default/49.sram_ctrl_ram_cfg.986580161
/workspace/coverage/default/49.sram_ctrl_regwen.277524248
/workspace/coverage/default/49.sram_ctrl_smoke.4256766385
/workspace/coverage/default/49.sram_ctrl_stress_all.2938494640
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2296855072
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2234772395
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.746706067
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2421573252
/workspace/coverage/default/5.sram_ctrl_alert_test.3543177014
/workspace/coverage/default/5.sram_ctrl_executable.3050026479
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1517242127
/workspace/coverage/default/5.sram_ctrl_max_throughput.3643321372
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.128110841
/workspace/coverage/default/5.sram_ctrl_mem_walk.3505457476
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2520576630
/workspace/coverage/default/5.sram_ctrl_partial_access.396699953
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3890456422
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3343357707
/workspace/coverage/default/5.sram_ctrl_regwen.723485446
/workspace/coverage/default/5.sram_ctrl_smoke.1925362174
/workspace/coverage/default/5.sram_ctrl_stress_all.1436507711
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.275207988
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.908676497
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3636241996
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.271604063
/workspace/coverage/default/6.sram_ctrl_alert_test.1795964421
/workspace/coverage/default/6.sram_ctrl_bijection.2918151447
/workspace/coverage/default/6.sram_ctrl_executable.3102299590
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3325311015
/workspace/coverage/default/6.sram_ctrl_max_throughput.2325517608
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1547025347
/workspace/coverage/default/6.sram_ctrl_mem_walk.363500532
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1363298993
/workspace/coverage/default/6.sram_ctrl_partial_access.1645686783
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3379181221
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2578749851
/workspace/coverage/default/6.sram_ctrl_regwen.4112071321
/workspace/coverage/default/6.sram_ctrl_smoke.2853183292
/workspace/coverage/default/6.sram_ctrl_stress_all.2809040365
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.931631235
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.428508168
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1257815915
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2657235653
/workspace/coverage/default/7.sram_ctrl_alert_test.1164586074
/workspace/coverage/default/7.sram_ctrl_bijection.3086169209
/workspace/coverage/default/7.sram_ctrl_executable.3905728639
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1879411049
/workspace/coverage/default/7.sram_ctrl_max_throughput.231084703
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1871668775
/workspace/coverage/default/7.sram_ctrl_mem_walk.1532565620
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1936921201
/workspace/coverage/default/7.sram_ctrl_partial_access.273824011
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1585623926
/workspace/coverage/default/7.sram_ctrl_ram_cfg.4100425057
/workspace/coverage/default/7.sram_ctrl_regwen.883557144
/workspace/coverage/default/7.sram_ctrl_smoke.1861196826
/workspace/coverage/default/7.sram_ctrl_stress_all.3952721382
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.280388660
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3519140446
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3967490295
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2428383578
/workspace/coverage/default/8.sram_ctrl_alert_test.1964690908
/workspace/coverage/default/8.sram_ctrl_bijection.716424567
/workspace/coverage/default/8.sram_ctrl_executable.922796205
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4268871907
/workspace/coverage/default/8.sram_ctrl_max_throughput.1912061979
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.433485386
/workspace/coverage/default/8.sram_ctrl_mem_walk.1150560494
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1694472033
/workspace/coverage/default/8.sram_ctrl_partial_access.149138880
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2582241453
/workspace/coverage/default/8.sram_ctrl_ram_cfg.740205941
/workspace/coverage/default/8.sram_ctrl_smoke.1835747785
/workspace/coverage/default/8.sram_ctrl_stress_all.2724691279
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1861808699
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.302194687
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1910172322
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2885268109
/workspace/coverage/default/9.sram_ctrl_alert_test.2241897574
/workspace/coverage/default/9.sram_ctrl_bijection.184407815
/workspace/coverage/default/9.sram_ctrl_executable.135693039
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3686008286
/workspace/coverage/default/9.sram_ctrl_max_throughput.4265935964
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4058106385
/workspace/coverage/default/9.sram_ctrl_mem_walk.2390900592
/workspace/coverage/default/9.sram_ctrl_multiple_keys.342469529
/workspace/coverage/default/9.sram_ctrl_partial_access.1765730923
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3421561812
/workspace/coverage/default/9.sram_ctrl_ram_cfg.883435299
/workspace/coverage/default/9.sram_ctrl_regwen.166209171
/workspace/coverage/default/9.sram_ctrl_smoke.500110917
/workspace/coverage/default/9.sram_ctrl_stress_all.57406930
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3399339750
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3188257244
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4266594335



Total test records in report: 1034
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/17.sram_ctrl_alert_test.3060041413 Aug 16 05:57:57 PM PDT 24 Aug 16 05:57:58 PM PDT 24 15426931 ps
T2 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.4123948671 Aug 16 05:57:54 PM PDT 24 Aug 16 06:02:30 PM PDT 24 4629294578 ps
T3 /workspace/coverage/default/23.sram_ctrl_smoke.731710468 Aug 16 05:57:59 PM PDT 24 Aug 16 05:58:04 PM PDT 24 356053159 ps
T4 /workspace/coverage/default/46.sram_ctrl_multiple_keys.4225790788 Aug 16 05:59:22 PM PDT 24 Aug 16 06:04:42 PM PDT 24 19142489037 ps
T5 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3697317470 Aug 16 05:59:21 PM PDT 24 Aug 16 06:02:02 PM PDT 24 29793346867 ps
T9 /workspace/coverage/default/37.sram_ctrl_alert_test.2806268465 Aug 16 05:58:42 PM PDT 24 Aug 16 05:58:43 PM PDT 24 15594808 ps
T10 /workspace/coverage/default/42.sram_ctrl_bijection.1959961555 Aug 16 05:59:01 PM PDT 24 Aug 16 06:12:33 PM PDT 24 175304616786 ps
T11 /workspace/coverage/default/27.sram_ctrl_mem_walk.3926107279 Aug 16 05:58:04 PM PDT 24 Aug 16 06:02:08 PM PDT 24 3945926677 ps
T12 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3910959210 Aug 16 05:57:27 PM PDT 24 Aug 16 06:06:57 PM PDT 24 30965550155 ps
T13 /workspace/coverage/default/10.sram_ctrl_bijection.1691937803 Aug 16 05:56:55 PM PDT 24 Aug 16 06:07:46 PM PDT 24 136667197094 ps
T23 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2652519418 Aug 16 05:57:09 PM PDT 24 Aug 16 06:13:32 PM PDT 24 14367063767 ps
T44 /workspace/coverage/default/12.sram_ctrl_mem_walk.3446301174 Aug 16 05:56:57 PM PDT 24 Aug 16 05:59:47 PM PDT 24 38476744218 ps
T24 /workspace/coverage/default/1.sram_ctrl_executable.2043526646 Aug 16 05:57:15 PM PDT 24 Aug 16 05:59:14 PM PDT 24 2480194070 ps
T48 /workspace/coverage/default/20.sram_ctrl_max_throughput.1132731815 Aug 16 05:57:45 PM PDT 24 Aug 16 05:57:53 PM PDT 24 3977133416 ps
T25 /workspace/coverage/default/31.sram_ctrl_executable.1064031677 Aug 16 05:58:12 PM PDT 24 Aug 16 06:02:37 PM PDT 24 34654551293 ps
T45 /workspace/coverage/default/38.sram_ctrl_multiple_keys.724503312 Aug 16 05:58:47 PM PDT 24 Aug 16 06:15:38 PM PDT 24 30696763091 ps
T63 /workspace/coverage/default/9.sram_ctrl_max_throughput.4265935964 Aug 16 05:57:21 PM PDT 24 Aug 16 05:57:31 PM PDT 24 1372610045 ps
T22 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1337290017 Aug 16 05:58:04 PM PDT 24 Aug 16 05:58:14 PM PDT 24 1363209244 ps
T57 /workspace/coverage/default/3.sram_ctrl_smoke.3968989215 Aug 16 05:57:09 PM PDT 24 Aug 16 05:57:26 PM PDT 24 3124472837 ps
T30 /workspace/coverage/default/17.sram_ctrl_ram_cfg.620744127 Aug 16 05:58:01 PM PDT 24 Aug 16 05:58:05 PM PDT 24 734708627 ps
T64 /workspace/coverage/default/28.sram_ctrl_partial_access.1772467015 Aug 16 05:57:57 PM PDT 24 Aug 16 05:58:29 PM PDT 24 2978622226 ps
T80 /workspace/coverage/default/18.sram_ctrl_max_throughput.3199714494 Aug 16 05:57:53 PM PDT 24 Aug 16 05:59:08 PM PDT 24 2903843580 ps
T6 /workspace/coverage/default/17.sram_ctrl_lc_escalation.3342243594 Aug 16 05:57:35 PM PDT 24 Aug 16 05:58:23 PM PDT 24 13375572912 ps
T49 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.4041508785 Aug 16 05:58:03 PM PDT 24 Aug 16 06:00:57 PM PDT 24 21817357787 ps
T69 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2601561634 Aug 16 05:57:48 PM PDT 24 Aug 16 06:00:12 PM PDT 24 818790812 ps
T70 /workspace/coverage/default/1.sram_ctrl_bijection.1856480088 Aug 16 05:56:36 PM PDT 24 Aug 16 06:06:31 PM PDT 24 155153714851 ps
T71 /workspace/coverage/default/38.sram_ctrl_smoke.500619978 Aug 16 05:58:44 PM PDT 24 Aug 16 05:58:51 PM PDT 24 1582779713 ps
T72 /workspace/coverage/default/47.sram_ctrl_smoke.464099513 Aug 16 05:59:30 PM PDT 24 Aug 16 06:01:19 PM PDT 24 2627609004 ps
T73 /workspace/coverage/default/31.sram_ctrl_smoke.2651672764 Aug 16 05:58:13 PM PDT 24 Aug 16 05:58:33 PM PDT 24 1001959676 ps
T28 /workspace/coverage/default/9.sram_ctrl_executable.135693039 Aug 16 05:57:13 PM PDT 24 Aug 16 06:01:10 PM PDT 24 5936944228 ps
T50 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3563921573 Aug 16 05:58:55 PM PDT 24 Aug 16 06:00:12 PM PDT 24 5151338098 ps
T74 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1319562360 Aug 16 05:59:30 PM PDT 24 Aug 16 06:01:58 PM PDT 24 4931224670 ps
T75 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3083390909 Aug 16 05:58:24 PM PDT 24 Aug 16 06:06:10 PM PDT 24 25705828889 ps
T171 /workspace/coverage/default/23.sram_ctrl_bijection.4172587122 Aug 16 05:57:31 PM PDT 24 Aug 16 06:05:33 PM PDT 24 13781148864 ps
T7 /workspace/coverage/default/5.sram_ctrl_stress_all.1436507711 Aug 16 05:56:52 PM PDT 24 Aug 16 06:45:35 PM PDT 24 26018097368 ps
T29 /workspace/coverage/default/8.sram_ctrl_regwen.1235119311 Aug 16 05:57:15 PM PDT 24 Aug 16 06:13:00 PM PDT 24 28302979303 ps
T124 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1297657373 Aug 16 05:58:00 PM PDT 24 Aug 16 06:03:20 PM PDT 24 5409650571 ps
T26 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4051137241 Aug 16 05:58:15 PM PDT 24 Aug 16 05:58:29 PM PDT 24 515029849 ps
T27 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2443561907 Aug 16 05:59:20 PM PDT 24 Aug 16 05:59:27 PM PDT 24 755521457 ps
T31 /workspace/coverage/default/21.sram_ctrl_ram_cfg.3926436362 Aug 16 05:57:30 PM PDT 24 Aug 16 05:57:33 PM PDT 24 693721167 ps
T8 /workspace/coverage/default/4.sram_ctrl_lc_escalation.1987085478 Aug 16 05:56:42 PM PDT 24 Aug 16 05:58:28 PM PDT 24 54181585498 ps
T46 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2657235653 Aug 16 05:57:08 PM PDT 24 Aug 16 06:16:08 PM PDT 24 179531531758 ps
T174 /workspace/coverage/default/25.sram_ctrl_bijection.1659732685 Aug 16 05:58:01 PM PDT 24 Aug 16 06:09:20 PM PDT 24 41675406874 ps
T175 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.28837575 Aug 16 05:58:04 PM PDT 24 Aug 16 05:58:13 PM PDT 24 702284803 ps
T32 /workspace/coverage/default/1.sram_ctrl_ram_cfg.21672027 Aug 16 05:56:33 PM PDT 24 Aug 16 05:56:38 PM PDT 24 4187882562 ps
T79 /workspace/coverage/default/23.sram_ctrl_regwen.1418167381 Aug 16 05:58:00 PM PDT 24 Aug 16 06:06:11 PM PDT 24 17481328438 ps
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T177 /workspace/coverage/default/34.sram_ctrl_partial_access.662293406 Aug 16 05:58:09 PM PDT 24 Aug 16 05:58:39 PM PDT 24 821881216 ps
T178 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2190485984 Aug 16 05:58:02 PM PDT 24 Aug 16 05:58:05 PM PDT 24 368947177 ps
T179 /workspace/coverage/default/24.sram_ctrl_max_throughput.2355697298 Aug 16 05:57:37 PM PDT 24 Aug 16 05:57:45 PM PDT 24 6095833214 ps
T47 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3353979775 Aug 16 05:57:43 PM PDT 24 Aug 16 06:08:52 PM PDT 24 8981596224 ps
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T180 /workspace/coverage/default/15.sram_ctrl_smoke.3765620252 Aug 16 05:57:35 PM PDT 24 Aug 16 05:59:49 PM PDT 24 4329252858 ps
T181 /workspace/coverage/default/14.sram_ctrl_multiple_keys.3785538792 Aug 16 05:57:08 PM PDT 24 Aug 16 06:14:05 PM PDT 24 27614605606 ps
T172 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.922082650 Aug 16 05:58:12 PM PDT 24 Aug 16 05:58:25 PM PDT 24 727207818 ps
T19 /workspace/coverage/default/36.sram_ctrl_regwen.1984501544 Aug 16 05:58:47 PM PDT 24 Aug 16 06:14:00 PM PDT 24 11160272412 ps
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T15 /workspace/coverage/default/21.sram_ctrl_alert_test.182566514 Aug 16 05:57:28 PM PDT 24 Aug 16 05:57:29 PM PDT 24 41728533 ps
T58 /workspace/coverage/default/8.sram_ctrl_mem_walk.1150560494 Aug 16 05:57:31 PM PDT 24 Aug 16 06:02:26 PM PDT 24 5256850592 ps
T53 /workspace/coverage/default/44.sram_ctrl_mem_walk.1569270511 Aug 16 05:59:10 PM PDT 24 Aug 16 06:01:49 PM PDT 24 15064842989 ps
T182 /workspace/coverage/default/42.sram_ctrl_smoke.2246092967 Aug 16 05:59:02 PM PDT 24 Aug 16 05:59:19 PM PDT 24 1205372664 ps
T105 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2881791743 Aug 16 05:57:31 PM PDT 24 Aug 16 06:09:12 PM PDT 24 16469500212 ps
T20 /workspace/coverage/default/30.sram_ctrl_regwen.568874476 Aug 16 05:57:56 PM PDT 24 Aug 16 06:11:06 PM PDT 24 45331158060 ps
T183 /workspace/coverage/default/11.sram_ctrl_max_throughput.2781724008 Aug 16 05:57:14 PM PDT 24 Aug 16 05:57:45 PM PDT 24 1223345132 ps
T106 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.3519901981 Aug 16 05:57:49 PM PDT 24 Aug 16 06:00:33 PM PDT 24 4568109811 ps
T107 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2519962640 Aug 16 05:56:37 PM PDT 24 Aug 16 06:07:59 PM PDT 24 43533950945 ps
T158 /workspace/coverage/default/3.sram_ctrl_executable.1804924335 Aug 16 05:56:39 PM PDT 24 Aug 16 06:13:18 PM PDT 24 45325773588 ps
T59 /workspace/coverage/default/23.sram_ctrl_mem_walk.1686515071 Aug 16 05:57:29 PM PDT 24 Aug 16 06:00:07 PM PDT 24 7211177362 ps
T21 /workspace/coverage/default/32.sram_ctrl_regwen.1430087185 Aug 16 05:58:11 PM PDT 24 Aug 16 06:18:41 PM PDT 24 17650358443 ps
T90 /workspace/coverage/default/36.sram_ctrl_lc_escalation.547375843 Aug 16 05:58:45 PM PDT 24 Aug 16 05:59:11 PM PDT 24 12683404817 ps
T162 /workspace/coverage/default/42.sram_ctrl_regwen.834844941 Aug 16 05:59:00 PM PDT 24 Aug 16 06:22:40 PM PDT 24 4609609325 ps
T157 /workspace/coverage/default/6.sram_ctrl_stress_all.2809040365 Aug 16 05:56:47 PM PDT 24 Aug 16 06:38:57 PM PDT 24 277476287912 ps
T184 /workspace/coverage/default/30.sram_ctrl_smoke.2710148649 Aug 16 05:57:53 PM PDT 24 Aug 16 05:59:04 PM PDT 24 863522228 ps
T185 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2487390807 Aug 16 05:58:47 PM PDT 24 Aug 16 06:19:59 PM PDT 24 18928167339 ps
T60 /workspace/coverage/default/38.sram_ctrl_mem_walk.427181388 Aug 16 05:58:48 PM PDT 24 Aug 16 06:01:24 PM PDT 24 10962065105 ps
T186 /workspace/coverage/default/0.sram_ctrl_bijection.2226977587 Aug 16 05:56:30 PM PDT 24 Aug 16 06:37:29 PM PDT 24 132647026491 ps
T166 /workspace/coverage/default/14.sram_ctrl_regwen.541243400 Aug 16 05:57:46 PM PDT 24 Aug 16 06:07:48 PM PDT 24 8495004956 ps
T126 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3771348599 Aug 16 05:58:44 PM PDT 24 Aug 16 06:03:14 PM PDT 24 58265565240 ps
T14 /workspace/coverage/default/40.sram_ctrl_alert_test.4263806720 Aug 16 05:59:04 PM PDT 24 Aug 16 05:59:05 PM PDT 24 11707583 ps
T187 /workspace/coverage/default/42.sram_ctrl_ram_cfg.596126830 Aug 16 05:59:03 PM PDT 24 Aug 16 05:59:07 PM PDT 24 363155440 ps
T144 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3245064082 Aug 16 05:59:15 PM PDT 24 Aug 16 06:00:33 PM PDT 24 23181716405 ps
T127 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3314480820 Aug 16 05:58:04 PM PDT 24 Aug 16 06:01:04 PM PDT 24 21112992476 ps
T128 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.908676497 Aug 16 05:56:46 PM PDT 24 Aug 16 06:01:50 PM PDT 24 3222874707 ps
T188 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1089408443 Aug 16 05:58:00 PM PDT 24 Aug 16 05:58:12 PM PDT 24 1632470691 ps
T173 /workspace/coverage/default/34.sram_ctrl_max_throughput.3330866701 Aug 16 05:58:12 PM PDT 24 Aug 16 05:59:01 PM PDT 24 1477308783 ps
T108 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.7368249 Aug 16 05:58:03 PM PDT 24 Aug 16 06:04:51 PM PDT 24 29006456002 ps
T189 /workspace/coverage/default/0.sram_ctrl_ram_cfg.4193822097 Aug 16 05:56:53 PM PDT 24 Aug 16 05:56:57 PM PDT 24 722950458 ps
T61 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1495016052 Aug 16 05:57:11 PM PDT 24 Aug 16 06:00:58 PM PDT 24 3255537687 ps
T62 /workspace/coverage/default/10.sram_ctrl_mem_walk.1125609872 Aug 16 05:56:57 PM PDT 24 Aug 16 05:59:28 PM PDT 24 29216697584 ps
T52 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3812108977 Aug 16 05:58:03 PM PDT 24 Aug 16 05:59:32 PM PDT 24 10924491483 ps
T190 /workspace/coverage/default/27.sram_ctrl_max_throughput.1832921759 Aug 16 05:57:45 PM PDT 24 Aug 16 05:58:11 PM PDT 24 709927436 ps
T119 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.233147017 Aug 16 05:57:21 PM PDT 24 Aug 16 06:12:08 PM PDT 24 32323339627 ps
T191 /workspace/coverage/default/29.sram_ctrl_ram_cfg.2215517341 Aug 16 05:58:05 PM PDT 24 Aug 16 05:58:09 PM PDT 24 3340395964 ps
T192 /workspace/coverage/default/12.sram_ctrl_regwen.3531992791 Aug 16 05:57:22 PM PDT 24 Aug 16 06:08:26 PM PDT 24 14012593926 ps
T193 /workspace/coverage/default/20.sram_ctrl_multiple_keys.362739915 Aug 16 05:57:51 PM PDT 24 Aug 16 06:10:58 PM PDT 24 20100357501 ps
T170 /workspace/coverage/default/25.sram_ctrl_multiple_keys.693958548 Aug 16 05:58:02 PM PDT 24 Aug 16 06:26:57 PM PDT 24 77910516345 ps
T194 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3344124881 Aug 16 05:56:44 PM PDT 24 Aug 16 06:06:32 PM PDT 24 6233790329 ps
T195 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.683416678 Aug 16 05:58:23 PM PDT 24 Aug 16 06:02:07 PM PDT 24 24366794172 ps
T196 /workspace/coverage/default/6.sram_ctrl_bijection.2918151447 Aug 16 05:57:23 PM PDT 24 Aug 16 06:32:01 PM PDT 24 60826199213 ps
T197 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2276338432 Aug 16 05:59:14 PM PDT 24 Aug 16 06:04:43 PM PDT 24 18984641690 ps
T161 /workspace/coverage/default/38.sram_ctrl_stress_all.2181630654 Aug 16 05:58:57 PM PDT 24 Aug 16 06:12:18 PM PDT 24 50135299052 ps
T145 /workspace/coverage/default/32.sram_ctrl_stress_all.1870555289 Aug 16 05:58:12 PM PDT 24 Aug 16 06:55:05 PM PDT 24 279239489087 ps
T165 /workspace/coverage/default/20.sram_ctrl_stress_all.2444507951 Aug 16 05:57:21 PM PDT 24 Aug 16 06:58:43 PM PDT 24 140423675472 ps
T198 /workspace/coverage/default/22.sram_ctrl_multiple_keys.789215121 Aug 16 05:57:59 PM PDT 24 Aug 16 06:28:00 PM PDT 24 89892856000 ps
T163 /workspace/coverage/default/27.sram_ctrl_stress_all.3621367966 Aug 16 05:58:03 PM PDT 24 Aug 16 07:08:39 PM PDT 24 261943782033 ps
T199 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3006370392 Aug 16 05:57:30 PM PDT 24 Aug 16 05:59:19 PM PDT 24 1001488038 ps
T164 /workspace/coverage/default/45.sram_ctrl_stress_all.4265982505 Aug 16 05:59:19 PM PDT 24 Aug 16 07:13:54 PM PDT 24 187040931705 ps
T200 /workspace/coverage/default/13.sram_ctrl_executable.1552551135 Aug 16 05:57:39 PM PDT 24 Aug 16 06:09:47 PM PDT 24 11075850940 ps
T201 /workspace/coverage/default/21.sram_ctrl_partial_access.296224809 Aug 16 05:57:28 PM PDT 24 Aug 16 05:57:38 PM PDT 24 2591201340 ps
T202 /workspace/coverage/default/8.sram_ctrl_ram_cfg.740205941 Aug 16 05:56:49 PM PDT 24 Aug 16 05:56:53 PM PDT 24 680542120 ps
T203 /workspace/coverage/default/47.sram_ctrl_bijection.4145520792 Aug 16 05:59:29 PM PDT 24 Aug 16 06:08:34 PM PDT 24 24253052703 ps
T159 /workspace/coverage/default/4.sram_ctrl_stress_all.1695121367 Aug 16 05:56:43 PM PDT 24 Aug 16 07:51:19 PM PDT 24 439203132247 ps
T204 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1585623926 Aug 16 05:57:11 PM PDT 24 Aug 16 06:04:58 PM PDT 24 36087664338 ps
T205 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1630200285 Aug 16 05:57:59 PM PDT 24 Aug 16 06:03:29 PM PDT 24 5053188362 ps
T206 /workspace/coverage/default/37.sram_ctrl_bijection.3919649288 Aug 16 05:58:38 PM PDT 24 Aug 16 06:12:21 PM PDT 24 33862606737 ps
T84 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1880661765 Aug 16 05:58:12 PM PDT 24 Aug 16 05:58:36 PM PDT 24 706512913 ps
T65 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4135899579 Aug 16 05:56:33 PM PDT 24 Aug 16 05:59:05 PM PDT 24 5310960182 ps
T207 /workspace/coverage/default/7.sram_ctrl_multiple_keys.1936921201 Aug 16 05:57:08 PM PDT 24 Aug 16 06:19:31 PM PDT 24 77074705716 ps
T168 /workspace/coverage/default/5.sram_ctrl_multiple_keys.2520576630 Aug 16 05:57:00 PM PDT 24 Aug 16 06:13:56 PM PDT 24 45284601785 ps
T208 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2596785924 Aug 16 05:58:10 PM PDT 24 Aug 16 05:58:14 PM PDT 24 360225408 ps
T167 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.744594652 Aug 16 05:58:00 PM PDT 24 Aug 16 06:02:10 PM PDT 24 11698441370 ps
T209 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3939149157 Aug 16 05:58:57 PM PDT 24 Aug 16 06:00:06 PM PDT 24 2417064598 ps
T210 /workspace/coverage/default/35.sram_ctrl_executable.2823956869 Aug 16 05:58:46 PM PDT 24 Aug 16 06:08:49 PM PDT 24 29817700386 ps
T211 /workspace/coverage/default/13.sram_ctrl_stress_all.3374658856 Aug 16 05:57:08 PM PDT 24 Aug 16 08:02:37 PM PDT 24 272806336848 ps
T212 /workspace/coverage/default/17.sram_ctrl_mem_walk.3988510262 Aug 16 05:57:40 PM PDT 24 Aug 16 06:03:09 PM PDT 24 51223073378 ps
T213 /workspace/coverage/default/4.sram_ctrl_bijection.3954719333 Aug 16 05:56:37 PM PDT 24 Aug 16 06:14:42 PM PDT 24 129691334610 ps
T214 /workspace/coverage/default/19.sram_ctrl_executable.1424038772 Aug 16 05:57:55 PM PDT 24 Aug 16 05:59:51 PM PDT 24 6779457845 ps
T215 /workspace/coverage/default/34.sram_ctrl_multiple_keys.2214708579 Aug 16 05:58:37 PM PDT 24 Aug 16 06:16:01 PM PDT 24 13693389876 ps
T216 /workspace/coverage/default/24.sram_ctrl_smoke.980177304 Aug 16 05:57:58 PM PDT 24 Aug 16 05:58:11 PM PDT 24 1925368168 ps
T217 /workspace/coverage/default/11.sram_ctrl_stress_all.4058927914 Aug 16 05:57:12 PM PDT 24 Aug 16 06:51:33 PM PDT 24 122499942005 ps
T169 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3486995242 Aug 16 05:58:40 PM PDT 24 Aug 16 06:03:01 PM PDT 24 101116102750 ps
T218 /workspace/coverage/default/43.sram_ctrl_mem_walk.3619592505 Aug 16 05:59:14 PM PDT 24 Aug 16 06:01:23 PM PDT 24 21919686947 ps
T219 /workspace/coverage/default/33.sram_ctrl_max_throughput.3945796927 Aug 16 05:58:10 PM PDT 24 Aug 16 05:59:31 PM PDT 24 3100442092 ps
T220 /workspace/coverage/default/44.sram_ctrl_max_throughput.4173466245 Aug 16 05:59:14 PM PDT 24 Aug 16 05:59:28 PM PDT 24 1409484611 ps
T221 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3743381980 Aug 16 05:57:29 PM PDT 24 Aug 16 06:12:32 PM PDT 24 10666925263 ps
T222 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3188257244 Aug 16 05:57:22 PM PDT 24 Aug 16 06:02:34 PM PDT 24 33272591355 ps
T223 /workspace/coverage/default/43.sram_ctrl_ram_cfg.1423700423 Aug 16 05:59:00 PM PDT 24 Aug 16 05:59:04 PM PDT 24 1766643136 ps
T54 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2954496736 Aug 16 05:57:51 PM PDT 24 Aug 16 05:59:32 PM PDT 24 33408593153 ps
T224 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1823730857 Aug 16 05:59:27 PM PDT 24 Aug 16 06:08:14 PM PDT 24 91515115918 ps
T225 /workspace/coverage/default/44.sram_ctrl_ram_cfg.554573757 Aug 16 05:59:11 PM PDT 24 Aug 16 05:59:15 PM PDT 24 1411427279 ps
T226 /workspace/coverage/default/9.sram_ctrl_mem_walk.2390900592 Aug 16 05:57:25 PM PDT 24 Aug 16 06:00:05 PM PDT 24 69434187023 ps
T160 /workspace/coverage/default/33.sram_ctrl_regwen.2443170486 Aug 16 05:58:13 PM PDT 24 Aug 16 06:11:38 PM PDT 24 3038619782 ps
T227 /workspace/coverage/default/42.sram_ctrl_partial_access.2661639274 Aug 16 05:59:12 PM PDT 24 Aug 16 05:59:16 PM PDT 24 1649349699 ps
T228 /workspace/coverage/default/2.sram_ctrl_executable.2529153717 Aug 16 05:57:06 PM PDT 24 Aug 16 06:08:58 PM PDT 24 3760923382 ps
T229 /workspace/coverage/default/28.sram_ctrl_regwen.3269052357 Aug 16 05:58:02 PM PDT 24 Aug 16 06:11:18 PM PDT 24 4083631380 ps
T230 /workspace/coverage/default/36.sram_ctrl_multiple_keys.299874530 Aug 16 05:58:31 PM PDT 24 Aug 16 06:07:20 PM PDT 24 12889224407 ps
T55 /workspace/coverage/default/1.sram_ctrl_mem_walk.2844436418 Aug 16 05:57:10 PM PDT 24 Aug 16 06:03:01 PM PDT 24 20697244272 ps
T231 /workspace/coverage/default/18.sram_ctrl_multiple_keys.4271424131 Aug 16 05:57:54 PM PDT 24 Aug 16 06:07:33 PM PDT 24 17570777879 ps
T232 /workspace/coverage/default/3.sram_ctrl_partial_access.2992476105 Aug 16 05:56:40 PM PDT 24 Aug 16 05:57:04 PM PDT 24 3958128666 ps
T233 /workspace/coverage/default/35.sram_ctrl_mem_walk.1579709728 Aug 16 05:58:29 PM PDT 24 Aug 16 06:00:37 PM PDT 24 2042482588 ps
T234 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2172454554 Aug 16 05:56:50 PM PDT 24 Aug 16 06:06:03 PM PDT 24 45947805962 ps
T235 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3086353697 Aug 16 05:59:12 PM PDT 24 Aug 16 06:00:23 PM PDT 24 763834082 ps
T109 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2149086961 Aug 16 05:57:59 PM PDT 24 Aug 16 05:59:15 PM PDT 24 2753306474 ps
T236 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3391939850 Aug 16 05:57:38 PM PDT 24 Aug 16 05:57:42 PM PDT 24 1341282543 ps
T237 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2385648966 Aug 16 05:58:11 PM PDT 24 Aug 16 06:04:13 PM PDT 24 55420045593 ps
T238 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1661174892 Aug 16 05:58:30 PM PDT 24 Aug 16 06:05:07 PM PDT 24 18134528717 ps
T239 /workspace/coverage/default/37.sram_ctrl_stress_all.1743395458 Aug 16 05:58:38 PM PDT 24 Aug 16 07:58:16 PM PDT 24 77537414837 ps
T240 /workspace/coverage/default/9.sram_ctrl_stress_all.57406930 Aug 16 05:56:56 PM PDT 24 Aug 16 06:27:00 PM PDT 24 78923906998 ps
T241 /workspace/coverage/default/16.sram_ctrl_multiple_keys.2341956057 Aug 16 05:58:00 PM PDT 24 Aug 16 06:11:47 PM PDT 24 28421387452 ps
T242 /workspace/coverage/default/19.sram_ctrl_bijection.2554325026 Aug 16 05:57:45 PM PDT 24 Aug 16 06:42:06 PM PDT 24 147942476957 ps
T243 /workspace/coverage/default/18.sram_ctrl_alert_test.3170857107 Aug 16 05:57:58 PM PDT 24 Aug 16 05:57:59 PM PDT 24 26919618 ps
T244 /workspace/coverage/default/11.sram_ctrl_mem_walk.2527942266 Aug 16 05:57:13 PM PDT 24 Aug 16 06:02:14 PM PDT 24 10940903239 ps
T245 /workspace/coverage/default/27.sram_ctrl_lc_escalation.332313666 Aug 16 05:57:43 PM PDT 24 Aug 16 05:58:49 PM PDT 24 27885805387 ps
T246 /workspace/coverage/default/25.sram_ctrl_lc_escalation.3283401706 Aug 16 05:57:58 PM PDT 24 Aug 16 05:58:21 PM PDT 24 3756993048 ps
T129 /workspace/coverage/default/12.sram_ctrl_alert_test.989958599 Aug 16 05:57:13 PM PDT 24 Aug 16 05:57:14 PM PDT 24 19890918 ps
T85 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1607694342 Aug 16 05:59:39 PM PDT 24 Aug 16 05:59:50 PM PDT 24 984803210 ps
T130 /workspace/coverage/default/38.sram_ctrl_max_throughput.4080180174 Aug 16 05:58:47 PM PDT 24 Aug 16 06:00:50 PM PDT 24 2996707434 ps
T131 /workspace/coverage/default/19.sram_ctrl_alert_test.1444178880 Aug 16 05:57:21 PM PDT 24 Aug 16 05:57:22 PM PDT 24 10679848 ps
T132 /workspace/coverage/default/19.sram_ctrl_ram_cfg.881578604 Aug 16 05:57:56 PM PDT 24 Aug 16 05:57:59 PM PDT 24 1348541062 ps
T133 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.93617403 Aug 16 05:58:52 PM PDT 24 Aug 16 06:06:33 PM PDT 24 71775645982 ps
T134 /workspace/coverage/default/2.sram_ctrl_alert_test.3408360621 Aug 16 05:56:41 PM PDT 24 Aug 16 05:56:42 PM PDT 24 21603786 ps
T56 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.2851961489 Aug 16 05:57:31 PM PDT 24 Aug 16 06:00:28 PM PDT 24 34967307444 ps
T135 /workspace/coverage/default/25.sram_ctrl_alert_test.4058399633 Aug 16 05:58:01 PM PDT 24 Aug 16 05:58:02 PM PDT 24 44019946 ps
T136 /workspace/coverage/default/40.sram_ctrl_ram_cfg.1323158984 Aug 16 05:59:09 PM PDT 24 Aug 16 05:59:12 PM PDT 24 1873055175 ps
T247 /workspace/coverage/default/42.sram_ctrl_executable.3779133063 Aug 16 05:59:16 PM PDT 24 Aug 16 06:22:35 PM PDT 24 90475657872 ps
T248 /workspace/coverage/default/23.sram_ctrl_lc_escalation.309523992 Aug 16 05:57:25 PM PDT 24 Aug 16 05:58:25 PM PDT 24 10927985536 ps
T249 /workspace/coverage/default/7.sram_ctrl_smoke.1861196826 Aug 16 05:57:01 PM PDT 24 Aug 16 05:57:52 PM PDT 24 2927889142 ps
T250 /workspace/coverage/default/9.sram_ctrl_regwen.166209171 Aug 16 05:57:15 PM PDT 24 Aug 16 06:07:44 PM PDT 24 38990079719 ps
T251 /workspace/coverage/default/10.sram_ctrl_stress_all.1768580199 Aug 16 05:57:19 PM PDT 24 Aug 16 07:52:07 PM PDT 24 269288595882 ps
T252 /workspace/coverage/default/16.sram_ctrl_alert_test.4104590685 Aug 16 05:57:12 PM PDT 24 Aug 16 05:57:13 PM PDT 24 16497592 ps
T253 /workspace/coverage/default/35.sram_ctrl_max_throughput.2700791312 Aug 16 05:58:49 PM PDT 24 Aug 16 05:59:06 PM PDT 24 13784793739 ps
T254 /workspace/coverage/default/12.sram_ctrl_multiple_keys.2854449752 Aug 16 05:56:59 PM PDT 24 Aug 16 06:21:26 PM PDT 24 39478685872 ps
T255 /workspace/coverage/default/7.sram_ctrl_executable.3905728639 Aug 16 05:57:15 PM PDT 24 Aug 16 06:25:31 PM PDT 24 19987099048 ps
T256 /workspace/coverage/default/32.sram_ctrl_max_throughput.822396263 Aug 16 05:58:14 PM PDT 24 Aug 16 05:58:25 PM PDT 24 687602582 ps
T257 /workspace/coverage/default/4.sram_ctrl_partial_access.1571580337 Aug 16 05:56:44 PM PDT 24 Aug 16 05:57:22 PM PDT 24 1740331031 ps
T258 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.112813756 Aug 16 05:59:31 PM PDT 24 Aug 16 06:04:22 PM PDT 24 36140621920 ps
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T303 /workspace/coverage/default/3.sram_ctrl_bijection.2864542759 Aug 16 05:56:38 PM PDT 24 Aug 16 06:48:52 PM PDT 24 749488563784 ps
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