Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	145747785	1			T2	204337		T3	692		T4	64444
triple_byte_access	2831354	1			T2	4141		T3	13		T4	1294
halfword_access	4344468	1			T2	6161		T3	23		T4	2003
byte_access	6076040	1			T2	8161		T3	23		T4	2524
zero_access	1836836	1			T2	2039		T3	12		T4	659

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80198846

1

T2

112736

T3

385

T4

35344

auto[1]

80637637

1

T2

112103

T3

378

T4

35580

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72520493	1			T2	102490		T3	351		T4	32167
auto[0]	triple_byte_access	1350473	1			T2	2110		T3	5		T4	643
auto[0]	halfword_access	2122062	1			T2	3041		T3	11		T4	970
auto[0]	byte_access	3109763	1			T2	4074		T3	11		T4	1242
auto[0]	zero_access	1096055	1			T2	1021		T3	7		T4	322
auto[1]	word_access	73227292	1			T2	101847		T3	341		T4	32277
auto[1]	triple_byte_access	1480881	1			T2	2031		T3	8		T4	651
auto[1]	halfword_access	2222406	1			T2	3120		T3	12		T4	1033
auto[1]	byte_access	2966277	1			T2	4087		T3	12		T4	1282
auto[1]	zero_access	740781	1			T2	1018		T3	5		T4	337