Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16209809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

154072140

1

T1

77850

T2

1264

T3

170355

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	83846353	1			T1	42829		T2	704		T3	93539
values[0x0]	41601806	1			T1	20579		T2	356		T3	45113
values[0x1]	44833790	1			T1	22227		T2	323		T3	48714

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8234932	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162047017

1

T1

81801

T2

1316

T3

178793

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	560921	1			T1	377		T2	2		T3	714
valid_sources[0x01]	577111	1			T1	360		T2	14		T3	745
valid_sources[0x02]	607804	1			T1	313		T2	6		T3	718
valid_sources[0x03]	549529	1			T1	357		T2	14		T3	795
valid_sources[0x04]	541883	1			T1	324		T2	6		T3	757
valid_sources[0x05]	563846	1			T1	333		T2	5		T3	727
valid_sources[0x06]	541299	1			T1	316		T2	7		T3	711
valid_sources[0x07]	1272318	1			T1	339		T2	2		T3	699
valid_sources[0x08]	542862	1			T1	346		T2	4		T3	699
valid_sources[0x09]	560739	1			T1	313		T2	4		T3	701
valid_sources[0x0a]	862398	1			T1	317		T2	7		T3	731
valid_sources[0x0b]	563344	1			T1	371		T2	7		T3	737
valid_sources[0x0c]	536975	1			T1	325		T2	7		T3	684
valid_sources[0x0d]	590743	1			T1	380		T2	2		T3	695
valid_sources[0x0e]	594098	1			T1	324		T2	4		T3	728
valid_sources[0x0f]	575972	1			T1	360		T2	3		T3	700
valid_sources[0x10]	570541	1			T1	297		T2	10		T3	790
valid_sources[0x11]	592768	1			T1	320		T2	6		T3	780
valid_sources[0x12]	3168704	1			T1	358		T2	9		T3	758
valid_sources[0x13]	569327	1			T1	353		T2	4		T3	713
valid_sources[0x14]	561585	1			T1	351		T2	9		T3	730
valid_sources[0x15]	656462	1			T1	320		T2	2		T3	687
valid_sources[0x16]	528675	1			T1	325		T2	6		T3	747
valid_sources[0x17]	606753	1			T1	330		T2	6		T3	742
valid_sources[0x18]	1771761	1			T1	359		T2	9		T3	720
valid_sources[0x19]	571784	1			T1	344		T2	6		T3	771
valid_sources[0x1a]	548652	1			T1	305		T2	4		T3	741
valid_sources[0x1b]	537999	1			T1	368		T2	4		T3	654
valid_sources[0x1c]	607518	1			T1	362		T2	7		T3	725
valid_sources[0x1d]	542658	1			T1	315		T2	3		T3	727
valid_sources[0x1e]	571206	1			T1	329		T2	3		T3	757
valid_sources[0x1f]	547127	1			T1	337		T2	6		T3	647
valid_sources[0x20]	546105	1			T1	339		T2	7		T3	760
valid_sources[0x21]	604257	1			T1	304		T2	11		T3	672
valid_sources[0x22]	574200	1			T1	343		T2	9		T3	694
valid_sources[0x23]	1616865	1			T1	317		T2	6		T3	688
valid_sources[0x24]	620279	1			T1	290		T2	7		T3	711
valid_sources[0x25]	569637	1			T1	332		T2	9		T3	746
valid_sources[0x26]	604841	1			T1	345		T2	4		T3	705
valid_sources[0x27]	536618	1			T1	303		T2	6		T3	776
valid_sources[0x28]	545343	1			T1	347		T2	3		T3	722
valid_sources[0x29]	600879	1			T1	326		T2	8		T3	780
valid_sources[0x2a]	781090	1			T1	341		T2	6		T3	672
valid_sources[0x2b]	571344	1			T1	316		T2	7		T3	748
valid_sources[0x2c]	589191	1			T1	332		T2	9		T3	747
valid_sources[0x2d]	599202	1			T1	344		T2	10		T3	726
valid_sources[0x2e]	527840	1			T1	343		T2	7		T3	797
valid_sources[0x2f]	569912	1			T1	348		T2	3		T3	708
valid_sources[0x30]	551151	1			T1	333		T2	4		T3	679
valid_sources[0x31]	551024	1			T1	337		T2	4		T3	767
valid_sources[0x32]	577344	1			T1	347		T2	4		T3	720
valid_sources[0x33]	2137265	1			T1	323		T2	10		T3	709
valid_sources[0x34]	540826	1			T1	317		T2	6		T3	735
valid_sources[0x35]	588431	1			T1	361		T2	9		T3	704
valid_sources[0x36]	556708	1			T1	330		T2	7		T3	732
valid_sources[0x37]	584555	1			T1	346		T2	5		T3	704
valid_sources[0x38]	583773	1			T1	336		T2	2		T3	772
valid_sources[0x39]	714367	1			T1	385		T2	6		T3	709
valid_sources[0x3a]	591077	1			T1	352		T2	7		T3	743
valid_sources[0x3b]	646422	1			T1	357		T2	11		T3	711
valid_sources[0x3c]	595227	1			T1	324		T2	7		T3	775
valid_sources[0x3d]	555855	1			T1	336		T2	4		T3	723
valid_sources[0x3e]	532119	1			T1	311		T2	12		T3	761
valid_sources[0x3f]	553746	1			T1	328		T2	4		T3	736
valid_sources[0x40]	746088	1			T1	338		T2	6		T3	791
valid_sources[0x41]	558564	1			T1	322		T2	2		T3	759
valid_sources[0x42]	1618042	1			T1	325		T2	8		T3	765
valid_sources[0x43]	557574	1			T1	345		T2	1		T3	725
valid_sources[0x44]	575136	1			T1	324		T2	6		T3	749
valid_sources[0x45]	588352	1			T1	323		T2	2		T3	756
valid_sources[0x46]	608572	1			T1	352		T2	8		T3	695
valid_sources[0x47]	543030	1			T1	347		T2	5		T3	736
valid_sources[0x48]	1552452	1			T1	329		T2	5		T3	743
valid_sources[0x49]	573807	1			T1	336		T2	5		T3	746
valid_sources[0x4a]	635120	1			T1	344		T2	8		T3	765
valid_sources[0x4b]	554604	1			T1	324		T2	6		T3	750
valid_sources[0x4c]	550905	1			T1	311		T2	11		T3	787
valid_sources[0x4d]	539063	1			T1	340		T2	3		T3	668
valid_sources[0x4e]	824520	1			T1	300		T2	4		T3	768
valid_sources[0x4f]	1123179	1			T1	332		T2	4		T3	783
valid_sources[0x50]	562516	1			T1	349		T2	4		T3	752
valid_sources[0x51]	559557	1			T1	294		T2	8		T3	786
valid_sources[0x52]	557086	1			T1	321		T2	4		T3	779
valid_sources[0x53]	565441	1			T1	342		T2	3		T3	737
valid_sources[0x54]	554849	1			T1	315		T2	6		T3	731
valid_sources[0x55]	554231	1			T1	348		T2	4		T3	703
valid_sources[0x56]	541447	1			T1	337		T2	8		T3	734
valid_sources[0x57]	608402	1			T1	310		T2	6		T3	701
valid_sources[0x58]	546247	1			T1	333		T2	8		T3	704
valid_sources[0x59]	528998	1			T1	346		T2	8		T3	734
valid_sources[0x5a]	553509	1			T1	382		T2	5		T3	731
valid_sources[0x5b]	1320798	1			T1	362		T2	11		T3	725
valid_sources[0x5c]	590825	1			T1	330		T2	5		T3	701
valid_sources[0x5d]	587020	1			T1	316		T2	7		T3	708
valid_sources[0x5e]	599225	1			T1	352		T2	4		T3	698
valid_sources[0x5f]	558898	1			T1	316		T2	5		T3	646
valid_sources[0x60]	562806	1			T1	314		T2	5		T3	799
valid_sources[0x61]	577700	1			T1	332		T2	5		T3	727
valid_sources[0x62]	548319	1			T1	335		T2	3		T3	767
valid_sources[0x63]	533004	1			T1	327		T2	7		T3	746
valid_sources[0x64]	831797	1			T1	332		T2	6		T3	797
valid_sources[0x65]	575747	1			T1	359		T2	4		T3	669
valid_sources[0x66]	558705	1			T1	317		T2	7		T3	740
valid_sources[0x67]	646988	1			T1	351		T2	6		T3	729
valid_sources[0x68]	577239	1			T1	347		T2	8		T3	717
valid_sources[0x69]	541073	1			T1	363		T2	5		T3	735
valid_sources[0x6a]	534214	1			T1	346		T2	2		T3	721
valid_sources[0x6b]	1780244	1			T1	305		T3	801		T4	16
valid_sources[0x6c]	557484	1			T1	349		T2	9		T3	758
valid_sources[0x6d]	573665	1			T1	329		T2	3		T3	765
valid_sources[0x6e]	657216	1			T1	316		T2	3		T3	731
valid_sources[0x6f]	695775	1			T1	335		T2	4		T3	709
valid_sources[0x70]	541293	1			T1	378		T2	6		T3	801
valid_sources[0x71]	549213	1			T1	322		T2	5		T3	761
valid_sources[0x72]	553150	1			T1	332		T2	2		T3	739
valid_sources[0x73]	557035	1			T1	324		T2	3		T3	779
valid_sources[0x74]	532658	1			T1	307		T2	2		T3	746
valid_sources[0x75]	759617	1			T1	372		T2	6		T3	786
valid_sources[0x76]	568245	1			T1	277		T2	3		T3	739
valid_sources[0x77]	554824	1			T1	328		T2	12		T3	683
valid_sources[0x78]	661750	1			T1	351		T2	1		T3	723
valid_sources[0x79]	567973	1			T1	340		T2	2		T3	692
valid_sources[0x7a]	533278	1			T1	342		T2	4		T3	741
valid_sources[0x7b]	593625	1			T1	356		T2	1		T3	699
valid_sources[0x7c]	554969	1			T1	370		T2	4		T3	709
valid_sources[0x7d]	588483	1			T1	338		T2	1		T3	698
valid_sources[0x7e]	806227	1			T1	347		T2	7		T3	709
valid_sources[0x7f]	764457	1			T1	297		T2	8		T3	763
valid_sources[0x80]	572450	1			T1	310		T2	2		T3	706

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75702682

1

T1

38928

T2

641

T3

85142

values[0x0]

all_enables

biggest_size

39180874

1

T1

19411

T2

330

T3

42538

values[0x1]

all_enables

biggest_size

39188584

1

T1

19511

T2

293

T3

42675

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

146876

1

T1

2

T2

10

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52141	1			T2	14		T4	484		T9	3
values[0x0]	66386	1			T1	8		T2	8		T3	10
values[0x1]	71577	1			T1	8		T2	7		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156453

1

T1

3

T2

12

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	766	1			T4	12		T5	1		T34	2
valid_sources[0x01]	729	1			T4	6		T25	12		T46	5
valid_sources[0x02]	683	1			T4	7		T6	1		T40	2
valid_sources[0x03]	715	1			T4	9		T6	1		T41	3
valid_sources[0x04]	834	1			T4	5		T41	1		T56	5
valid_sources[0x05]	621	1			T4	1		T6	1		T18	1
valid_sources[0x06]	751	1			T4	4		T9	1		T42	1
valid_sources[0x07]	725	1			T4	10		T41	2		T42	1
valid_sources[0x08]	833	1			T4	3		T25	8		T46	6
valid_sources[0x09]	570	1			T4	3		T25	6		T46	10
valid_sources[0x0a]	754	1			T4	13		T20	1		T25	14
valid_sources[0x0b]	867	1			T4	7		T18	2		T41	2
valid_sources[0x0c]	631	1			T2	3		T4	10		T18	1
valid_sources[0x0d]	896	1			T4	5		T41	3		T24	5
valid_sources[0x0e]	654	1			T4	2		T103	1		T25	11
valid_sources[0x0f]	638	1			T4	2		T18	1		T26	1
valid_sources[0x10]	1035	1			T4	15		T23	1		T41	2
valid_sources[0x11]	1067	1			T4	5		T42	2		T24	2
valid_sources[0x12]	827	1			T4	9		T25	9		T46	9
valid_sources[0x13]	745	1			T4	3		T9	1		T6	1
valid_sources[0x14]	517	1			T4	8		T6	1		T41	3
valid_sources[0x15]	602	1			T4	12		T40	1		T56	1
valid_sources[0x16]	709	1			T2	1		T4	14		T6	1
valid_sources[0x17]	769	1			T2	3		T4	5		T25	16
valid_sources[0x18]	561	1			T4	1		T25	10		T46	13
valid_sources[0x19]	610	1			T1	1		T41	1		T34	1
valid_sources[0x1a]	810	1			T4	11		T26	5		T41	2
valid_sources[0x1b]	602	1			T4	11		T41	1		T42	1
valid_sources[0x1c]	639	1			T4	4		T41	1		T25	9
valid_sources[0x1d]	652	1			T4	1		T6	1		T41	3
valid_sources[0x1e]	864	1			T4	18		T40	1		T24	29
valid_sources[0x1f]	670	1			T3	3		T4	18		T41	2
valid_sources[0x20]	675	1			T4	1		T41	2		T56	2
valid_sources[0x21]	765	1			T4	7		T40	1		T18	2
valid_sources[0x22]	602	1			T4	5		T41	1		T56	1
valid_sources[0x23]	999	1			T4	7		T52	2		T42	2
valid_sources[0x24]	596	1			T4	2		T41	4		T25	2
valid_sources[0x25]	1049	1			T4	21		T6	2		T25	8
valid_sources[0x26]	658	1			T4	17		T56	2		T25	8
valid_sources[0x27]	675	1			T4	5		T9	1		T6	1
valid_sources[0x28]	698	1			T4	4		T25	6		T46	10
valid_sources[0x29]	624	1			T4	4		T18	1		T25	5
valid_sources[0x2a]	537	1			T40	1		T18	2		T41	1
valid_sources[0x2b]	742	1			T4	20		T56	1		T25	11
valid_sources[0x2c]	944	1			T4	12		T26	17		T24	1
valid_sources[0x2d]	829	1			T2	1		T4	6		T41	1
valid_sources[0x2e]	703	1			T4	9		T18	1		T19	1
valid_sources[0x2f]	661	1			T4	1		T42	1		T25	8
valid_sources[0x30]	645	1			T4	9		T41	3		T24	4
valid_sources[0x31]	901	1			T4	10		T5	1		T18	1
valid_sources[0x32]	789	1			T1	1		T4	1		T18	2
valid_sources[0x33]	589	1			T4	2		T42	4		T56	1
valid_sources[0x34]	750	1			T4	10		T8	2		T41	4
valid_sources[0x35]	869	1			T4	5		T18	1		T20	1
valid_sources[0x36]	762	1			T4	1		T6	1		T7	28
valid_sources[0x37]	646	1			T4	11		T5	1		T41	2
valid_sources[0x38]	580	1			T4	1		T41	1		T25	14
valid_sources[0x39]	753	1			T41	5		T25	5		T46	2
valid_sources[0x3a]	694	1			T4	9		T41	5		T34	2
valid_sources[0x3b]	538	1			T4	4		T56	2		T25	9
valid_sources[0x3c]	1381	1			T4	8		T18	1		T41	1
valid_sources[0x3d]	992	1			T4	9		T24	159		T25	12
valid_sources[0x3e]	694	1			T1	1		T4	11		T20	7
valid_sources[0x3f]	928	1			T4	3		T18	1		T41	1
valid_sources[0x40]	741	1			T3	2		T4	3		T56	2
valid_sources[0x41]	576	1			T4	7		T33	1		T25	10
valid_sources[0x42]	640	1			T4	9		T18	1		T41	2
valid_sources[0x43]	721	1			T4	18		T41	2		T55	3
valid_sources[0x44]	598	1			T4	8		T11	5		T41	1
valid_sources[0x45]	658	1			T4	1		T6	1		T41	2
valid_sources[0x46]	666	1			T4	1		T6	1		T41	1
valid_sources[0x47]	808	1			T4	2		T41	2		T34	1
valid_sources[0x48]	599	1			T4	2		T41	1		T20	16
valid_sources[0x49]	734	1			T4	2		T18	4		T41	2
valid_sources[0x4a]	825	1			T4	3		T6	1		T41	1
valid_sources[0x4b]	767	1			T4	1		T41	2		T25	8
valid_sources[0x4c]	1251	1			T103	1		T41	1		T20	8
valid_sources[0x4d]	876	1			T4	3		T19	9		T41	5
valid_sources[0x4e]	806	1			T4	31		T9	1		T18	2
valid_sources[0x4f]	779	1			T4	14		T41	4		T25	9
valid_sources[0x50]	899	1			T4	4		T41	2		T25	8
valid_sources[0x51]	1060	1			T4	8		T56	2		T25	11
valid_sources[0x52]	566	1			T4	6		T25	13		T46	13
valid_sources[0x53]	731	1			T2	1		T4	2		T41	1
valid_sources[0x54]	545	1			T4	2		T56	2		T33	1
valid_sources[0x55]	651	1			T4	2		T6	1		T25	6
valid_sources[0x56]	636	1			T4	1		T18	1		T24	4
valid_sources[0x57]	595	1			T4	23		T20	8		T56	1
valid_sources[0x58]	817	1			T4	11		T18	1		T56	1
valid_sources[0x59]	588	1			T4	7		T24	3		T25	9
valid_sources[0x5a]	668	1			T85	1		T41	1		T24	19
valid_sources[0x5b]	669	1			T4	2		T18	1		T41	3
valid_sources[0x5c]	714	1			T4	8		T12	3		T18	2
valid_sources[0x5d]	681	1			T4	12		T41	2		T56	2
valid_sources[0x5e]	1090	1			T4	4		T40	1		T41	1
valid_sources[0x5f]	619	1			T4	4		T6	1		T26	12
valid_sources[0x60]	768	1			T3	7		T4	2		T9	1
valid_sources[0x61]	663	1			T4	4		T18	2		T41	1
valid_sources[0x62]	553	1			T4	3		T5	1		T18	2
valid_sources[0x63]	691	1			T4	19		T26	3		T41	4
valid_sources[0x64]	627	1			T4	1		T25	10		T46	7
valid_sources[0x65]	851	1			T4	7		T18	2		T41	1
valid_sources[0x66]	691	1			T4	15		T18	2		T85	1
valid_sources[0x67]	769	1			T4	1		T19	1		T24	1
valid_sources[0x68]	621	1			T41	2		T56	4		T25	11
valid_sources[0x69]	836	1			T4	4		T18	1		T19	7
valid_sources[0x6a]	520	1			T4	5		T42	2		T25	11
valid_sources[0x6b]	1015	1			T4	4		T18	5		T41	2
valid_sources[0x6c]	1051	1			T1	1		T4	1		T6	1
valid_sources[0x6d]	638	1			T4	17		T40	2		T56	2
valid_sources[0x6e]	964	1			T4	11		T6	1		T19	3
valid_sources[0x6f]	809	1			T4	2		T41	2		T56	5
valid_sources[0x70]	941	1			T4	1		T6	1		T42	4
valid_sources[0x71]	628	1			T4	4		T5	1		T25	5
valid_sources[0x72]	823	1			T4	9		T6	1		T12	1
valid_sources[0x73]	1272	1			T4	3		T56	1		T25	12
valid_sources[0x74]	564	1			T2	1		T4	3		T41	2
valid_sources[0x75]	689	1			T4	1		T9	3		T42	2
valid_sources[0x76]	581	1			T4	6		T41	1		T42	3
valid_sources[0x77]	701	1			T4	7		T18	1		T41	1
valid_sources[0x78]	617	1			T4	16		T6	1		T18	2
valid_sources[0x79]	842	1			T4	15		T25	14		T46	8
valid_sources[0x7a]	606	1			T4	1		T41	1		T25	7
valid_sources[0x7b]	659	1			T4	7		T18	4		T56	3
valid_sources[0x7c]	666	1			T4	14		T12	3		T18	1
valid_sources[0x7d]	866	1			T1	1		T4	10		T41	1
valid_sources[0x7e]	812	1			T4	4		T40	1		T42	3
valid_sources[0x7f]	685	1			T4	25		T9	1		T41	1
valid_sources[0x80]	722	1			T4	4		T18	1		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39419

1

T2

5

T4

403

T9

2

values[0x0]

all_enables

biggest_size

54880

1

T1

1

T2

3

T3

2

values[0x1]

all_enables

biggest_size

52577

1

T1

1

T2

2

T3

3