Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16115020

1

T1

7785

T2

44

T3

17011

full_word

151159988

1

T1

77850

T2

490

T3

170355

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	167274718	1			T1	85635		T2	534		T3	187366
auto[TlIntgErrCmd]	98	1			T65	1		T66	3		T67	1
auto[TlIntgErrData]	96	1			T65	4		T66	3		T67	5
auto[TlIntgErrBoth]	96	1			T65	5		T66	4		T67	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80774724

1

T1

42829

T2

245

T3

93539

auto[1]

86500284

1

T1

42806

T2

289

T3

93827

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7899904	1			T1	3901		T2	22		T3	8397
auto[TlIntgErrNone]	partial	auto[1]	8214853	1			T1	3884		T2	22		T3	8614
auto[TlIntgErrNone]	full_word	auto[0]	72874688	1			T1	38928		T2	223		T3	85142
auto[TlIntgErrNone]	full_word	auto[1]	78285273	1			T1	38922		T2	267		T3	85213
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T65	1		T66	1		T121	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T66	2		T67	1		T121	7
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T121	1		T131	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T121	1		T127	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T65	1		T67	4		T121	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T66	3		T124	2		T127	8
auto[TlIntgErrData]	full_word	auto[0]	7	1			T65	3		T67	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T121	1		T124	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T65	2		T66	2		T67	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T65	3		T66	1		T67	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T123	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T66	1		T121	1		T126	1