Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	901109	1			T9	195		T6	1		T11	1706
auto[1]	10786462	1			T1	21652		T2	210		T3	57363
auto[2]	708439	1			T9	122		T11	1265		T18	2351
auto[3]	10482913	1			T1	21668		T2	259		T3	57466

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14313362	1			T1	36220		T2	397		T3	94671
auto[1]	2167491	1			T1	3370		T2	32		T3	9681
auto[2]	2189831	1			T1	3398		T2	38		T3	9493
auto[3]	4208239	1			T1	332		T2	2		T3	984

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9201902

1

T1

43316

T2

469

T3

114827

auto[1]

13677021

1

T1

4

T3

2

T5

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	262537	1			T9	166		T6	1		T18	3194
auto[0]	auto[0]	auto[1]	27825	1			T9	17		T18	333		T103	1
auto[0]	auto[0]	auto[2]	27982	1			T9	11		T18	340		T26	5
auto[0]	auto[0]	auto[3]	55092	1			T9	1		T18	25		T103	4
auto[0]	auto[1]	auto[0]	3364629	1			T1	18094		T2	179		T3	47336
auto[0]	auto[1]	auto[1]	352194	1			T1	1595		T2	11		T3	4862
auto[0]	auto[1]	auto[2]	361713	1			T1	1797		T2	18		T3	4671
auto[0]	auto[1]	auto[3]	289908	1			T1	164		T2	2		T3	492
auto[0]	auto[2]	auto[0]	196320	1			T9	103		T18	1995		T55	1
auto[0]	auto[2]	auto[1]	23445	1			T9	7		T18	204		T103	1
auto[0]	auto[2]	auto[2]	26367	1			T9	12		T18	136		T103	1
auto[0]	auto[2]	auto[3]	41478	1			T18	16		T103	3		T26	3
auto[0]	auto[3]	auto[0]	3209598	1			T1	18124		T2	218		T3	47334
auto[0]	auto[3]	auto[1]	342038	1			T1	1774		T2	21		T3	4819
auto[0]	auto[3]	auto[2]	356539	1			T1	1600		T2	20		T3	4821
auto[0]	auto[3]	auto[3]	264237	1			T1	168		T3	492		T5	300
auto[1]	auto[0]	auto[0]	17388	1			T11	53		T103	1086		T141	963
auto[1]	auto[0]	auto[1]	78418	1			T11	259		T103	4823		T141	4224
auto[1]	auto[0]	auto[2]	78282	1			T11	256		T103	4695		T141	4118
auto[1]	auto[0]	auto[3]	353585	1			T11	1138		T103	21699		T55	3
auto[1]	auto[1]	auto[0]	3627187	1			T3	1		T11	107		T40	1
auto[1]	auto[1]	auto[1]	667845	1			T1	1		T5	1		T11	828
auto[1]	auto[1]	auto[2]	625673	1			T1	1		T3	1		T11	461
auto[1]	auto[1]	auto[3]	1497313	1			T11	3451		T103	22002		T85	676
auto[1]	auto[2]	auto[0]	14170	1			T103	965		T141	842		T142	463
auto[1]	auto[2]	auto[1]	63702	1			T103	4498		T141	3828		T142	1856
auto[1]	auto[2]	auto[2]	62589	1			T11	269		T103	4087		T141	2807
auto[1]	auto[2]	auto[3]	280368	1			T11	996		T103	18302		T141	12702
auto[1]	auto[3]	auto[0]	3621533	1			T1	2		T5	2		T11	43
auto[1]	auto[3]	auto[1]	612024	1			T11	236		T103	369		T85	6891
auto[1]	auto[3]	auto[2]	650686	1			T11	743		T103	4106		T85	6274
auto[1]	auto[3]	auto[3]	1426258	1			T11	3351		T103	18517		T85	666