Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1131213240	211562	0	0
ctrl_regwen_rd_A	1131213240	2602	0	0
exec_rd_A	1131213240	2394	0	0
exec_regwen_rd_A	1131213240	2649	0	0
readback_rd_A	1131213240	1745	0	0
readback_regwen_rd_A	1131213240	1427	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131213240	211562	0	0
T4	93906	4121	0	0
T5	623208	0	0	0
T6	879290	0	0	0
T8	74574	0	0	0
T9	204941	0	0	0
T10	89660	0	0	0
T11	696578	0	0	0
T12	939	0	0	0
T23	72958	0	0	0
T24	0	1499	0	0
T25	0	2990	0	0
T40	834941	0	0	0
T46	0	3646	0	0
T57	0	10092	0	0
T59	0	6138	0	0
T71	0	1229	0	0
T72	0	6480	0	0
T73	0	2865	0	0
T74	0	3167	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131213240	2602	0	0
T15	20763	0	0	0
T24	36598	128	0	0
T25	0	258	0	0
T27	33767	0	0	0
T32	418402	0	0	0
T33	358194	0	0	0
T34	150970	0	0	0
T35	336192	0	0	0
T36	71640	0	0	0
T37	183434	0	0	0
T71	0	84	0	0
T74	0	134	0	0
T111	0	328	0	0
T112	0	256	0	0
T113	0	71	0	0
T114	0	281	0	0
T115	0	164	0	0
T116	0	46	0	0
T117	76844	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131213240	2394	0	0
T15	20763	0	0	0
T24	36598	137	0	0
T25	0	194	0	0
T27	33767	0	0	0
T32	418402	0	0	0
T33	358194	0	0	0
T34	150970	0	0	0
T35	336192	0	0	0
T36	71640	0	0	0
T37	183434	0	0	0
T71	0	53	0	0
T74	0	133	0	0
T111	0	291	0	0
T112	0	223	0	0
T113	0	59	0	0
T114	0	255	0	0
T115	0	104	0	0
T116	0	63	0	0
T117	76844	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131213240	2649	0	0
T15	20763	0	0	0
T24	36598	157	0	0
T25	0	254	0	0
T27	33767	0	0	0
T32	418402	0	0	0
T33	358194	0	0	0
T34	150970	0	0	0
T35	336192	0	0	0
T36	71640	0	0	0
T37	183434	0	0	0
T71	0	32	0	0
T74	0	94	0	0
T111	0	344	0	0
T112	0	241	0	0
T113	0	65	0	0
T114	0	407	0	0
T115	0	101	0	0
T116	0	15	0	0
T117	76844	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131213240	1745	0	0
T15	20763	0	0	0
T24	36598	103	0	0
T25	0	181	0	0
T27	33767	0	0	0
T32	418402	0	0	0
T33	358194	0	0	0
T34	150970	0	0	0
T35	336192	0	0	0
T36	71640	0	0	0
T37	183434	0	0	0
T71	0	66	0	0
T74	0	122	0	0
T111	0	290	0	0
T112	0	343	0	0
T113	0	34	0	0
T114	0	292	0	0
T115	0	38	0	0
T116	0	46	0	0
T117	76844	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131213240	1427	0	0
T15	20763	0	0	0
T24	36598	83	0	0
T25	0	179	0	0
T27	33767	0	0	0
T32	418402	0	0	0
T33	358194	0	0	0
T34	150970	0	0	0
T35	336192	0	0	0
T36	71640	0	0	0
T37	183434	0	0	0
T71	0	33	0	0
T74	0	95	0	0
T111	0	263	0	0
T112	0	241	0	0
T113	0	34	0	0
T114	0	217	0	0
T115	0	81	0	0
T116	0	38	0	0
T117	76844	0	0	0