| T797 |
/workspace/coverage/default/46.sram_ctrl_executable.1801468860 |
|
|
Aug 18 04:49:10 PM PDT 24 |
Aug 18 05:04:02 PM PDT 24 |
58987935382 ps |
| T798 |
/workspace/coverage/default/11.sram_ctrl_executable.4120816247 |
|
|
Aug 18 04:45:41 PM PDT 24 |
Aug 18 05:00:19 PM PDT 24 |
71833894290 ps |
| T799 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3241123762 |
|
|
Aug 18 04:45:21 PM PDT 24 |
Aug 18 04:49:32 PM PDT 24 |
18028069560 ps |
| T800 |
/workspace/coverage/default/35.sram_ctrl_smoke.2881157078 |
|
|
Aug 18 04:47:16 PM PDT 24 |
Aug 18 04:49:48 PM PDT 24 |
6020965370 ps |
| T801 |
/workspace/coverage/default/26.sram_ctrl_regwen.1940782742 |
|
|
Aug 18 04:46:18 PM PDT 24 |
Aug 18 05:07:36 PM PDT 24 |
171165895448 ps |
| T802 |
/workspace/coverage/default/18.sram_ctrl_executable.1009943564 |
|
|
Aug 18 04:45:49 PM PDT 24 |
Aug 18 04:50:34 PM PDT 24 |
3712162736 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.882391838 |
|
|
Aug 18 04:48:40 PM PDT 24 |
Aug 18 04:54:27 PM PDT 24 |
25667568641 ps |
| T804 |
/workspace/coverage/default/6.sram_ctrl_smoke.2278785077 |
|
|
Aug 18 04:45:33 PM PDT 24 |
Aug 18 04:46:45 PM PDT 24 |
7134260641 ps |
| T805 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4279438318 |
|
|
Aug 18 04:45:20 PM PDT 24 |
Aug 18 04:45:53 PM PDT 24 |
3007245818 ps |
| T806 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3723678828 |
|
|
Aug 18 04:47:18 PM PDT 24 |
Aug 18 04:53:57 PM PDT 24 |
19135990485 ps |
| T807 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2277559672 |
|
|
Aug 18 04:48:01 PM PDT 24 |
Aug 18 04:57:05 PM PDT 24 |
25411433843 ps |
| T808 |
/workspace/coverage/default/23.sram_ctrl_smoke.1032860474 |
|
|
Aug 18 04:46:16 PM PDT 24 |
Aug 18 04:46:58 PM PDT 24 |
1058184930 ps |
| T809 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2119556768 |
|
|
Aug 18 04:45:23 PM PDT 24 |
Aug 18 04:45:24 PM PDT 24 |
11290563 ps |
| T810 |
/workspace/coverage/default/39.sram_ctrl_smoke.4256178224 |
|
|
Aug 18 04:47:54 PM PDT 24 |
Aug 18 04:49:40 PM PDT 24 |
774530716 ps |
| T811 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.4155653705 |
|
|
Aug 18 04:45:58 PM PDT 24 |
Aug 18 04:46:55 PM PDT 24 |
1506286099 ps |
| T43 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.138466865 |
|
|
Aug 18 04:45:13 PM PDT 24 |
Aug 18 04:45:52 PM PDT 24 |
4802888001 ps |
| T812 |
/workspace/coverage/default/29.sram_ctrl_bijection.1195043263 |
|
|
Aug 18 04:46:38 PM PDT 24 |
Aug 18 05:11:31 PM PDT 24 |
22297885420 ps |
| T813 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.200633830 |
|
|
Aug 18 04:46:03 PM PDT 24 |
Aug 18 05:01:55 PM PDT 24 |
23134298781 ps |
| T814 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.307262368 |
|
|
Aug 18 04:45:27 PM PDT 24 |
Aug 18 04:45:31 PM PDT 24 |
1352792043 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3996032278 |
|
|
Aug 18 04:46:02 PM PDT 24 |
Aug 18 04:52:23 PM PDT 24 |
16858960549 ps |
| T816 |
/workspace/coverage/default/8.sram_ctrl_stress_all.499176466 |
|
|
Aug 18 04:45:26 PM PDT 24 |
Aug 18 05:36:07 PM PDT 24 |
30273899132 ps |
| T817 |
/workspace/coverage/default/3.sram_ctrl_executable.720172886 |
|
|
Aug 18 04:45:14 PM PDT 24 |
Aug 18 04:48:23 PM PDT 24 |
2427595933 ps |
| T818 |
/workspace/coverage/default/32.sram_ctrl_bijection.3169083460 |
|
|
Aug 18 04:46:57 PM PDT 24 |
Aug 18 05:01:56 PM PDT 24 |
32803445334 ps |
| T819 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2986138703 |
|
|
Aug 18 04:45:42 PM PDT 24 |
Aug 18 04:45:46 PM PDT 24 |
1358189280 ps |
| T820 |
/workspace/coverage/default/0.sram_ctrl_alert_test.185048570 |
|
|
Aug 18 04:45:19 PM PDT 24 |
Aug 18 04:45:20 PM PDT 24 |
48072172 ps |
| T821 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3670865229 |
|
|
Aug 18 04:47:46 PM PDT 24 |
Aug 18 05:32:03 PM PDT 24 |
109065433748 ps |
| T822 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3719382901 |
|
|
Aug 18 04:45:48 PM PDT 24 |
Aug 18 04:48:15 PM PDT 24 |
4396778372 ps |
| T823 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2364100615 |
|
|
Aug 18 04:47:42 PM PDT 24 |
Aug 18 04:50:05 PM PDT 24 |
1871613709 ps |
| T824 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.800982486 |
|
|
Aug 18 04:46:13 PM PDT 24 |
Aug 18 04:46:36 PM PDT 24 |
14351037081 ps |
| T825 |
/workspace/coverage/default/15.sram_ctrl_bijection.1435641874 |
|
|
Aug 18 04:45:48 PM PDT 24 |
Aug 18 05:16:04 PM PDT 24 |
82418083789 ps |
| T826 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1194375123 |
|
|
Aug 18 04:45:53 PM PDT 24 |
Aug 18 04:51:48 PM PDT 24 |
14594011885 ps |
| T827 |
/workspace/coverage/default/45.sram_ctrl_executable.978503193 |
|
|
Aug 18 04:49:01 PM PDT 24 |
Aug 18 04:58:36 PM PDT 24 |
23490129223 ps |
| T828 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2209559846 |
|
|
Aug 18 04:49:30 PM PDT 24 |
Aug 18 04:54:01 PM PDT 24 |
4936935569 ps |
| T829 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1569796701 |
|
|
Aug 18 04:45:39 PM PDT 24 |
Aug 18 04:46:50 PM PDT 24 |
11201638802 ps |
| T830 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2332780495 |
|
|
Aug 18 04:45:22 PM PDT 24 |
Aug 18 04:48:08 PM PDT 24 |
3356204402 ps |
| T831 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3951768613 |
|
|
Aug 18 04:47:08 PM PDT 24 |
Aug 18 04:53:23 PM PDT 24 |
60961164325 ps |
| T832 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.618439813 |
|
|
Aug 18 04:45:05 PM PDT 24 |
Aug 18 04:45:08 PM PDT 24 |
1673375495 ps |
| T833 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1790895233 |
|
|
Aug 18 04:46:57 PM PDT 24 |
Aug 18 04:46:58 PM PDT 24 |
14207175 ps |
| T834 |
/workspace/coverage/default/40.sram_ctrl_bijection.1207768486 |
|
|
Aug 18 04:48:00 PM PDT 24 |
Aug 18 05:19:52 PM PDT 24 |
398908640109 ps |
| T835 |
/workspace/coverage/default/28.sram_ctrl_bijection.3711761108 |
|
|
Aug 18 04:46:36 PM PDT 24 |
Aug 18 04:58:17 PM PDT 24 |
43404904932 ps |
| T836 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.1556111542 |
|
|
Aug 18 04:46:36 PM PDT 24 |
Aug 18 04:47:21 PM PDT 24 |
7370789465 ps |
| T837 |
/workspace/coverage/default/39.sram_ctrl_alert_test.2501341322 |
|
|
Aug 18 04:48:00 PM PDT 24 |
Aug 18 04:48:01 PM PDT 24 |
18423992 ps |
| T838 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3164153739 |
|
|
Aug 18 04:45:59 PM PDT 24 |
Aug 18 04:46:02 PM PDT 24 |
1295707848 ps |
| T839 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1377575431 |
|
|
Aug 18 04:47:50 PM PDT 24 |
Aug 18 04:48:19 PM PDT 24 |
737720449 ps |
| T840 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3120007322 |
|
|
Aug 18 04:45:53 PM PDT 24 |
Aug 18 04:47:36 PM PDT 24 |
17422270395 ps |
| T841 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1445115967 |
|
|
Aug 18 04:49:13 PM PDT 24 |
Aug 18 04:50:17 PM PDT 24 |
22391839401 ps |
| T842 |
/workspace/coverage/default/20.sram_ctrl_bijection.3353016197 |
|
|
Aug 18 04:45:57 PM PDT 24 |
Aug 18 05:10:50 PM PDT 24 |
778611056262 ps |
| T843 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.1379615122 |
|
|
Aug 18 04:46:09 PM PDT 24 |
Aug 18 04:46:24 PM PDT 24 |
2768290439 ps |
| T844 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.3494257700 |
|
|
Aug 18 04:49:03 PM PDT 24 |
Aug 18 04:50:54 PM PDT 24 |
772525936 ps |
| T845 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.4273060400 |
|
|
Aug 18 04:46:15 PM PDT 24 |
Aug 18 04:48:47 PM PDT 24 |
2742154986 ps |
| T846 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3856368335 |
|
|
Aug 18 04:49:11 PM PDT 24 |
Aug 18 04:51:15 PM PDT 24 |
4112342399 ps |
| T847 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.4026197140 |
|
|
Aug 18 04:46:11 PM PDT 24 |
Aug 18 04:56:35 PM PDT 24 |
36925121925 ps |
| T848 |
/workspace/coverage/default/1.sram_ctrl_regwen.912774307 |
|
|
Aug 18 04:45:16 PM PDT 24 |
Aug 18 04:57:22 PM PDT 24 |
28391076452 ps |
| T849 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1580725278 |
|
|
Aug 18 04:47:06 PM PDT 24 |
Aug 18 04:47:31 PM PDT 24 |
1011049530 ps |
| T850 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2956636932 |
|
|
Aug 18 04:45:18 PM PDT 24 |
Aug 18 04:48:15 PM PDT 24 |
27710188846 ps |
| T851 |
/workspace/coverage/default/35.sram_ctrl_bijection.2367465960 |
|
|
Aug 18 04:47:30 PM PDT 24 |
Aug 18 05:27:02 PM PDT 24 |
551729173674 ps |
| T852 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1590593348 |
|
|
Aug 18 04:46:45 PM PDT 24 |
Aug 18 04:52:53 PM PDT 24 |
4997008945 ps |
| T853 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.167275574 |
|
|
Aug 18 04:45:54 PM PDT 24 |
Aug 18 04:48:08 PM PDT 24 |
7898097823 ps |
| T854 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.140998002 |
|
|
Aug 18 04:48:22 PM PDT 24 |
Aug 18 04:54:03 PM PDT 24 |
81350832247 ps |
| T855 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2971377193 |
|
|
Aug 18 04:49:02 PM PDT 24 |
Aug 18 04:49:34 PM PDT 24 |
4776134267 ps |
| T856 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.877798474 |
|
|
Aug 18 04:49:31 PM PDT 24 |
Aug 18 04:56:07 PM PDT 24 |
27206822908 ps |
| T857 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2654399585 |
|
|
Aug 18 04:49:39 PM PDT 24 |
Aug 18 04:50:20 PM PDT 24 |
65284365942 ps |
| T858 |
/workspace/coverage/default/44.sram_ctrl_bijection.2883577342 |
|
|
Aug 18 04:48:43 PM PDT 24 |
Aug 18 05:28:09 PM PDT 24 |
143675003036 ps |
| T859 |
/workspace/coverage/default/36.sram_ctrl_regwen.1060189681 |
|
|
Aug 18 04:47:42 PM PDT 24 |
Aug 18 05:06:00 PM PDT 24 |
43881208801 ps |
| T860 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1865768687 |
|
|
Aug 18 04:46:28 PM PDT 24 |
Aug 18 06:13:54 PM PDT 24 |
1491853646719 ps |
| T861 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.485076374 |
|
|
Aug 18 04:45:21 PM PDT 24 |
Aug 18 04:46:23 PM PDT 24 |
986620506 ps |
| T862 |
/workspace/coverage/default/12.sram_ctrl_bijection.1207254805 |
|
|
Aug 18 04:45:43 PM PDT 24 |
Aug 18 05:23:00 PM PDT 24 |
873996993939 ps |
| T863 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3273648040 |
|
|
Aug 18 04:45:35 PM PDT 24 |
Aug 18 04:54:21 PM PDT 24 |
18126877494 ps |
| T864 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.4106985567 |
|
|
Aug 18 04:45:58 PM PDT 24 |
Aug 18 05:08:31 PM PDT 24 |
8614017307 ps |
| T865 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2794769962 |
|
|
Aug 18 04:45:19 PM PDT 24 |
Aug 18 04:46:17 PM PDT 24 |
3808685751 ps |
| T866 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.112497155 |
|
|
Aug 18 04:47:50 PM PDT 24 |
Aug 18 04:48:08 PM PDT 24 |
3232125206 ps |
| T867 |
/workspace/coverage/default/5.sram_ctrl_executable.2403287124 |
|
|
Aug 18 04:45:46 PM PDT 24 |
Aug 18 04:53:44 PM PDT 24 |
10395132233 ps |
| T868 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3446886829 |
|
|
Aug 18 04:48:00 PM PDT 24 |
Aug 18 04:58:09 PM PDT 24 |
20771764728 ps |
| T869 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1982296228 |
|
|
Aug 18 04:48:35 PM PDT 24 |
Aug 18 04:59:51 PM PDT 24 |
9592574730 ps |
| T870 |
/workspace/coverage/default/1.sram_ctrl_smoke.3267108286 |
|
|
Aug 18 04:45:18 PM PDT 24 |
Aug 18 04:46:06 PM PDT 24 |
2911462741 ps |
| T871 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.1807498128 |
|
|
Aug 18 04:45:50 PM PDT 24 |
Aug 18 04:46:53 PM PDT 24 |
110370772585 ps |
| T872 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2938044776 |
|
|
Aug 18 04:46:00 PM PDT 24 |
Aug 18 04:47:26 PM PDT 24 |
2022155242 ps |
| T873 |
/workspace/coverage/default/41.sram_ctrl_partial_access.220324938 |
|
|
Aug 18 04:48:12 PM PDT 24 |
Aug 18 04:48:23 PM PDT 24 |
1840824442 ps |
| T874 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2245906805 |
|
|
Aug 18 04:48:12 PM PDT 24 |
Aug 18 04:48:38 PM PDT 24 |
2592714195 ps |
| T875 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3714766827 |
|
|
Aug 18 04:47:07 PM PDT 24 |
Aug 18 04:48:39 PM PDT 24 |
10528110088 ps |
| T876 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3157097133 |
|
|
Aug 18 04:45:21 PM PDT 24 |
Aug 18 04:45:36 PM PDT 24 |
3449186342 ps |
| T877 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.704493466 |
|
|
Aug 18 04:46:45 PM PDT 24 |
Aug 18 04:48:04 PM PDT 24 |
4831536732 ps |
| T878 |
/workspace/coverage/default/5.sram_ctrl_regwen.772710539 |
|
|
Aug 18 04:45:34 PM PDT 24 |
Aug 18 04:53:55 PM PDT 24 |
3596739345 ps |
| T879 |
/workspace/coverage/default/49.sram_ctrl_regwen.3984184570 |
|
|
Aug 18 04:49:30 PM PDT 24 |
Aug 18 05:07:49 PM PDT 24 |
3548440790 ps |
| T880 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2121678524 |
|
|
Aug 18 04:47:06 PM PDT 24 |
Aug 18 04:49:07 PM PDT 24 |
2683797327 ps |
| T881 |
/workspace/coverage/default/9.sram_ctrl_bijection.1581627702 |
|
|
Aug 18 04:45:43 PM PDT 24 |
Aug 18 05:02:41 PM PDT 24 |
64886813078 ps |
| T882 |
/workspace/coverage/default/24.sram_ctrl_executable.1236338325 |
|
|
Aug 18 04:46:14 PM PDT 24 |
Aug 18 04:55:56 PM PDT 24 |
7251328682 ps |
| T883 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.4274211168 |
|
|
Aug 18 04:46:14 PM PDT 24 |
Aug 18 04:46:17 PM PDT 24 |
353897609 ps |
| T884 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.804004192 |
|
|
Aug 18 04:49:20 PM PDT 24 |
Aug 18 04:49:24 PM PDT 24 |
1775659691 ps |
| T885 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1857302993 |
|
|
Aug 18 04:45:15 PM PDT 24 |
Aug 18 04:46:15 PM PDT 24 |
1516493369 ps |
| T886 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1075462715 |
|
|
Aug 18 04:46:46 PM PDT 24 |
Aug 18 04:46:50 PM PDT 24 |
1343858134 ps |
| T887 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1460502680 |
|
|
Aug 18 04:46:17 PM PDT 24 |
Aug 18 04:46:24 PM PDT 24 |
2662987111 ps |
| T888 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3211744554 |
|
|
Aug 18 04:45:43 PM PDT 24 |
Aug 18 04:49:40 PM PDT 24 |
7810951836 ps |
| T889 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1465566851 |
|
|
Aug 18 04:45:45 PM PDT 24 |
Aug 18 05:00:23 PM PDT 24 |
80012091231 ps |
| T890 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1176941978 |
|
|
Aug 18 04:45:58 PM PDT 24 |
Aug 18 04:46:13 PM PDT 24 |
1014459111 ps |
| T891 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.875099504 |
|
|
Aug 18 04:45:44 PM PDT 24 |
Aug 18 04:50:23 PM PDT 24 |
5496218681 ps |
| T892 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3414776622 |
|
|
Aug 18 04:46:54 PM PDT 24 |
Aug 18 04:52:03 PM PDT 24 |
13740831223 ps |
| T893 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2249110501 |
|
|
Aug 18 04:45:44 PM PDT 24 |
Aug 18 04:47:36 PM PDT 24 |
813103050 ps |
| T894 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3621896220 |
|
|
Aug 18 04:46:14 PM PDT 24 |
Aug 18 04:46:17 PM PDT 24 |
702981175 ps |
| T895 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2847718501 |
|
|
Aug 18 04:46:07 PM PDT 24 |
Aug 18 04:46:38 PM PDT 24 |
9257932572 ps |
| T896 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3480216555 |
|
|
Aug 18 04:49:00 PM PDT 24 |
Aug 18 06:14:47 PM PDT 24 |
299329827637 ps |
| T897 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3129144376 |
|
|
Aug 18 04:45:19 PM PDT 24 |
Aug 18 04:45:22 PM PDT 24 |
1400676001 ps |
| T898 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.599008658 |
|
|
Aug 18 04:45:46 PM PDT 24 |
Aug 18 04:51:28 PM PDT 24 |
21516152590 ps |
| T899 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2722764459 |
|
|
Aug 18 04:46:55 PM PDT 24 |
Aug 18 04:46:58 PM PDT 24 |
680841150 ps |
| T900 |
/workspace/coverage/default/46.sram_ctrl_partial_access.4261033012 |
|
|
Aug 18 04:49:01 PM PDT 24 |
Aug 18 04:49:54 PM PDT 24 |
4269640852 ps |
| T901 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.793557714 |
|
|
Aug 18 04:45:48 PM PDT 24 |
Aug 18 04:46:00 PM PDT 24 |
1377149799 ps |
| T902 |
/workspace/coverage/default/28.sram_ctrl_executable.3846344865 |
|
|
Aug 18 04:46:38 PM PDT 24 |
Aug 18 04:55:06 PM PDT 24 |
3525276085 ps |
| T903 |
/workspace/coverage/default/34.sram_ctrl_executable.3825890229 |
|
|
Aug 18 04:47:15 PM PDT 24 |
Aug 18 05:04:58 PM PDT 24 |
40817100804 ps |
| T904 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.366683019 |
|
|
Aug 18 04:47:42 PM PDT 24 |
Aug 18 04:52:17 PM PDT 24 |
4221104968 ps |
| T905 |
/workspace/coverage/default/27.sram_ctrl_bijection.1491562079 |
|
|
Aug 18 04:46:19 PM PDT 24 |
Aug 18 05:32:11 PM PDT 24 |
167207023263 ps |
| T906 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.982389658 |
|
|
Aug 18 04:47:06 PM PDT 24 |
Aug 18 04:52:15 PM PDT 24 |
32822576055 ps |
| T907 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.585593322 |
|
|
Aug 18 04:45:25 PM PDT 24 |
Aug 18 04:46:54 PM PDT 24 |
50252129588 ps |
| T908 |
/workspace/coverage/default/29.sram_ctrl_stress_all.2802571588 |
|
|
Aug 18 04:46:45 PM PDT 24 |
Aug 18 06:29:24 PM PDT 24 |
594962641462 ps |
| T909 |
/workspace/coverage/default/8.sram_ctrl_executable.3220430532 |
|
|
Aug 18 04:45:20 PM PDT 24 |
Aug 18 04:45:52 PM PDT 24 |
5538155129 ps |
| T910 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2904214835 |
|
|
Aug 18 04:45:18 PM PDT 24 |
Aug 18 05:27:59 PM PDT 24 |
32563253589 ps |
| T911 |
/workspace/coverage/default/49.sram_ctrl_executable.3895070908 |
|
|
Aug 18 04:49:36 PM PDT 24 |
Aug 18 05:12:38 PM PDT 24 |
37705079530 ps |
| T912 |
/workspace/coverage/default/15.sram_ctrl_executable.1885059529 |
|
|
Aug 18 04:46:00 PM PDT 24 |
Aug 18 04:49:43 PM PDT 24 |
12997613977 ps |
| T913 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4161887985 |
|
|
Aug 18 04:48:22 PM PDT 24 |
Aug 18 04:50:14 PM PDT 24 |
1538742135 ps |
| T914 |
/workspace/coverage/default/16.sram_ctrl_executable.4265164090 |
|
|
Aug 18 04:45:48 PM PDT 24 |
Aug 18 04:55:54 PM PDT 24 |
29195083985 ps |
| T915 |
/workspace/coverage/default/4.sram_ctrl_stress_all.1319210644 |
|
|
Aug 18 04:45:25 PM PDT 24 |
Aug 18 06:24:37 PM PDT 24 |
272391113708 ps |
| T916 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1529927028 |
|
|
Aug 18 04:46:20 PM PDT 24 |
Aug 18 04:47:51 PM PDT 24 |
2608619198 ps |
| T917 |
/workspace/coverage/default/22.sram_ctrl_smoke.1653597613 |
|
|
Aug 18 04:46:03 PM PDT 24 |
Aug 18 04:46:47 PM PDT 24 |
6090673139 ps |
| T918 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3526402420 |
|
|
Aug 18 04:49:01 PM PDT 24 |
Aug 18 04:59:39 PM PDT 24 |
63441231045 ps |
| T919 |
/workspace/coverage/default/1.sram_ctrl_bijection.2288312267 |
|
|
Aug 18 04:45:21 PM PDT 24 |
Aug 18 05:06:24 PM PDT 24 |
36202126713 ps |
| T920 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1770968454 |
|
|
Aug 18 04:46:15 PM PDT 24 |
Aug 18 05:40:20 PM PDT 24 |
271964620537 ps |
| T921 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1892759655 |
|
|
Aug 18 04:47:30 PM PDT 24 |
Aug 18 05:10:40 PM PDT 24 |
30108309246 ps |
| T922 |
/workspace/coverage/default/2.sram_ctrl_regwen.307744684 |
|
|
Aug 18 04:45:26 PM PDT 24 |
Aug 18 04:58:43 PM PDT 24 |
25076657381 ps |
| T923 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.3085237299 |
|
|
Aug 18 04:46:09 PM PDT 24 |
Aug 18 05:06:46 PM PDT 24 |
128436986691 ps |
| T924 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1100519104 |
|
|
Aug 18 04:45:15 PM PDT 24 |
Aug 18 04:52:33 PM PDT 24 |
36199271356 ps |
| T925 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2517570808 |
|
|
Aug 18 04:48:20 PM PDT 24 |
Aug 18 04:48:21 PM PDT 24 |
73660243 ps |
| T926 |
/workspace/coverage/default/0.sram_ctrl_smoke.2676065940 |
|
|
Aug 18 04:45:18 PM PDT 24 |
Aug 18 04:45:39 PM PDT 24 |
10675231499 ps |
| T927 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.278862348 |
|
|
Aug 18 04:45:59 PM PDT 24 |
Aug 18 04:51:21 PM PDT 24 |
5475391397 ps |
| T928 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.665914774 |
|
|
Aug 18 04:45:31 PM PDT 24 |
Aug 18 04:45:58 PM PDT 24 |
2130756743 ps |
| T929 |
/workspace/coverage/default/45.sram_ctrl_bijection.1986142164 |
|
|
Aug 18 04:48:55 PM PDT 24 |
Aug 18 05:05:42 PM PDT 24 |
15283182188 ps |
| T930 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3487842678 |
|
|
Aug 18 04:46:08 PM PDT 24 |
Aug 18 04:54:02 PM PDT 24 |
5807597907 ps |
| T931 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2063982860 |
|
|
Aug 18 04:46:09 PM PDT 24 |
Aug 18 04:46:10 PM PDT 24 |
34663269 ps |
| T932 |
/workspace/coverage/default/25.sram_ctrl_executable.1969520734 |
|
|
Aug 18 04:46:16 PM PDT 24 |
Aug 18 05:11:38 PM PDT 24 |
16193725521 ps |
| T933 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3087402215 |
|
|
Aug 18 04:48:11 PM PDT 24 |
Aug 18 04:54:12 PM PDT 24 |
6276191534 ps |
| T934 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1866286844 |
|
|
Aug 18 04:46:14 PM PDT 24 |
Aug 18 04:46:31 PM PDT 24 |
4519709888 ps |
| T935 |
/workspace/coverage/default/9.sram_ctrl_alert_test.218265372 |
|
|
Aug 18 04:45:48 PM PDT 24 |
Aug 18 04:45:49 PM PDT 24 |
21239548 ps |
| T936 |
/workspace/coverage/default/39.sram_ctrl_bijection.267335772 |
|
|
Aug 18 04:47:53 PM PDT 24 |
Aug 18 04:58:06 PM PDT 24 |
248186229550 ps |
| T937 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.38486892 |
|
|
Aug 18 04:46:16 PM PDT 24 |
Aug 18 04:50:34 PM PDT 24 |
10148182991 ps |
| T938 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3764127000 |
|
|
Aug 18 04:48:52 PM PDT 24 |
Aug 18 04:50:09 PM PDT 24 |
13129346870 ps |
| T939 |
/workspace/coverage/default/35.sram_ctrl_executable.575098231 |
|
|
Aug 18 04:47:29 PM PDT 24 |
Aug 18 04:53:13 PM PDT 24 |
14952935862 ps |
| T940 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2396147527 |
|
|
Aug 18 04:45:45 PM PDT 24 |
Aug 18 04:46:56 PM PDT 24 |
5358726392 ps |
| T941 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1562110314 |
|
|
Aug 18 04:47:59 PM PDT 24 |
Aug 18 04:48:05 PM PDT 24 |
1310510322 ps |
| T942 |
/workspace/coverage/default/9.sram_ctrl_partial_access.827221921 |
|
|
Aug 18 04:45:26 PM PDT 24 |
Aug 18 04:47:26 PM PDT 24 |
6597591836 ps |
| T943 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2502349923 |
|
|
Aug 18 04:45:45 PM PDT 24 |
Aug 18 04:46:55 PM PDT 24 |
46899008351 ps |
| T944 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3096962608 |
|
|
Aug 18 04:46:02 PM PDT 24 |
Aug 18 04:48:43 PM PDT 24 |
13641368280 ps |
| T69 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3471256697 |
|
|
Aug 18 05:48:57 PM PDT 24 |
Aug 18 05:48:58 PM PDT 24 |
96927899 ps |
| T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1130815208 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:48 PM PDT 24 |
355430387 ps |
| T65 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.233958268 |
|
|
Aug 18 05:48:46 PM PDT 24 |
Aug 18 05:48:48 PM PDT 24 |
372805202 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2323288148 |
|
|
Aug 18 05:48:46 PM PDT 24 |
Aug 18 05:48:50 PM PDT 24 |
363781955 ps |
| T947 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3122274673 |
|
|
Aug 18 05:48:53 PM PDT 24 |
Aug 18 05:48:56 PM PDT 24 |
1375508864 ps |
| T66 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3746259157 |
|
|
Aug 18 05:48:51 PM PDT 24 |
Aug 18 05:48:52 PM PDT 24 |
99019802 ps |
| T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3330854896 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:49:06 PM PDT 24 |
4000116063 ps |
| T76 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3694485540 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:39 PM PDT 24 |
13194524 ps |
| T67 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2410496678 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:47 PM PDT 24 |
282064521 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1484765475 |
|
|
Aug 18 05:48:42 PM PDT 24 |
Aug 18 05:48:45 PM PDT 24 |
76285236 ps |
| T949 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4050491195 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:42 PM PDT 24 |
355724000 ps |
| T77 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1790554904 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:46 PM PDT 24 |
38746745 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3192867521 |
|
|
Aug 18 05:48:30 PM PDT 24 |
Aug 18 05:48:31 PM PDT 24 |
17958417 ps |
| T121 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3557711083 |
|
|
Aug 18 05:48:41 PM PDT 24 |
Aug 18 05:48:44 PM PDT 24 |
211511318 ps |
| T950 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2870196941 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:47 PM PDT 24 |
732713557 ps |
| T951 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.280325807 |
|
|
Aug 18 05:48:39 PM PDT 24 |
Aug 18 05:48:43 PM PDT 24 |
1479049948 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3233063985 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:46 PM PDT 24 |
82445218 ps |
| T953 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.884404389 |
|
|
Aug 18 05:48:46 PM PDT 24 |
Aug 18 05:48:50 PM PDT 24 |
403826064 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1735041678 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:40 PM PDT 24 |
58618443 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1730886352 |
|
|
Aug 18 05:48:47 PM PDT 24 |
Aug 18 05:48:52 PM PDT 24 |
266272191 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.573378626 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:49 PM PDT 24 |
500752367 ps |
| T79 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3540565304 |
|
|
Aug 18 05:48:37 PM PDT 24 |
Aug 18 05:48:38 PM PDT 24 |
21381632 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2253487153 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:49 PM PDT 24 |
711986978 ps |
| T124 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4153134473 |
|
|
Aug 18 05:48:39 PM PDT 24 |
Aug 18 05:48:40 PM PDT 24 |
402598579 ps |
| T80 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3054426925 |
|
|
Aug 18 05:48:53 PM PDT 24 |
Aug 18 05:49:20 PM PDT 24 |
7104474760 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3902928983 |
|
|
Aug 18 05:48:43 PM PDT 24 |
Aug 18 05:48:49 PM PDT 24 |
160999754 ps |
| T81 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2401168790 |
|
|
Aug 18 05:48:53 PM PDT 24 |
Aug 18 05:48:54 PM PDT 24 |
36563021 ps |
| T82 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3473477168 |
|
|
Aug 18 05:48:37 PM PDT 24 |
Aug 18 05:48:38 PM PDT 24 |
16440418 ps |
| T110 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1037678921 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:45 PM PDT 24 |
43878942 ps |
| T127 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1711710127 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:41 PM PDT 24 |
186938404 ps |
| T83 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1754702180 |
|
|
Aug 18 05:48:54 PM PDT 24 |
Aug 18 05:48:55 PM PDT 24 |
94521722 ps |
| T84 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2001417870 |
|
|
Aug 18 05:48:37 PM PDT 24 |
Aug 18 05:48:39 PM PDT 24 |
46336362 ps |
| T959 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1517757042 |
|
|
Aug 18 05:48:50 PM PDT 24 |
Aug 18 05:48:54 PM PDT 24 |
366483675 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1730350670 |
|
|
Aug 18 05:48:37 PM PDT 24 |
Aug 18 05:48:38 PM PDT 24 |
24144383 ps |
| T86 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.861601781 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:46 PM PDT 24 |
13872357 ps |
| T104 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2142367935 |
|
|
Aug 18 05:48:36 PM PDT 24 |
Aug 18 05:48:36 PM PDT 24 |
20107581 ps |
| T961 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2592546264 |
|
|
Aug 18 05:48:53 PM PDT 24 |
Aug 18 05:48:57 PM PDT 24 |
421880896 ps |
| T962 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2292536330 |
|
|
Aug 18 05:48:43 PM PDT 24 |
Aug 18 05:49:16 PM PDT 24 |
15377828889 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.945826510 |
|
|
Aug 18 05:48:36 PM PDT 24 |
Aug 18 05:48:37 PM PDT 24 |
17922750 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.112241754 |
|
|
Aug 18 05:48:42 PM PDT 24 |
Aug 18 05:48:46 PM PDT 24 |
697690187 ps |
| T130 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.612753415 |
|
|
Aug 18 05:48:39 PM PDT 24 |
Aug 18 05:48:41 PM PDT 24 |
239650502 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2398674312 |
|
|
Aug 18 05:48:35 PM PDT 24 |
Aug 18 05:49:04 PM PDT 24 |
14813892022 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1620675254 |
|
|
Aug 18 05:48:46 PM PDT 24 |
Aug 18 05:48:48 PM PDT 24 |
64948323 ps |
| T966 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1920327089 |
|
|
Aug 18 05:48:47 PM PDT 24 |
Aug 18 05:48:50 PM PDT 24 |
84971226 ps |
| T967 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2077440905 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:40 PM PDT 24 |
64639680 ps |
| T968 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1640794632 |
|
|
Aug 18 05:48:52 PM PDT 24 |
Aug 18 05:48:54 PM PDT 24 |
126807988 ps |
| T969 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.767762315 |
|
|
Aug 18 05:48:37 PM PDT 24 |
Aug 18 05:48:40 PM PDT 24 |
1359361592 ps |
| T106 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3858475536 |
|
|
Aug 18 05:49:03 PM PDT 24 |
Aug 18 05:49:05 PM PDT 24 |
46168165 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.822135513 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:38 PM PDT 24 |
34986815 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3233949222 |
|
|
Aug 18 05:48:37 PM PDT 24 |
Aug 18 05:48:38 PM PDT 24 |
49534327 ps |
| T108 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1242831994 |
|
|
Aug 18 05:48:40 PM PDT 24 |
Aug 18 05:48:41 PM PDT 24 |
30854021 ps |
| T971 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1104664288 |
|
|
Aug 18 05:48:46 PM PDT 24 |
Aug 18 05:48:49 PM PDT 24 |
285524824 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1687946988 |
|
|
Aug 18 05:48:56 PM PDT 24 |
Aug 18 05:48:57 PM PDT 24 |
56806864 ps |
| T125 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.840897629 |
|
|
Aug 18 05:48:42 PM PDT 24 |
Aug 18 05:48:45 PM PDT 24 |
140241312 ps |
| T87 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3193518819 |
|
|
Aug 18 05:48:47 PM PDT 24 |
Aug 18 05:49:39 PM PDT 24 |
33510718439 ps |
| T88 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1711151637 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:46 PM PDT 24 |
37024341 ps |
| T973 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3874868627 |
|
|
Aug 18 05:48:41 PM PDT 24 |
Aug 18 05:48:41 PM PDT 24 |
25507960 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3713317663 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:50 PM PDT 24 |
52926955 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.261503398 |
|
|
Aug 18 05:48:29 PM PDT 24 |
Aug 18 05:49:29 PM PDT 24 |
14679510103 ps |
| T976 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.211205504 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:49:08 PM PDT 24 |
5865573574 ps |
| T126 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1068656064 |
|
|
Aug 18 05:48:35 PM PDT 24 |
Aug 18 05:48:37 PM PDT 24 |
99953639 ps |
| T89 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2928340814 |
|
|
Aug 18 05:48:56 PM PDT 24 |
Aug 18 05:48:57 PM PDT 24 |
16200807 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3109517837 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:45 PM PDT 24 |
12274108 ps |
| T132 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.404052258 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:41 PM PDT 24 |
688399884 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3626376442 |
|
|
Aug 18 05:48:40 PM PDT 24 |
Aug 18 05:48:42 PM PDT 24 |
66823736 ps |
| T131 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.598816631 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:45 PM PDT 24 |
140160889 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.463135877 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:46 PM PDT 24 |
22280050 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3401691014 |
|
|
Aug 18 05:48:48 PM PDT 24 |
Aug 18 05:48:49 PM PDT 24 |
176921051 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1467687700 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:46 PM PDT 24 |
92289372 ps |
| T982 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1164565585 |
|
|
Aug 18 05:48:53 PM PDT 24 |
Aug 18 05:48:58 PM PDT 24 |
1417395452 ps |
| T983 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.332802234 |
|
|
Aug 18 05:48:53 PM PDT 24 |
Aug 18 05:48:55 PM PDT 24 |
50841285 ps |
| T984 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1665023683 |
|
|
Aug 18 05:48:55 PM PDT 24 |
Aug 18 05:48:58 PM PDT 24 |
901061491 ps |
| T985 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3475923360 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:45 PM PDT 24 |
24117405 ps |
| T90 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3803861026 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:39 PM PDT 24 |
16229483 ps |
| T986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1843713462 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:49 PM PDT 24 |
41319543 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4154844744 |
|
|
Aug 18 05:48:41 PM PDT 24 |
Aug 18 05:48:42 PM PDT 24 |
25685139 ps |
| T91 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.290615110 |
|
|
Aug 18 05:48:45 PM PDT 24 |
Aug 18 05:48:46 PM PDT 24 |
14736119 ps |
| T988 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.651579936 |
|
|
Aug 18 05:48:36 PM PDT 24 |
Aug 18 05:48:37 PM PDT 24 |
36267482 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1665751027 |
|
|
Aug 18 05:48:29 PM PDT 24 |
Aug 18 05:48:32 PM PDT 24 |
26812519 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2365572953 |
|
|
Aug 18 05:48:54 PM PDT 24 |
Aug 18 05:48:58 PM PDT 24 |
357790635 ps |
| T128 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1567854850 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:47 PM PDT 24 |
192507489 ps |
| T92 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1180353638 |
|
|
Aug 18 05:48:56 PM PDT 24 |
Aug 18 05:49:51 PM PDT 24 |
70320595988 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3496406884 |
|
|
Aug 18 05:48:55 PM PDT 24 |
Aug 18 05:48:56 PM PDT 24 |
21046566 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.273162185 |
|
|
Aug 18 05:48:51 PM PDT 24 |
Aug 18 05:48:55 PM PDT 24 |
51771915 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3925184685 |
|
|
Aug 18 05:48:28 PM PDT 24 |
Aug 18 05:48:29 PM PDT 24 |
39248457 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1178285958 |
|
|
Aug 18 05:48:30 PM PDT 24 |
Aug 18 05:48:32 PM PDT 24 |
35201388 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.675469747 |
|
|
Aug 18 05:48:35 PM PDT 24 |
Aug 18 05:48:39 PM PDT 24 |
717663542 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.598879778 |
|
|
Aug 18 05:48:36 PM PDT 24 |
Aug 18 05:48:39 PM PDT 24 |
623471820 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1413079244 |
|
|
Aug 18 05:48:57 PM PDT 24 |
Aug 18 05:49:00 PM PDT 24 |
359796838 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2191566613 |
|
|
Aug 18 05:48:38 PM PDT 24 |
Aug 18 05:48:39 PM PDT 24 |
56026590 ps |
| T998 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4203599729 |
|
|
Aug 18 05:48:53 PM PDT 24 |
Aug 18 05:48:54 PM PDT 24 |
22972571 ps |
| T999 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2961196239 |
|
|
Aug 18 05:48:36 PM PDT 24 |
Aug 18 05:48:37 PM PDT 24 |
22994087 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2809760156 |
|
|
Aug 18 05:48:26 PM PDT 24 |
Aug 18 05:48:30 PM PDT 24 |
1246808329 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4038363978 |
|
|
Aug 18 05:48:32 PM PDT 24 |
Aug 18 05:48:36 PM PDT 24 |
116268739 ps |
| T1002 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3844398567 |
|
|
Aug 18 05:48:48 PM PDT 24 |
Aug 18 05:48:51 PM PDT 24 |
360464881 ps |
| T99 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1999359501 |
|
|
Aug 18 05:48:56 PM PDT 24 |
Aug 18 05:49:27 PM PDT 24 |
16745492902 ps |
| T1003 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3439113455 |
|
|
Aug 18 05:49:05 PM PDT 24 |
Aug 18 05:49:56 PM PDT 24 |
7416230370 ps |
| T1004 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4062432788 |
|
|
Aug 18 05:48:44 PM PDT 24 |
Aug 18 05:48:44 PM PDT 24 |
41655428 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4169035541 |
|
|
Aug 18 05:48:46 PM PDT 24 |
Aug 18 05:48:48 PM PDT 24 |
58154813 ps |
| T1005 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3352514808 |
|
|
Aug 18 05:48:56 PM PDT 24 |
Aug 18 05:48:58 PM PDT 24 |
365306976 ps |
| T1006 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2735764124 |
|
|
Aug 18 05:48:37 PM PDT 24 |
Aug 18 05:48:38 PM PDT 24 |
47955519 ps |