Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	358507630	1			T1	117964		T2	129362		T3	372722
instr_valid_dis	307919561	1			T1	117964		T2	129362		T3	353528
instr_en	37076821	1			T3	19194		T9	23868		T10	283130

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13394004	1			T3	148402		T10	17264		T42	99350
sram_ifetch_valid_disable	311443898	1			T1	117964		T2	129362		T3	112680
sram_ifetch_enable	33669728	1			T3	111640		T9	4676		T10	7886

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	358507630	1			T1	117964		T2	129362		T3	372722
hw_debug_en_valid_off	311092214	1			T1	117964		T2	129362		T3	207310
hw_debug_en_on	35177336	1			T3	116280		T9	18620		T10	155454

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	311443898	1			T1	117964		T2	129362		T3	112680
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	290604429	1			T1	117964		T2	129362		T3	112680
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	15836795	1			T9	19916		T10	257980		T42	14944
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5364516	1			T3	56272		T10	17264		T42	38732
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1970548	1			T3	56272		T45	39930		T46	42206
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2893968	1			T10	17264		T72	46964		T121	100
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6010408	1			T3	66190		T42	42770		T45	16530
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3576910	1			T3	66190		T45	16530		T46	15094
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1877312	1			T21	42268		T143	108572		T144	66636
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	15805484	1			T3	20170		T9	18620		T10	150732
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6091154	1			T3	20170		T10	90		T46	79112
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7980448	1			T9	18620		T10	150642		T72	112052

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	15552102	1			T3	19194		T9	3952		T10	7886
lc_exec_en	13361444	1			T3	29920		T10	4722		T42	48064
valid_exec_dis	300356622	1			T1	117964		T2	129362		T3	181026
invalid_exec_dis	47063732	1			T3	260042		T9	4676		T10	25150