Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	148874465	1			T1	589824		T2	3339		T3	77534
triple_byte_access	2796967	1			T2	7241		T3	1534		T4	17
halfword_access	4286985	1			T2	13475		T3	2353		T4	31
byte_access	6000233	1			T2	25567		T3	3079		T4	41
zero_access	1816164	1			T2	15059		T3	781		T4	11

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81825995

1

T1

294912

T2

32171

T3

47481

auto[1]

81948819

1

T1

294912

T2

32510

T3

37800

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	74231365	1			T1	294912		T2	258		T3	43095
auto[0]	triple_byte_access	1335109	1			T2	1362		T3	883		T4	6
auto[0]	halfword_access	2097416	1			T2	4650		T3	1352		T4	18
auto[0]	byte_access	3075928	1			T2	13790		T3	1722		T4	19
auto[0]	zero_access	1086177	1			T2	12111		T3	429		T4	6
auto[1]	word_access	74643100	1			T1	294912		T2	3081		T3	34439
auto[1]	triple_byte_access	1461858	1			T2	5879		T3	651		T4	11
auto[1]	halfword_access	2189569	1			T2	8825		T3	1001		T4	13
auto[1]	byte_access	2924305	1			T2	11777		T3	1357		T4	22
auto[1]	zero_access	729987	1			T2	2948		T3	352		T4	5