Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	350175378	1			T1	4600		T2	16622		T3	17404
instr_valid_dis	312823995	1			T1	4600		T2	16622		T3	17404
instr_en	29025264	1			T26	23162		T36	111020		T142	82718

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10619518	1			T36	98684		T18	93360		T40	47170
sram_ifetch_valid_disable	314253812	1			T1	4600		T2	16622		T3	17404
sram_ifetch_enable	25302048	1			T26	53478		T36	41594		T18	82042

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	350175378	1			T1	4600		T2	16622		T3	17404
hw_debug_en_valid_off	303542626	1			T1	4600		T2	16622		T3	17404
hw_debug_en_on	26533125	1			T26	53544		T36	52752		T18	101868

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	314253812	1			T1	4600		T2	16622		T3	17404
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	295838845	1			T1	4600		T2	16622		T3	17404
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	14443550	1			T26	19806		T36	33666		T142	45624
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3267008	1			T18	71204		T40	7958		T22	10390
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1644690	1			T18	71204		T40	7958		T19	20072
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1248794	1			T22	10390		T150	1028		T144	13782
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3957710	1			T36	1796		T18	12422		T40	31976
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1555768	1			T36	1796		T18	12422		T40	31976
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1636314	1			T22	101044		T143	62304		T150	56920
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13400343	1			T26	66		T36	20370		T18	60520
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	7919950	1			T26	66		T18	60520		T40	19470
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4348159	1			T140	8408		T22	46326		T141	15110

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10632436	1			T26	3356		T142	37094		T22	71846
lc_exec_en	9175072	1			T26	53478		T36	30586		T18	28926
valid_exec_dis	301682390	1			T1	4600		T2	16622		T3	17404
invalid_exec_dis	35921566	1			T26	53478		T36	140278		T18	175402