Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.19 94.27 99.72 100.00 96.03 99.12 97.26


Total tests in report: 1037
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
69.82 69.82 92.23 92.23 67.30 67.30 83.71 83.71 33.33 33.33 81.52 81.52 93.57 93.57 37.11 37.11 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3370471748
82.07 12.25 95.18 2.94 81.52 14.22 95.94 12.22 47.62 14.29 86.73 5.21 95.32 1.75 72.21 35.10 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3557610783
90.88 8.81 98.28 3.11 82.46 0.95 95.94 0.00 100.00 52.38 90.76 4.03 96.35 1.02 72.39 0.18 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2180087125
92.53 1.64 98.53 0.25 85.66 3.20 96.07 0.14 100.00 0.00 92.65 1.90 96.35 0.00 78.43 6.03 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1096617057
93.87 1.34 98.53 0.00 87.44 1.78 97.73 1.65 100.00 0.00 93.84 1.18 96.35 0.00 83.18 4.75 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1863643854
94.85 0.98 98.86 0.33 89.81 2.37 98.76 1.03 100.00 0.00 95.50 1.66 96.93 0.58 84.10 0.91 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3130299376
95.61 0.76 98.86 0.00 90.17 0.36 98.76 0.00 100.00 0.00 95.50 0.00 96.93 0.00 89.03 4.94 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2731794992
96.22 0.61 99.10 0.25 90.17 0.00 98.76 0.00 100.00 0.00 95.73 0.24 97.08 0.15 92.69 3.66 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.221466610
96.48 0.26 99.10 0.00 90.17 0.00 98.76 0.00 100.00 0.00 95.73 0.00 97.08 0.00 94.52 1.83 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.4256604736
96.69 0.21 99.10 0.00 90.40 0.24 98.76 0.00 100.00 0.00 95.73 0.00 98.10 1.02 94.70 0.18 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1703520494
96.87 0.19 99.10 0.00 90.52 0.12 98.76 0.00 100.00 0.00 96.21 0.47 98.83 0.73 94.70 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3535033050
97.05 0.17 99.10 0.00 90.64 0.12 98.76 0.00 100.00 0.00 96.21 0.00 98.83 0.00 95.80 1.10 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3657731638
97.18 0.13 99.18 0.08 90.64 0.00 99.59 0.83 100.00 0.00 96.21 0.00 98.83 0.00 95.80 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1591573375
97.26 0.08 99.18 0.00 90.64 0.00 99.59 0.00 100.00 0.00 96.21 0.00 98.83 0.00 96.34 0.55 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1002747025
97.32 0.06 99.18 0.00 91.00 0.36 99.66 0.07 100.00 0.00 96.21 0.00 98.83 0.00 96.34 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.926644918
97.37 0.05 99.18 0.00 91.00 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.83 0.00 96.71 0.37 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2904119872
97.42 0.05 99.18 0.00 91.00 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.83 0.00 97.07 0.37 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.3415141200
97.47 0.05 99.18 0.00 91.00 0.00 99.72 0.07 100.00 0.00 96.21 0.00 99.12 0.29 97.07 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.288802371
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.558484986

Tests that do not contribute to grading

Name
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4101804463
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.987125864
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2886692765
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2668991462
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.510749488
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.732162435
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2154841466
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1717394529
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3587430678
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2426235819
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1275838005
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2343844230
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3993887304
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2909184945
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3035502065
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2954118337
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.960928316
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1253236333
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3535258917
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1656106296
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3926374651
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3643106009
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3536806589
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2522660348
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.417962482
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.438132510
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3224513362
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.892884335
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2639978433
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2061956753
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2867168013
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3068574253
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1831188637
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1727928853
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1660490149
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2009599082
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4051918014
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.348210320
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1033619066
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.820652906
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3813689208
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2013502206
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2438854269
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1985004628
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.745873484
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1152700310
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2854503805
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2095463114
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3388631608
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3807092861
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.277237044
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.214350158
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3591521814
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1197857321
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4060382612
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.555580898
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1050555725
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3934147444
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2585824201
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2766067410
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.945312363
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3999458803
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.378458386
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.755174370
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.702538831
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2944005001
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3009510735
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4260299579
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.812755377
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3746482679
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2434885357
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.421839185
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/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1561394209
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.240757321
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3252694342
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3237053743
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3651066237
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3312440276
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.2212694327
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4208700194
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2885041426
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2081538624
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.610625430
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3381856715
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3225493788
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2152733470
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3703086831
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2165574278
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3723558081
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2406265610
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2290678790
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.130816017
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2795540440
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.764504032
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.858888324
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1737617692
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2785509127
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.558124302
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2363334167
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2785730041
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2148332444
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.722634102
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.4285887772
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1342015085
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.1983736844
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.100982605
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2878256000
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2045409306
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1876219723
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3732531452



Total test records in report: 1037
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.43834877 Aug 21 10:19:22 AM UTC 24 Aug 21 10:19:39 AM UTC 24 719390000 ps
T2 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3109965565 Aug 21 10:19:57 AM UTC 24 Aug 21 10:20:30 AM UTC 24 1764959173 ps
T3 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3466528998 Aug 21 10:20:33 AM UTC 24 Aug 21 10:21:47 AM UTC 24 3122042167 ps
T4 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3370471748 Aug 21 10:21:04 AM UTC 24 Aug 21 10:21:52 AM UTC 24 7691368806 ps
T9 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1591573375 Aug 21 10:21:48 AM UTC 24 Aug 21 10:22:08 AM UTC 24 361513271 ps
T10 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2532201394 Aug 21 10:20:58 AM UTC 24 Aug 21 10:22:19 AM UTC 24 1483033844 ps
T11 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2464933298 Aug 21 10:22:28 AM UTC 24 Aug 21 10:22:34 AM UTC 24 13658579 ps
T5 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3130299376 Aug 21 10:22:27 AM UTC 24 Aug 21 10:22:35 AM UTC 24 351110069 ps
T12 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.72532110 Aug 21 10:19:44 AM UTC 24 Aug 21 10:22:42 AM UTC 24 3228107682 ps
T8 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1863643854 Aug 21 10:22:44 AM UTC 24 Aug 21 10:23:09 AM UTC 24 3689520210 ps
T23 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3557610783 Aug 21 10:22:10 AM UTC 24 Aug 21 10:23:12 AM UTC 24 1560899316 ps
T31 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.1360036549 Aug 21 10:23:05 AM UTC 24 Aug 21 10:23:39 AM UTC 24 710505239 ps
T32 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.57137773 Aug 21 10:22:35 AM UTC 24 Aug 21 10:24:07 AM UTC 24 8302922442 ps
T33 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3663677823 Aug 21 10:21:54 AM UTC 24 Aug 21 10:24:08 AM UTC 24 6566014494 ps
T27 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.735022734 Aug 21 10:24:08 AM UTC 24 Aug 21 10:24:15 AM UTC 24 1424481085 ps
T34 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.533474484 Aug 21 10:23:09 AM UTC 24 Aug 21 10:24:37 AM UTC 24 820178123 ps
T6 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.2586238677 Aug 21 10:23:15 AM UTC 24 Aug 21 10:24:54 AM UTC 24 42587827045 ps
T13 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.926644918 Aug 21 10:24:59 AM UTC 24 Aug 21 10:25:05 AM UTC 24 21005341 ps
T16 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2435626628 Aug 21 10:24:56 AM UTC 24 Aug 21 10:25:05 AM UTC 24 554401867 ps
T35 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.45282303 Aug 21 10:19:23 AM UTC 24 Aug 21 10:25:06 AM UTC 24 25250064001 ps
T24 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2995406253 Aug 21 10:24:16 AM UTC 24 Aug 21 10:25:18 AM UTC 24 5326777776 ps
T41 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1023121571 Aug 21 10:24:12 AM UTC 24 Aug 21 10:25:55 AM UTC 24 1428287229 ps
T58 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.424492471 Aug 21 10:25:55 AM UTC 24 Aug 21 10:26:13 AM UTC 24 401681674 ps
T26 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.4192049107 Aug 21 10:21:37 AM UTC 24 Aug 21 10:26:13 AM UTC 24 8456174781 ps
T59 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2509922600 Aug 21 10:25:06 AM UTC 24 Aug 21 10:26:52 AM UTC 24 1837104122 ps
T60 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.384791266 Aug 21 10:26:15 AM UTC 24 Aug 21 10:26:53 AM UTC 24 1351647847 ps
T42 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.76125179 Aug 21 10:24:08 AM UTC 24 Aug 21 10:27:23 AM UTC 24 56016338785 ps
T61 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3030764808 Aug 21 10:26:15 AM UTC 24 Aug 21 10:27:51 AM UTC 24 1628824857 ps
T62 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3450788034 Aug 21 10:22:39 AM UTC 24 Aug 21 10:27:53 AM UTC 24 5109271361 ps
T28 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.309445583 Aug 21 10:27:51 AM UTC 24 Aug 21 10:28:00 AM UTC 24 2251766597 ps
T14 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2199790126 Aug 21 10:28:19 AM UTC 24 Aug 21 10:28:20 AM UTC 24 31938648 ps
T17 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1956858111 Aug 21 10:28:18 AM UTC 24 Aug 21 10:28:24 AM UTC 24 707402069 ps
T7 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1940336858 Aug 21 10:26:53 AM UTC 24 Aug 21 10:28:39 AM UTC 24 10231091762 ps
T25 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2612144390 Aug 21 10:28:04 AM UTC 24 Aug 21 10:28:48 AM UTC 24 1146503111 ps
T109 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1795961136 Aug 21 10:25:19 AM UTC 24 Aug 21 10:29:07 AM UTC 24 3493991162 ps
T83 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1800789533 Aug 21 10:28:22 AM UTC 24 Aug 21 10:29:12 AM UTC 24 1059415206 ps
T89 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2693230945 Aug 21 10:28:02 AM UTC 24 Aug 21 10:29:21 AM UTC 24 1845950617 ps
T124 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.716577858 Aug 21 10:28:49 AM UTC 24 Aug 21 10:29:22 AM UTC 24 668492163 ps
T125 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1787151189 Aug 21 10:29:07 AM UTC 24 Aug 21 10:29:42 AM UTC 24 1019824997 ps
T126 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.588302264 Aug 21 10:25:06 AM UTC 24 Aug 21 10:29:45 AM UTC 24 20861247908 ps
T36 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.4256604736 Aug 21 10:23:40 AM UTC 24 Aug 21 10:29:56 AM UTC 24 11620462267 ps
T127 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3471178088 Aug 21 10:29:56 AM UTC 24 Aug 21 10:30:06 AM UTC 24 348550002 ps
T128 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3993893341 Aug 21 10:29:14 AM UTC 24 Aug 21 10:30:14 AM UTC 24 4369351586 ps
T70 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2965931027 Aug 21 10:30:11 AM UTC 24 Aug 21 10:30:24 AM UTC 24 332137157 ps
T29 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1035202167 Aug 21 10:30:25 AM UTC 24 Aug 21 10:30:34 AM UTC 24 544279395 ps
T43 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.189551117 Aug 21 10:21:50 AM UTC 24 Aug 21 10:30:40 AM UTC 24 82753212803 ps
T15 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.4111244543 Aug 21 10:30:35 AM UTC 24 Aug 21 10:30:43 AM UTC 24 15767799 ps
T110 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1431793551 Aug 21 10:20:32 AM UTC 24 Aug 21 10:30:50 AM UTC 24 50653107147 ps
T152 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1633871280 Aug 21 10:30:42 AM UTC 24 Aug 21 10:31:05 AM UTC 24 431982144 ps
T18 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3657731638 Aug 21 10:21:42 AM UTC 24 Aug 21 10:31:20 AM UTC 24 3626173214 ps
T37 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1933252502 Aug 21 10:26:54 AM UTC 24 Aug 21 10:31:21 AM UTC 24 2528633313 ps
T21 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3931628703 Aug 21 10:29:23 AM UTC 24 Aug 21 10:31:32 AM UTC 24 69153132292 ps
T40 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.409735878 Aug 21 10:24:05 AM UTC 24 Aug 21 10:32:26 AM UTC 24 15166484424 ps
T153 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.931407869 Aug 21 10:31:22 AM UTC 24 Aug 21 10:32:27 AM UTC 24 1555319614 ps
T90 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2575112268 Aug 21 10:30:07 AM UTC 24 Aug 21 10:32:27 AM UTC 24 17562081422 ps
T154 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.10202829 Aug 21 10:32:00 AM UTC 24 Aug 21 10:32:29 AM UTC 24 2841960076 ps
T155 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1242848348 Aug 21 10:31:33 AM UTC 24 Aug 21 10:32:33 AM UTC 24 2887978565 ps
T156 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2014264969 Aug 21 10:32:31 AM UTC 24 Aug 21 10:32:39 AM UTC 24 695651968 ps
T111 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.221466610 Aug 21 10:22:44 AM UTC 24 Aug 21 10:32:58 AM UTC 24 93006821016 ps
T112 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.2727622600 Aug 21 10:28:39 AM UTC 24 Aug 21 10:33:13 AM UTC 24 14575897044 ps
T157 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1459055794 Aug 21 10:32:27 AM UTC 24 Aug 21 10:33:21 AM UTC 24 7062594326 ps
T113 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1368092841 Aug 21 10:25:57 AM UTC 24 Aug 21 10:33:27 AM UTC 24 52608657042 ps
T30 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1278947219 Aug 21 10:33:22 AM UTC 24 Aug 21 10:33:29 AM UTC 24 903923541 ps
T158 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2271532501 Aug 21 10:33:28 AM UTC 24 Aug 21 10:33:31 AM UTC 24 14107372 ps
T159 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2123790488 Aug 21 10:30:44 AM UTC 24 Aug 21 10:33:48 AM UTC 24 1592394442 ps
T160 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.32018427 Aug 21 10:33:30 AM UTC 24 Aug 21 10:34:01 AM UTC 24 2067631400 ps
T47 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1723899715 Aug 21 10:27:53 AM UTC 24 Aug 21 10:34:06 AM UTC 24 276568669733 ps
T44 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2180087125 Aug 21 10:32:39 AM UTC 24 Aug 21 10:34:20 AM UTC 24 8775605493 ps
T161 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1685064924 Aug 21 10:34:02 AM UTC 24 Aug 21 10:34:35 AM UTC 24 1272809517 ps
T142 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.3456636482 Aug 21 10:29:43 AM UTC 24 Aug 21 10:34:40 AM UTC 24 7837761497 ps
T140 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.1327183522 Aug 21 10:32:28 AM UTC 24 Aug 21 10:34:45 AM UTC 24 2360361059 ps
T51 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1564237080 Aug 21 10:32:59 AM UTC 24 Aug 21 10:34:48 AM UTC 24 22149181213 ps
T162 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3885652684 Aug 21 10:34:41 AM UTC 24 Aug 21 10:35:04 AM UTC 24 2152551887 ps
T163 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1410287872 Aug 21 10:34:21 AM UTC 24 Aug 21 10:35:17 AM UTC 24 2830899072 ps
T164 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1645945077 Aug 21 10:35:05 AM UTC 24 Aug 21 10:35:24 AM UTC 24 689613624 ps
T114 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.307923811 Aug 21 10:31:23 AM UTC 24 Aug 21 10:35:30 AM UTC 24 29653301710 ps
T52 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3785668699 Aug 21 10:29:57 AM UTC 24 Aug 21 10:35:43 AM UTC 24 52485506004 ps
T165 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.4053494709 Aug 21 10:34:37 AM UTC 24 Aug 21 10:36:14 AM UTC 24 809315798 ps
T166 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.4182677782 Aug 21 10:36:16 AM UTC 24 Aug 21 10:36:31 AM UTC 24 28261000 ps
T63 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.894033053 Aug 21 10:35:33 AM UTC 24 Aug 21 10:36:36 AM UTC 24 2399789238 ps
T167 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3242340039 Aug 21 10:28:57 AM UTC 24 Aug 21 10:37:01 AM UTC 24 119913731873 ps
T168 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2363223675 Aug 21 10:31:06 AM UTC 24 Aug 21 10:37:05 AM UTC 24 4014836401 ps
T169 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.4185063126 Aug 21 10:22:36 AM UTC 24 Aug 21 10:37:13 AM UTC 24 11765105364 ps
T38 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.931686315 Aug 21 10:21:17 AM UTC 24 Aug 21 10:37:22 AM UTC 24 10377047237 ps
T22 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1096617057 Aug 21 10:24:39 AM UTC 24 Aug 21 10:37:33 AM UTC 24 297891901513 ps
T170 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2243484427 Aug 21 10:37:14 AM UTC 24 Aug 21 10:37:52 AM UTC 24 1815434692 ps
T53 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1665631958 Aug 21 10:32:34 AM UTC 24 Aug 21 10:38:05 AM UTC 24 14256534638 ps
T171 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.2823419559 Aug 21 10:36:33 AM UTC 24 Aug 21 10:38:10 AM UTC 24 3309777296 ps
T172 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.2157001407 Aug 21 10:37:32 AM UTC 24 Aug 21 10:38:23 AM UTC 24 760819152 ps
T173 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3446269309 Aug 21 10:38:23 AM UTC 24 Aug 21 10:38:31 AM UTC 24 2109201256 ps
T174 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1333689224 Aug 21 10:37:35 AM UTC 24 Aug 21 10:39:09 AM UTC 24 3255930894 ps
T175 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.915341911 Aug 21 10:37:53 AM UTC 24 Aug 21 10:39:15 AM UTC 24 11986851060 ps
T45 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.3688338756 Aug 21 10:35:26 AM UTC 24 Aug 21 10:39:34 AM UTC 24 5254720821 ps
T176 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1720272721 Aug 21 10:39:34 AM UTC 24 Aug 21 10:39:37 AM UTC 24 86824457 ps
T177 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1676666010 Aug 21 10:33:52 AM UTC 24 Aug 21 10:39:40 AM UTC 24 26486263710 ps
T39 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.454451121 Aug 21 10:32:28 AM UTC 24 Aug 21 10:40:25 AM UTC 24 6632281881 ps
T178 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.999664257 Aug 21 10:39:38 AM UTC 24 Aug 21 10:40:26 AM UTC 24 2010315019 ps
T46 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2341220999 Aug 21 10:38:32 AM UTC 24 Aug 21 10:40:33 AM UTC 24 8382546589 ps
T71 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.864804334 Aug 21 10:39:10 AM UTC 24 Aug 21 10:40:40 AM UTC 24 1535885221 ps
T179 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.88515215 Aug 21 10:35:18 AM UTC 24 Aug 21 10:40:55 AM UTC 24 81292885882 ps
T146 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.4135785764 Aug 21 10:32:30 AM UTC 24 Aug 21 10:40:56 AM UTC 24 2512297322 ps
T180 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1203497113 Aug 21 10:40:35 AM UTC 24 Aug 21 10:40:59 AM UTC 24 7079976432 ps
T181 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1540505490 Aug 21 10:37:07 AM UTC 24 Aug 21 10:41:05 AM UTC 24 2604274749 ps
T182 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.240757321 Aug 21 10:40:57 AM UTC 24 Aug 21 10:41:43 AM UTC 24 9079289025 ps
T183 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2887134017 Aug 21 10:40:56 AM UTC 24 Aug 21 10:41:50 AM UTC 24 743687830 ps
T184 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.384889410 Aug 21 10:41:51 AM UTC 24 Aug 21 10:42:04 AM UTC 24 1203023681 ps
T149 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.379809054 Aug 21 10:34:07 AM UTC 24 Aug 21 10:42:05 AM UTC 24 54130452783 ps
T151 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3153321528 Aug 21 10:41:00 AM UTC 24 Aug 21 10:42:19 AM UTC 24 25711012762 ps
T72 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.395151358 Aug 21 10:42:15 AM UTC 24 Aug 21 10:42:51 AM UTC 24 711865101 ps
T185 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.154006157 Aug 21 10:42:51 AM UTC 24 Aug 21 10:42:53 AM UTC 24 26886537 ps
T186 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2165574278 Aug 21 10:42:54 AM UTC 24 Aug 21 10:43:28 AM UTC 24 7050372872 ps
T141 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.794925156 Aug 21 10:34:49 AM UTC 24 Aug 21 10:43:28 AM UTC 24 6437615827 ps
T187 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2725594511 Aug 21 10:33:32 AM UTC 24 Aug 21 10:43:30 AM UTC 24 7881563742 ps
T188 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3290240670 Aug 21 10:38:30 AM UTC 24 Aug 21 10:43:35 AM UTC 24 5904491386 ps
T189 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1561394209 Aug 21 10:40:28 AM UTC 24 Aug 21 10:44:00 AM UTC 24 8372415311 ps
T102 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1048868605 Aug 21 10:42:06 AM UTC 24 Aug 21 10:44:03 AM UTC 24 10976138776 ps
T190 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1426589598 Aug 21 10:28:25 AM UTC 24 Aug 21 10:44:06 AM UTC 24 9611063882 ps
T191 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3381856715 Aug 21 10:43:37 AM UTC 24 Aug 21 10:44:07 AM UTC 24 2357954533 ps
T192 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.130816017 Aug 21 10:44:07 AM UTC 24 Aug 21 10:44:26 AM UTC 24 1383082834 ps
T193 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4208700194 Aug 21 10:44:04 AM UTC 24 Aug 21 10:44:27 AM UTC 24 2782216164 ps
T194 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2601966723 Aug 21 10:37:24 AM UTC 24 Aug 21 10:45:00 AM UTC 24 67464415731 ps
T19 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.443753925 Aug 21 10:38:15 AM UTC 24 Aug 21 10:45:46 AM UTC 24 11191701097 ps
T195 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2152733470 Aug 21 10:45:48 AM UTC 24 Aug 21 10:45:56 AM UTC 24 1199791586 ps
T196 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.365729796 Aug 21 10:23:35 AM UTC 24 Aug 21 10:46:00 AM UTC 24 108028211677 ps
T143 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.4254358450 Aug 21 10:26:55 AM UTC 24 Aug 21 10:46:23 AM UTC 24 19968289722 ps
T197 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.2212694327 Aug 21 10:44:08 AM UTC 24 Aug 21 10:46:32 AM UTC 24 24642082845 ps
T150 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4210079061 Aug 21 10:29:46 AM UTC 24 Aug 21 10:46:44 AM UTC 24 38839928528 ps
T73 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2406265610 Aug 21 10:46:24 AM UTC 24 Aug 21 10:46:46 AM UTC 24 1404934481 ps
T198 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3237053743 Aug 21 10:46:45 AM UTC 24 Aug 21 10:46:48 AM UTC 24 23990225 ps
T20 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.865535912 Aug 21 10:27:24 AM UTC 24 Aug 21 10:46:53 AM UTC 24 17173577116 ps
T199 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.100982605 Aug 21 10:46:47 AM UTC 24 Aug 21 10:46:58 AM UTC 24 770789725 ps
T200 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3157424969 Aug 21 10:29:24 AM UTC 24 Aug 21 10:46:59 AM UTC 24 63250847921 ps
T201 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2885041426 Aug 21 10:46:00 AM UTC 24 Aug 21 10:47:15 AM UTC 24 4025238679 ps
T202 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.722634102 Aug 21 10:47:00 AM UTC 24 Aug 21 10:47:27 AM UTC 24 3466866209 ps
T203 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3732531452 Aug 21 10:47:33 AM UTC 24 Aug 21 10:48:16 AM UTC 24 735000760 ps
T204 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.304972922 Aug 21 10:36:37 AM UTC 24 Aug 21 10:48:21 AM UTC 24 21474167917 ps
T205 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2732341021 Aug 21 10:40:42 AM UTC 24 Aug 21 10:48:35 AM UTC 24 22337661498 ps
T206 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.558124302 Aug 21 10:47:28 AM UTC 24 Aug 21 10:48:57 AM UTC 24 802465285 ps
T207 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2304588954 Aug 21 10:42:06 AM UTC 24 Aug 21 10:48:59 AM UTC 24 5258279536 ps
T208 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1342015085 Aug 21 10:49:00 AM UTC 24 Aug 21 10:49:07 AM UTC 24 351582756 ps
T209 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2290678790 Aug 21 10:43:31 AM UTC 24 Aug 21 10:49:22 AM UTC 24 4471390976 ps
T210 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2785509127 Aug 21 10:48:16 AM UTC 24 Aug 21 10:49:50 AM UTC 24 24558431761 ps
T144 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.597133372 Aug 21 10:34:54 AM UTC 24 Aug 21 10:50:13 AM UTC 24 50890362455 ps
T48 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2045409306 Aug 21 10:49:51 AM UTC 24 Aug 21 10:50:20 AM UTC 24 829169302 ps
T211 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.764504032 Aug 21 10:50:20 AM UTC 24 Aug 21 10:50:24 AM UTC 24 24194391 ps
T212 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2363334167 Aug 21 10:49:23 AM UTC 24 Aug 21 10:50:46 AM UTC 24 1042345592 ps
T213 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3225493788 Aug 21 10:44:01 AM UTC 24 Aug 21 10:51:02 AM UTC 24 30994430519 ps
T214 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.3760972754 Aug 21 10:50:24 AM UTC 24 Aug 21 10:51:58 AM UTC 24 3224739251 ps
T215 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.53945031 Aug 21 10:41:07 AM UTC 24 Aug 21 10:52:18 AM UTC 24 7783234780 ps
T216 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2081538624 Aug 21 10:45:57 AM UTC 24 Aug 21 10:52:29 AM UTC 24 21112237053 ps
T217 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.497949037 Aug 21 10:51:59 AM UTC 24 Aug 21 10:52:42 AM UTC 24 3656362679 ps
T147 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.255195611 Aug 21 10:41:45 AM UTC 24 Aug 21 10:53:43 AM UTC 24 7596897656 ps
T218 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.327569563 Aug 21 10:25:08 AM UTC 24 Aug 21 10:53:47 AM UTC 24 62500093338 ps
T219 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3671181537 Aug 21 10:52:43 AM UTC 24 Aug 21 10:53:54 AM UTC 24 3254693784 ps
T220 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1800076656 Aug 21 10:52:31 AM UTC 24 Aug 21 10:54:00 AM UTC 24 808063254 ps
T221 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.107649684 Aug 21 10:53:55 AM UTC 24 Aug 21 10:54:02 AM UTC 24 1406932068 ps
T222 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1876219723 Aug 21 10:46:59 AM UTC 24 Aug 21 10:54:12 AM UTC 24 19833172735 ps
T223 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.4221410420 Aug 21 10:33:49 AM UTC 24 Aug 21 10:54:17 AM UTC 24 70130402289 ps
T224 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1257560935 Aug 21 10:54:13 AM UTC 24 Aug 21 10:54:35 AM UTC 24 1452762505 ps
T225 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1715963525 Aug 21 10:54:35 AM UTC 24 Aug 21 10:54:38 AM UTC 24 22571847 ps
T226 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2785730041 Aug 21 10:49:08 AM UTC 24 Aug 21 10:55:00 AM UTC 24 17134646184 ps
T227 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.1061753027 Aug 21 10:54:38 AM UTC 24 Aug 21 10:55:24 AM UTC 24 11177462342 ps
T228 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3483731724 Aug 21 10:39:41 AM UTC 24 Aug 21 10:55:40 AM UTC 24 37858724708 ps
T229 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3342103638 Aug 21 10:53:21 AM UTC 24 Aug 21 10:55:42 AM UTC 24 14165115169 ps
T54 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2733964981 Aug 21 10:54:03 AM UTC 24 Aug 21 10:55:46 AM UTC 24 2637455296 ps
T230 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.1983736844 Aug 21 10:48:59 AM UTC 24 Aug 21 10:55:53 AM UTC 24 6074245538 ps
T231 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.1655420860 Aug 21 10:22:36 AM UTC 24 Aug 21 10:55:56 AM UTC 24 159731607137 ps
T232 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.656019282 Aug 21 10:55:44 AM UTC 24 Aug 21 10:55:57 AM UTC 24 1773871392 ps
T233 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1737617692 Aug 21 10:48:36 AM UTC 24 Aug 21 10:56:04 AM UTC 24 9493344922 ps
T145 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3855884697 Aug 21 10:38:12 AM UTC 24 Aug 21 10:56:08 AM UTC 24 190178452057 ps
T234 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.3110778828 Aug 21 10:55:54 AM UTC 24 Aug 21 10:56:09 AM UTC 24 2707357829 ps
T235 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2148332444 Aug 21 10:46:48 AM UTC 24 Aug 21 10:56:13 AM UTC 24 41144087609 ps
T236 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1600396861 Aug 21 10:56:13 AM UTC 24 Aug 21 10:56:23 AM UTC 24 693726431 ps
T237 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2832892273 Aug 21 10:50:46 AM UTC 24 Aug 21 10:56:32 AM UTC 24 6164193762 ps
T238 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1955446232 Aug 21 10:55:57 AM UTC 24 Aug 21 10:56:38 AM UTC 24 763289357 ps
T239 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3461426138 Aug 21 10:19:39 AM UTC 24 Aug 21 10:56:47 AM UTC 24 469382996481 ps
T240 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.746954132 Aug 21 10:51:22 AM UTC 24 Aug 21 10:57:24 AM UTC 24 10289678968 ps
T241 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2415953071 Aug 21 10:57:26 AM UTC 24 Aug 21 10:57:28 AM UTC 24 13070186 ps
T242 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.504692823 Aug 21 10:57:29 AM UTC 24 Aug 21 10:57:44 AM UTC 24 501349266 ps
T148 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.210188011 Aug 21 10:35:45 AM UTC 24 Aug 21 10:57:52 AM UTC 24 67322422866 ps
T243 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3993681502 Aug 21 10:55:58 AM UTC 24 Aug 21 10:58:13 AM UTC 24 30541564183 ps
T55 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4141800475 Aug 21 10:56:38 AM UTC 24 Aug 21 10:58:21 AM UTC 24 10875354366 ps
T244 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.4285887772 Aug 21 10:47:16 AM UTC 24 Aug 21 10:58:24 AM UTC 24 23108820707 ps
T245 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.3046817899 Aug 21 10:53:47 AM UTC 24 Aug 21 10:58:39 AM UTC 24 5792557234 ps
T246 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.4272435581 Aug 21 10:58:22 AM UTC 24 Aug 21 10:58:52 AM UTC 24 1246549338 ps
T247 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.296532354 Aug 21 10:56:24 AM UTC 24 Aug 21 10:58:55 AM UTC 24 4116904517 ps
T248 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1064705256 Aug 21 10:34:46 AM UTC 24 Aug 21 10:59:03 AM UTC 24 59989734578 ps
T249 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3766746382 Aug 21 10:58:53 AM UTC 24 Aug 21 10:59:21 AM UTC 24 2818225974 ps
T250 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.16114817 Aug 21 10:58:56 AM UTC 24 Aug 21 10:59:25 AM UTC 24 3581834790 ps
T251 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2779700387 Aug 21 10:54:01 AM UTC 24 Aug 21 10:59:29 AM UTC 24 9908563555 ps
T252 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1730957865 Aug 21 10:59:30 AM UTC 24 Aug 21 10:59:35 AM UTC 24 691001542 ps
T56 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.380708616 Aug 21 10:56:33 AM UTC 24 Aug 21 10:59:35 AM UTC 24 8370775290 ps
T253 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3703086831 Aug 21 10:45:00 AM UTC 24 Aug 21 10:59:48 AM UTC 24 26771061777 ps
T254 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.610625430 Aug 21 10:43:29 AM UTC 24 Aug 21 10:59:58 AM UTC 24 20580099344 ps
T255 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3215647834 Aug 21 10:59:59 AM UTC 24 Aug 21 11:00:01 AM UTC 24 40995629 ps
T256 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3252694342 Aug 21 10:44:26 AM UTC 24 Aug 21 11:00:06 AM UTC 24 14892346158 ps
T119 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4085663950 Aug 21 10:59:36 AM UTC 24 Aug 21 11:00:09 AM UTC 24 1441779563 ps
T257 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3610916258 Aug 21 10:41:42 AM UTC 24 Aug 21 11:00:15 AM UTC 24 132148665867 ps
T258 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2958971515 Aug 21 10:58:40 AM UTC 24 Aug 21 11:00:17 AM UTC 24 3065799776 ps
T259 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2427578985 Aug 21 10:38:06 AM UTC 24 Aug 21 11:00:22 AM UTC 24 18386670790 ps
T260 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.106716694 Aug 21 11:00:02 AM UTC 24 Aug 21 11:00:36 AM UTC 24 738959809 ps
T261 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1745960354 Aug 21 10:55:41 AM UTC 24 Aug 21 11:00:37 AM UTC 24 14087369821 ps
T262 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3088557786 Aug 21 11:00:18 AM UTC 24 Aug 21 11:00:48 AM UTC 24 1187096296 ps
T263 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3312440276 Aug 21 10:44:27 AM UTC 24 Aug 21 11:01:05 AM UTC 24 101283820770 ps
T264 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2718506445 Aug 21 10:55:48 AM UTC 24 Aug 21 11:01:16 AM UTC 24 43525160105 ps
T265 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2795540440 Aug 21 10:48:21 AM UTC 24 Aug 21 11:01:17 AM UTC 24 46347050658 ps
T266 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2234804486 Aug 21 11:00:36 AM UTC 24 Aug 21 11:01:27 AM UTC 24 723998878 ps
T267 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1766886313 Aug 21 10:59:36 AM UTC 24 Aug 21 11:01:28 AM UTC 24 2749326459 ps
T268 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3400948198 Aug 21 11:01:29 AM UTC 24 Aug 21 11:01:38 AM UTC 24 353170926 ps
T269 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1947527157 Aug 21 11:00:38 AM UTC 24 Aug 21 11:01:47 AM UTC 24 762139681 ps
T120 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.899148052 Aug 21 11:01:47 AM UTC 24 Aug 21 11:01:54 AM UTC 24 176263137 ps
T270 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3818877234 Aug 21 10:59:05 AM UTC 24 Aug 21 11:01:58 AM UTC 24 2824207180 ps
T271 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1422179207 Aug 21 11:01:58 AM UTC 24 Aug 21 11:02:01 AM UTC 24 44069184 ps
T272 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1949854232 Aug 21 10:55:01 AM UTC 24 Aug 21 11:02:04 AM UTC 24 39834648223 ps
T273 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1613117692 Aug 21 11:00:49 AM UTC 24 Aug 21 11:02:26 AM UTC 24 39940990138 ps
T274 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.4177213376 Aug 21 11:02:02 AM UTC 24 Aug 21 11:02:29 AM UTC 24 2740874822 ps
T275 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3037289445 Aug 21 10:52:19 AM UTC 24 Aug 21 11:02:30 AM UTC 24 83871171119 ps
T276 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.3124670850 Aug 21 11:01:18 AM UTC 24 Aug 21 11:02:43 AM UTC 24 1334717893 ps
T277 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1030501702 Aug 21 11:02:31 AM UTC 24 Aug 21 11:03:08 AM UTC 24 970008786 ps
T278 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1731061194 Aug 21 11:00:16 AM UTC 24 Aug 21 11:03:15 AM UTC 24 11400487598 ps
T279 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.304124223 Aug 21 10:56:10 AM UTC 24 Aug 21 11:03:29 AM UTC 24 6867286961 ps
T280 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1911739788 Aug 21 10:33:15 AM UTC 24 Aug 21 11:03:36 AM UTC 24 45670524253 ps
T281 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.924097082 Aug 21 10:58:14 AM UTC 24 Aug 21 11:03:58 AM UTC 24 7822308310 ps
T57 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.471057134 Aug 21 11:01:39 AM UTC 24 Aug 21 11:03:58 AM UTC 24 20427792190 ps
T282 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.48448349 Aug 21 11:03:08 AM UTC 24 Aug 21 11:04:03 AM UTC 24 1499302662 ps
T283 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.736192126 Aug 21 11:04:04 AM UTC 24 Aug 21 11:04:11 AM UTC 24 1166556278 ps
T284 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1674308120 Aug 21 11:03:15 AM UTC 24 Aug 21 11:04:26 AM UTC 24 3257554973 ps
T285 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.1073018578 Aug 21 10:30:51 AM UTC 24 Aug 21 11:04:53 AM UTC 24 76858883326 ps
T286 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.708033560 Aug 21 11:04:54 AM UTC 24 Aug 21 11:05:26 AM UTC 24 1225545821 ps
T287 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2066167464 Aug 21 10:58:25 AM UTC 24 Aug 21 11:05:30 AM UTC 24 6261761000 ps
T288 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3142208102 Aug 21 11:05:30 AM UTC 24 Aug 21 11:05:33 AM UTC 24 17153709 ps
T289 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.3465251314 Aug 21 11:05:32 AM UTC 24 Aug 21 11:05:41 AM UTC 24 440927205 ps
T290 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.453039722 Aug 21 11:01:18 AM UTC 24 Aug 21 11:05:44 AM UTC 24 47917585913 ps
T291 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2577089606 Aug 21 11:02:30 AM UTC 24 Aug 21 11:05:49 AM UTC 24 16990198064 ps
T292 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.1549946453 Aug 21 10:53:27 AM UTC 24 Aug 21 11:05:57 AM UTC 24 13809544897 ps
T293 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3671432847 Aug 21 11:03:30 AM UTC 24 Aug 21 11:06:31 AM UTC 24 62473274138 ps
T294 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.2731960146 Aug 21 11:05:50 AM UTC 24 Aug 21 11:06:39 AM UTC 24 4179972648 ps
T295 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.673744318 Aug 21 11:03:59 AM UTC 24 Aug 21 11:06:40 AM UTC 24 7708840104 ps
T296 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.266691550 Aug 21 10:59:36 AM UTC 24 Aug 21 11:06:45 AM UTC 24 153447983577 ps
T297 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3675406330 Aug 21 10:56:05 AM UTC 24 Aug 21 11:06:46 AM UTC 24 10802004518 ps
T298 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.4008877120 Aug 21 11:01:29 AM UTC 24 Aug 21 11:06:48 AM UTC 24 51269966759 ps
T299 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2366902236 Aug 21 11:06:49 AM UTC 24 Aug 21 11:06:56 AM UTC 24 705740594 ps
T300 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3300439309 Aug 21 11:06:39 AM UTC 24 Aug 21 11:06:57 AM UTC 24 3868905813 ps
T301 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1699681983 Aug 21 11:06:41 AM UTC 24 Aug 21 11:07:04 AM UTC 24 6628794182 ps
T302 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.1513857055 Aug 21 11:04:12 AM UTC 24 Aug 21 11:07:05 AM UTC 24 4116420845 ps
T303 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2960430750 Aug 21 11:06:32 AM UTC 24 Aug 21 11:07:05 AM UTC 24 746085687 ps
T304 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2895620544 Aug 21 11:07:06 AM UTC 24 Aug 21 11:07:09 AM UTC 24 69067043 ps
T305 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.3402624472 Aug 21 10:37:03 AM UTC 24 Aug 21 11:07:12 AM UTC 24 645340139025 ps
T306 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.824554698 Aug 21 11:04:27 AM UTC 24 Aug 21 11:07:25 AM UTC 24 20533078583 ps
T307 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3564290667 Aug 21 11:00:23 AM UTC 24 Aug 21 11:07:32 AM UTC 24 15662510525 ps
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