Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	375484998	1			T1	6206		T4	1292		T5	1006
instr_valid_dis	329902820	1			T1	6206		T4	1292		T5	1006
instr_en	34961023	1			T28	37148		T21	238510		T131	35540

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13332088	1			T27	14506		T20	41320		T40	31180
sram_ifetch_valid_disable	333444948	1			T1	6206		T4	1292		T5	1006
sram_ifetch_enable	28707962	1			T28	90		T20	36174		T40	84854

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	375484998	1			T1	6206		T4	1292		T5	1006
hw_debug_en_valid_off	326925576	1			T1	6206		T4	1292		T5	1006
hw_debug_en_on	33171956	1			T27	14042		T28	37148		T20	5324

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	333444948	1			T1	6206		T4	1292		T5	1006
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	312524104	1			T1	6206		T4	1292		T5	1006
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	15260441	1			T28	37148		T21	119278		T131	35540
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4242524	1			T20	35996		T40	11180		T149	14902
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1588880	1			T20	35996		T149	14902		T22	28148
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1857006	1			T148	63488		T160	5300		T161	42
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4642804	1			T27	14042		T20	5324		T63	19092
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1808206	1			T27	14042		T20	5324		T63	19092
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2530748	1			T21	19104		T149	33624		T150	58278
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14236400	1			T28	37148		T40	39732		T21	18464
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5207410	1			T131	19776		T149	26200		T148	19590
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7740856	1			T28	37148		T21	18464		T133	50

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12097392	1			T21	69262		T149	59326		T148	53776
lc_exec_en	14292752	1			T21	12776		T131	14362		T133	2064
valid_exec_dis	325826620	1			T1	6206		T4	1292		T5	1006
invalid_exec_dis	42040050	1			T27	14506		T28	90		T20	77494