Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1037
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.58 62.58 89.86 89.86 65.40 65.40 67.42 67.42 23.81 23.81 76.07 76.07 92.84 92.84 22.67 22.67 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2305048796
80.57 17.99 94.93 5.07 80.57 15.17 93.53 26.10 71.43 47.62 85.31 9.24 94.88 2.05 43.33 20.66 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1226948038
85.47 4.90 97.47 2.53 83.89 3.32 95.87 2.34 80.95 9.52 90.28 4.98 95.91 1.02 53.93 10.60 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3996909442
89.68 4.21 98.45 0.98 83.89 0.00 95.87 0.00 100.00 19.05 91.71 1.42 95.91 0.00 61.97 8.04 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2095222216
91.70 2.02 98.69 0.25 88.03 4.15 96.42 0.55 100.00 0.00 94.31 2.61 95.91 0.00 68.56 6.58 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3695167534
92.98 1.28 98.86 0.16 89.45 1.42 98.66 2.24 100.00 0.00 95.26 0.95 96.05 0.15 72.58 4.02 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.316968140
93.91 0.93 98.86 0.00 89.45 0.00 98.66 0.00 100.00 0.00 95.26 0.00 97.08 1.02 78.06 5.48 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3449398916
94.73 0.82 98.86 0.00 90.05 0.59 98.66 0.00 100.00 0.00 95.26 0.00 97.08 0.00 83.18 5.12 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3329185414
95.44 0.71 98.86 0.00 90.05 0.00 98.73 0.07 100.00 0.00 95.26 0.00 97.08 0.00 88.12 4.94 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2733566297
96.01 0.57 99.10 0.25 90.05 0.00 98.73 0.00 100.00 0.00 95.50 0.24 97.08 0.00 91.59 3.47 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3026221652
96.42 0.42 99.10 0.00 90.05 0.00 98.73 0.00 100.00 0.00 95.50 0.00 97.08 0.00 94.52 2.93 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.144002614
96.61 0.19 99.10 0.00 90.17 0.12 98.73 0.00 100.00 0.00 95.97 0.47 97.81 0.73 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.574169782
96.79 0.18 99.10 0.00 90.17 0.00 98.79 0.07 100.00 0.00 95.97 0.00 98.98 1.17 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2145677875
96.95 0.16 99.18 0.08 90.17 0.00 99.62 0.83 100.00 0.00 96.21 0.24 98.98 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2323981611
97.11 0.16 99.18 0.00 90.17 0.00 99.62 0.00 100.00 0.00 96.21 0.00 98.98 0.00 95.61 1.10 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3814616877
97.21 0.10 99.18 0.00 90.17 0.00 99.62 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.34 0.73 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2963255261
97.28 0.07 99.18 0.00 90.64 0.47 99.62 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3323085438
97.35 0.07 99.18 0.00 91.00 0.36 99.72 0.10 100.00 0.00 96.21 0.00 98.98 0.00 96.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3877271219
97.40 0.05 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.71 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3425323777
97.45 0.05 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.07 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1585500278
97.48 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3166582220
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.51733126
97.52 0.02 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.354974839

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.655567770
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.345359635
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2003466891
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3897991327
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.97142950
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1078002130
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.860698277
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2459903253
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.952729335
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4219161622
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.104493698
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.379357024
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.993523100
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3439604373
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3550779749
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3975286131
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3292304036
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.174705479
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1859103962
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1824791189
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2724052316
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1431370230
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.287311456
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1809859493
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2301908400
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4172128977
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3020743822
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1799633367
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.506900013
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2981250294
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1626215489
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1476124245
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3661061069
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2134372227
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.425055591
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3127380492
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2274771311
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3946472328
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2026829682
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3755086160
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1772360056
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3807715581
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1115740066
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2413906071
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3213884818
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3074130405
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1943007016
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3938830653
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.211947629
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.502307638
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1007469774
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2899692177
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.61656787
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.330403753
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4169972948
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3519697097
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1038013071
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1897276867
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3867972463
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2535815564
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.48969630
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4163000242
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.589360663
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1933348465
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1974330404
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3725230709
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4184577962
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2558004217
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3961208808
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3425705785
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1793423171
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1191837576
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1026756627
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3813823814
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.148512946
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2583973302
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2578929023
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.502589351
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1761319702
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1045916888
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4214829744
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3677303469
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2776504269
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1644160710
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2996077539
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/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.514680568
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3272259886
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.2713428604
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1484497649
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2768406601
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3054870169
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.418586393
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/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3924785761
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/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.234526020
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.2970572224
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.210068195
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.458947673
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1545495700
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3361644989
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1433651499
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4055603600
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3150509053
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1862066486
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1127623934
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3871991889
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3772609208
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1983999319
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3181056712
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.542298793
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3588336660
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.4000785047
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.118535330
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.261618021
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.4236373022
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.1559807477
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3426073383
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2694591827
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2261122493
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1959725099
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.232194596
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2493299544
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3262364546
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3781899311
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3299851408
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1002944477
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3075237352
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2010129983
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3636023211
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2969383586
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1466891868
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.610927942
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1064948068
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.295965877
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2246955240
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1013685700
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2363184389
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2187728126
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.831635932
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2892125115
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.4099715562
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1251699936
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3988064652
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3181087614
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1169653841
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3622075877
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1174923709
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1168015463
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2153376085
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.967144218
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.1221073947
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2125750268
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3772297132
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3474561260
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3408295099



Total test records in report: 1037
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3102861224 Aug 23 12:53:06 PM UTC 24 Aug 23 12:53:17 PM UTC 24 6631014385 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3877271219 Aug 23 12:53:15 PM UTC 24 Aug 23 12:53:17 PM UTC 24 45583685 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3045059141 Aug 23 12:53:12 PM UTC 24 Aug 23 12:53:17 PM UTC 24 1408357036 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2305048796 Aug 23 12:53:09 PM UTC 24 Aug 23 12:53:17 PM UTC 24 2797243313 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3996909442 Aug 23 12:53:15 PM UTC 24 Aug 23 12:53:18 PM UTC 24 200676608 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3899351485 Aug 23 12:53:09 PM UTC 24 Aug 23 12:53:21 PM UTC 24 741378620 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.205667386 Aug 23 12:53:18 PM UTC 24 Aug 23 12:53:28 PM UTC 24 3143919489 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.809680447 Aug 23 12:53:26 PM UTC 24 Aug 23 12:53:31 PM UTC 24 1350845760 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1461031283 Aug 23 12:53:08 PM UTC 24 Aug 23 12:53:32 PM UTC 24 5233343255 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.3812472673 Aug 23 12:53:16 PM UTC 24 Aug 23 12:53:37 PM UTC 24 887494385 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.138355213 Aug 23 12:53:37 PM UTC 24 Aug 23 12:53:40 PM UTC 24 462384549 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1677035959 Aug 23 12:53:41 PM UTC 24 Aug 23 12:53:43 PM UTC 24 38703364 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2848526651 Aug 23 12:53:09 PM UTC 24 Aug 23 12:53:52 PM UTC 24 7947114591 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1986972001 Aug 23 12:53:42 PM UTC 24 Aug 23 12:53:56 PM UTC 24 1054294611 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.316968140 Aug 23 12:53:19 PM UTC 24 Aug 23 12:54:07 PM UTC 24 29506357641 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2620890223 Aug 23 12:53:57 PM UTC 24 Aug 23 12:54:16 PM UTC 24 2491927521 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.383444136 Aug 23 12:53:19 PM UTC 24 Aug 23 12:54:19 PM UTC 24 3137378284 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3449398916 Aug 23 12:53:15 PM UTC 24 Aug 23 12:54:21 PM UTC 24 5774444403 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2376205564 Aug 23 12:53:18 PM UTC 24 Aug 23 12:54:24 PM UTC 24 3177598215 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4069408795 Aug 23 12:54:17 PM UTC 24 Aug 23 12:54:26 PM UTC 24 721848128 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2416185711 Aug 23 12:53:11 PM UTC 24 Aug 23 12:54:42 PM UTC 24 5513237049 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2323981611 Aug 23 12:54:42 PM UTC 24 Aug 23 12:54:47 PM UTC 24 1250272465 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1782441413 Aug 23 12:54:20 PM UTC 24 Aug 23 12:54:49 PM UTC 24 15044435914 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1406272245 Aug 23 12:54:11 PM UTC 24 Aug 23 12:54:54 PM UTC 24 1525632039 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1226948038 Aug 23 12:53:31 PM UTC 24 Aug 23 12:54:57 PM UTC 24 7247935286 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1584963246 Aug 23 12:54:58 PM UTC 24 Aug 23 12:55:01 PM UTC 24 261700311 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1726873353 Aug 23 12:55:01 PM UTC 24 Aug 23 12:55:03 PM UTC 24 19684757 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.1414872710 Aug 23 12:54:25 PM UTC 24 Aug 23 12:55:04 PM UTC 24 4918154997 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1922662202 Aug 23 12:55:03 PM UTC 24 Aug 23 12:55:12 PM UTC 24 2950481962 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3060517275 Aug 23 12:53:15 PM UTC 24 Aug 23 12:55:14 PM UTC 24 2497614661 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1023262321 Aug 23 12:53:30 PM UTC 24 Aug 23 12:55:26 PM UTC 24 1601952211 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.514382712 Aug 23 12:55:04 PM UTC 24 Aug 23 12:55:30 PM UTC 24 3605234343 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.793385529 Aug 23 12:55:28 PM UTC 24 Aug 23 12:55:48 PM UTC 24 4426064908 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.4124415843 Aug 23 12:53:29 PM UTC 24 Aug 23 12:55:49 PM UTC 24 6921935927 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2733566297 Aug 23 12:54:50 PM UTC 24 Aug 23 12:55:51 PM UTC 24 4320320411 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2624427015 Aug 23 12:55:49 PM UTC 24 Aug 23 12:56:10 PM UTC 24 737030757 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.3314637606 Aug 23 12:54:27 PM UTC 24 Aug 23 12:56:31 PM UTC 24 3751816390 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1502725123 Aug 23 12:55:50 PM UTC 24 Aug 23 12:56:38 PM UTC 24 1578684099 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2326398486 Aug 23 12:55:52 PM UTC 24 Aug 23 12:56:38 PM UTC 24 13086663130 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.971867490 Aug 23 12:54:47 PM UTC 24 Aug 23 12:56:40 PM UTC 24 1593521054 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.574359996 Aug 23 12:56:39 PM UTC 24 Aug 23 12:56:43 PM UTC 24 1355179650 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.92061083 Aug 23 12:53:53 PM UTC 24 Aug 23 12:56:46 PM UTC 24 3140274994 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.595856000 Aug 23 12:56:47 PM UTC 24 Aug 23 12:56:57 PM UTC 24 972096370 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3695167534 Aug 23 12:53:11 PM UTC 24 Aug 23 12:57:04 PM UTC 24 14957490618 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.797353126 Aug 23 12:57:04 PM UTC 24 Aug 23 12:57:07 PM UTC 24 493867294 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1664422961 Aug 23 12:57:07 PM UTC 24 Aug 23 12:57:09 PM UTC 24 43491863 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3010929913 Aug 23 12:53:18 PM UTC 24 Aug 23 12:57:19 PM UTC 24 33425455821 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1416037777 Aug 23 12:57:09 PM UTC 24 Aug 23 12:57:21 PM UTC 24 13307303772 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3170046823 Aug 23 12:53:21 PM UTC 24 Aug 23 12:57:27 PM UTC 24 5444036014 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2140109460 Aug 23 12:53:15 PM UTC 24 Aug 23 12:57:46 PM UTC 24 21011004494 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1810764892 Aug 23 12:53:17 PM UTC 24 Aug 23 12:58:07 PM UTC 24 9995673220 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.51733126 Aug 23 12:53:07 PM UTC 24 Aug 23 12:58:07 PM UTC 24 11771683185 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.772546648 Aug 23 12:57:47 PM UTC 24 Aug 23 12:58:10 PM UTC 24 3779167759 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3026221652 Aug 23 12:53:18 PM UTC 24 Aug 23 12:58:20 PM UTC 24 48123825020 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.3508819371 Aug 23 12:53:44 PM UTC 24 Aug 23 12:58:27 PM UTC 24 26962094204 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.4067190568 Aug 23 12:58:08 PM UTC 24 Aug 23 12:58:30 PM UTC 24 761585354 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2995709662 Aug 23 12:58:21 PM UTC 24 Aug 23 12:58:31 PM UTC 24 2649942114 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.2818573758 Aug 23 12:56:39 PM UTC 24 Aug 23 12:58:41 PM UTC 24 6272909503 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.179125221 Aug 23 12:53:24 PM UTC 24 Aug 23 12:58:42 PM UTC 24 51271056945 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1162007149 Aug 23 12:58:11 PM UTC 24 Aug 23 12:58:43 PM UTC 24 3136347689 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1524755773 Aug 23 12:58:41 PM UTC 24 Aug 23 12:58:46 PM UTC 24 1612952663 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1424254164 Aug 23 12:53:08 PM UTC 24 Aug 23 12:59:03 PM UTC 24 4663053168 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3335341703 Aug 23 12:56:44 PM UTC 24 Aug 23 12:59:08 PM UTC 24 5236320429 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3457436218 Aug 23 12:59:09 PM UTC 24 Aug 23 12:59:12 PM UTC 24 852359512 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3446160874 Aug 23 12:59:13 PM UTC 24 Aug 23 12:59:15 PM UTC 24 12619534 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3025158202 Aug 23 12:54:08 PM UTC 24 Aug 23 12:59:15 PM UTC 24 27316885636 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.514680568 Aug 23 12:59:16 PM UTC 24 Aug 23 12:59:36 PM UTC 24 9205622040 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3398428186 Aug 23 12:55:31 PM UTC 24 Aug 23 12:59:49 PM UTC 24 10454753840 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1699140061 Aug 23 12:53:08 PM UTC 24 Aug 23 12:59:56 PM UTC 24 47977011519 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3663906688 Aug 23 12:55:15 PM UTC 24 Aug 23 12:59:56 PM UTC 24 17687298056 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1608276762 Aug 23 12:54:47 PM UTC 24 Aug 23 12:59:56 PM UTC 24 20687756059 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1060530686 Aug 23 12:59:57 PM UTC 24 Aug 23 01:00:10 PM UTC 24 3150750557 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1790611219 Aug 23 12:59:57 PM UTC 24 Aug 23 01:00:15 PM UTC 24 4533874331 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.6774441 Aug 23 12:58:43 PM UTC 24 Aug 23 01:00:54 PM UTC 24 4391208200 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.759894289 Aug 23 12:58:46 PM UTC 24 Aug 23 01:00:56 PM UTC 24 2893567799 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1484497649 Aug 23 01:00:11 PM UTC 24 Aug 23 01:01:00 PM UTC 24 830415194 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3367023653 Aug 23 12:56:40 PM UTC 24 Aug 23 01:01:24 PM UTC 24 13827432651 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1656436305 Aug 23 01:00:16 PM UTC 24 Aug 23 01:01:28 PM UTC 24 12509163271 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.4095263162 Aug 23 01:01:26 PM UTC 24 Aug 23 01:01:30 PM UTC 24 709621008 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3467247307 Aug 23 12:58:08 PM UTC 24 Aug 23 01:01:42 PM UTC 24 19738848043 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3272259886 Aug 23 01:01:43 PM UTC 24 Aug 23 01:01:48 PM UTC 24 1575885567 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2856442677 Aug 23 12:53:09 PM UTC 24 Aug 23 01:01:50 PM UTC 24 23734529767 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1781634250 Aug 23 12:57:28 PM UTC 24 Aug 23 01:01:51 PM UTC 24 5601322941 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.836037177 Aug 23 01:01:51 PM UTC 24 Aug 23 01:01:52 PM UTC 24 43151123 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.2713428604 Aug 23 12:59:50 PM UTC 24 Aug 23 01:01:55 PM UTC 24 20143179592 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.458947673 Aug 23 01:01:52 PM UTC 24 Aug 23 01:02:09 PM UTC 24 1957641626 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.1009873968 Aug 23 01:00:56 PM UTC 24 Aug 23 01:02:10 PM UTC 24 39035256274 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1882253831 Aug 23 01:02:11 PM UTC 24 Aug 23 01:02:18 PM UTC 24 820292967 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.3103112323 Aug 23 12:58:31 PM UTC 24 Aug 23 01:02:26 PM UTC 24 7483301634 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3701888145 Aug 23 12:59:17 PM UTC 24 Aug 23 01:02:34 PM UTC 24 3100979455 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3924785761 Aug 23 01:02:26 PM UTC 24 Aug 23 01:02:36 PM UTC 24 717456185 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4055603600 Aug 23 01:02:35 PM UTC 24 Aug 23 01:02:47 PM UTC 24 2881655038 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2928173802 Aug 23 12:54:22 PM UTC 24 Aug 23 01:02:51 PM UTC 24 10360992369 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.144002614 Aug 23 12:53:21 PM UTC 24 Aug 23 01:03:14 PM UTC 24 29441979744 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.2904367673 Aug 23 12:55:13 PM UTC 24 Aug 23 01:03:34 PM UTC 24 16409083492 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.2970572224 Aug 23 01:03:35 PM UTC 24 Aug 23 01:03:39 PM UTC 24 2814464304 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1731814794 Aug 23 01:02:37 PM UTC 24 Aug 23 01:03:41 PM UTC 24 19295738992 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.735174312 Aug 23 12:58:42 PM UTC 24 Aug 23 01:03:51 PM UTC 24 20655468173 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1445251310 Aug 23 01:01:31 PM UTC 24 Aug 23 01:03:56 PM UTC 24 13981617512 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2095222216 Aug 23 01:01:30 PM UTC 24 Aug 23 01:04:03 PM UTC 24 10348815789 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3054870169 Aug 23 01:04:03 PM UTC 24 Aug 23 01:04:04 PM UTC 24 77992746 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3361644989 Aug 23 01:03:52 PM UTC 24 Aug 23 01:04:12 PM UTC 24 1072298468 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.1559807477 Aug 23 01:04:05 PM UTC 24 Aug 23 01:04:25 PM UTC 24 3948978423 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2641421107 Aug 23 01:00:55 PM UTC 24 Aug 23 01:04:28 PM UTC 24 8050850874 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.807956843 Aug 23 12:56:32 PM UTC 24 Aug 23 01:04:50 PM UTC 24 30041905502 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.2898329589 Aug 23 01:02:52 PM UTC 24 Aug 23 01:04:50 PM UTC 24 3236065362 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.4000785047 Aug 23 01:04:51 PM UTC 24 Aug 23 01:05:01 PM UTC 24 457622346 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2320400491 Aug 23 12:59:57 PM UTC 24 Aug 23 01:05:38 PM UTC 24 6953130117 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1983999319 Aug 23 01:05:01 PM UTC 24 Aug 23 01:05:50 PM UTC 24 898743762 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1959725099 Aug 23 01:05:39 PM UTC 24 Aug 23 01:06:06 PM UTC 24 6095215708 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2607855397 Aug 23 01:03:42 PM UTC 24 Aug 23 01:06:15 PM UTC 24 11015874801 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.864799721 Aug 23 12:58:31 PM UTC 24 Aug 23 01:06:31 PM UTC 24 2871710109 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3772609208 Aug 23 01:05:51 PM UTC 24 Aug 23 01:07:05 PM UTC 24 43908808785 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.261618021 Aug 23 01:07:06 PM UTC 24 Aug 23 01:07:11 PM UTC 24 1407500699 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1433651499 Aug 23 01:02:10 PM UTC 24 Aug 23 01:07:24 PM UTC 24 38136988872 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.596181140 Aug 23 12:56:11 PM UTC 24 Aug 23 01:07:45 PM UTC 24 14348245149 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2694591827 Aug 23 01:07:45 PM UTC 24 Aug 23 01:07:58 PM UTC 24 661334068 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.4082228556 Aug 23 12:54:54 PM UTC 24 Aug 23 01:08:07 PM UTC 24 157438096573 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1862066486 Aug 23 01:08:07 PM UTC 24 Aug 23 01:08:09 PM UTC 24 36035337 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2261122493 Aug 23 01:04:29 PM UTC 24 Aug 23 01:08:15 PM UTC 24 15085388814 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1064948068 Aug 23 01:08:09 PM UTC 24 Aug 23 01:08:25 PM UTC 24 1561892317 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3544244621 Aug 23 01:01:53 PM UTC 24 Aug 23 01:08:31 PM UTC 24 58414510269 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.487501554 Aug 23 01:03:41 PM UTC 24 Aug 23 01:08:34 PM UTC 24 57548887737 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.4049079420 Aug 23 12:58:28 PM UTC 24 Aug 23 01:08:52 PM UTC 24 278709538048 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2969383586 Aug 23 01:08:35 PM UTC 24 Aug 23 01:09:00 PM UTC 24 3203967198 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1002944477 Aug 23 01:09:01 PM UTC 24 Aug 23 01:09:12 PM UTC 24 1501944879 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.234526020 Aug 23 01:02:19 PM UTC 24 Aug 23 01:09:22 PM UTC 24 174334292572 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3181056712 Aug 23 01:07:24 PM UTC 24 Aug 23 01:09:35 PM UTC 24 12867971997 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3323085438 Aug 23 01:01:49 PM UTC 24 Aug 23 01:09:35 PM UTC 24 104601281744 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.542298793 Aug 23 01:07:11 PM UTC 24 Aug 23 01:09:40 PM UTC 24 68969851446 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2363184389 Aug 23 01:09:13 PM UTC 24 Aug 23 01:09:46 PM UTC 24 764638328 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2577821789 Aug 23 12:57:20 PM UTC 24 Aug 23 01:09:50 PM UTC 24 137183102391 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.610927942 Aug 23 01:09:47 PM UTC 24 Aug 23 01:09:51 PM UTC 24 720020113 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.1064138072 Aug 23 12:53:07 PM UTC 24 Aug 23 01:10:28 PM UTC 24 73647404930 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3299851408 Aug 23 01:09:23 PM UTC 24 Aug 23 01:10:37 PM UTC 24 37240089064 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2768406601 Aug 23 01:02:47 PM UTC 24 Aug 23 01:10:50 PM UTC 24 23222118905 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2493299544 Aug 23 01:10:50 PM UTC 24 Aug 23 01:10:52 PM UTC 24 36275757 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2246955240 Aug 23 01:10:29 PM UTC 24 Aug 23 01:10:57 PM UTC 24 3588247880 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.118535330 Aug 23 01:04:51 PM UTC 24 Aug 23 01:10:57 PM UTC 24 19234258633 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3588336660 Aug 23 01:04:13 PM UTC 24 Aug 23 01:10:58 PM UTC 24 38670083428 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.1221073947 Aug 23 01:10:52 PM UTC 24 Aug 23 01:11:06 PM UTC 24 492876399 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3075237352 Aug 23 01:09:52 PM UTC 24 Aug 23 01:11:08 PM UTC 24 11472856117 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1174923709 Aug 23 01:11:07 PM UTC 24 Aug 23 01:11:26 PM UTC 24 4743268588 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.210068195 Aug 23 01:03:15 PM UTC 24 Aug 23 01:11:28 PM UTC 24 19367502076 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2010129983 Aug 23 01:09:51 PM UTC 24 Aug 23 01:11:38 PM UTC 24 5335742512 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1251699936 Aug 23 01:11:39 PM UTC 24 Aug 23 01:12:06 PM UTC 24 3458647368 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.232194596 Aug 23 01:09:36 PM UTC 24 Aug 23 01:12:13 PM UTC 24 21207502145 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3928609994 Aug 23 01:01:01 PM UTC 24 Aug 23 01:12:15 PM UTC 24 35003639804 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3988064652 Aug 23 01:11:27 PM UTC 24 Aug 23 01:12:15 PM UTC 24 1526740769 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2153376085 Aug 23 01:12:16 PM UTC 24 Aug 23 01:12:21 PM UTC 24 393583682 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3408295099 Aug 23 01:11:29 PM UTC 24 Aug 23 01:12:28 PM UTC 24 1632022317 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3181087614 Aug 23 01:12:28 PM UTC 24 Aug 23 01:13:27 PM UTC 24 1041830434 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1013685700 Aug 23 01:08:33 PM UTC 24 Aug 23 01:13:32 PM UTC 24 4464717691 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3871991889 Aug 23 01:06:16 PM UTC 24 Aug 23 01:13:39 PM UTC 24 7160288200 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.831635932 Aug 23 01:13:40 PM UTC 24 Aug 23 01:13:41 PM UTC 24 40044266 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.2014837237 Aug 23 01:13:42 PM UTC 24 Aug 23 01:13:52 PM UTC 24 743102492 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3772297132 Aug 23 01:13:28 PM UTC 24 Aug 23 01:14:05 PM UTC 24 2009832112 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1466891868 Aug 23 01:08:53 PM UTC 24 Aug 23 01:14:23 PM UTC 24 14282010125 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3636023211 Aug 23 01:08:15 PM UTC 24 Aug 23 01:14:27 PM UTC 24 32314708780 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3622075877 Aug 23 01:10:58 PM UTC 24 Aug 23 01:14:27 PM UTC 24 7273853556 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3150509053 Aug 23 01:06:07 PM UTC 24 Aug 23 01:14:56 PM UTC 24 97182364128 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3814616877 Aug 23 01:09:41 PM UTC 24 Aug 23 01:15:03 PM UTC 24 19626528888 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.197939638 Aug 23 01:14:56 PM UTC 24 Aug 23 01:15:04 PM UTC 24 796778805 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.962837848 Aug 23 01:14:28 PM UTC 24 Aug 23 01:15:09 PM UTC 24 1830383552 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3474561260 Aug 23 01:10:59 PM UTC 24 Aug 23 01:15:13 PM UTC 24 4173167070 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2397539428 Aug 23 01:15:14 PM UTC 24 Aug 23 01:15:34 PM UTC 24 5566374564 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.4164773356 Aug 23 01:15:04 PM UTC 24 Aug 23 01:15:46 PM UTC 24 3276048946 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3576255384 Aug 23 01:15:47 PM UTC 24 Aug 23 01:15:51 PM UTC 24 355704080 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1127623934 Aug 23 01:04:25 PM UTC 24 Aug 23 01:16:29 PM UTC 24 26406514424 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.668991881 Aug 23 01:15:04 PM UTC 24 Aug 23 01:16:37 PM UTC 24 55275879097 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.4236373022 Aug 23 01:06:32 PM UTC 24 Aug 23 01:16:40 PM UTC 24 8034850206 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1768360277 Aug 23 01:16:37 PM UTC 24 Aug 23 01:16:47 PM UTC 24 592661944 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.554014859 Aug 23 01:16:47 PM UTC 24 Aug 23 01:16:49 PM UTC 24 69794205 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1169653841 Aug 23 01:12:21 PM UTC 24 Aug 23 01:16:51 PM UTC 24 15715700488 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.567371369 Aug 23 01:16:49 PM UTC 24 Aug 23 01:16:53 PM UTC 24 359309565 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2321904780 Aug 23 12:57:22 PM UTC 24 Aug 23 01:17:25 PM UTC 24 107665239553 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.967144218 Aug 23 01:12:15 PM UTC 24 Aug 23 01:17:32 PM UTC 24 9379259552 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.280810787 Aug 23 01:17:32 PM UTC 24 Aug 23 01:17:43 PM UTC 24 2194294745 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.4099715562 Aug 23 01:12:13 PM UTC 24 Aug 23 01:17:44 PM UTC 24 5513458900 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2890703831 Aug 23 01:17:44 PM UTC 24 Aug 23 01:18:02 PM UTC 24 738548240 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1168015463 Aug 23 01:11:09 PM UTC 24 Aug 23 01:18:11 PM UTC 24 179605124785 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1194897015 Aug 23 01:18:12 PM UTC 24 Aug 23 01:18:26 PM UTC 24 24187870353 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2735587231 Aug 23 01:16:30 PM UTC 24 Aug 23 01:18:31 PM UTC 24 4967022658 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3959376103 Aug 23 01:18:03 PM UTC 24 Aug 23 01:18:41 PM UTC 24 762171037 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.94922899 Aug 23 12:53:44 PM UTC 24 Aug 23 01:19:37 PM UTC 24 307289641127 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.4175517071 Aug 23 01:19:38 PM UTC 24 Aug 23 01:19:43 PM UTC 24 1356828254 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2278859100 Aug 23 01:13:53 PM UTC 24 Aug 23 01:20:15 PM UTC 24 5338928137 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.1996261704 Aug 23 01:14:23 PM UTC 24 Aug 23 01:20:47 PM UTC 24 37248608788 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.4118629073 Aug 23 01:15:52 PM UTC 24 Aug 23 01:20:59 PM UTC 24 20910627805 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1319477137 Aug 23 01:21:00 PM UTC 24 Aug 23 01:21:02 PM UTC 24 24901248 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.696086990 Aug 23 01:18:42 PM UTC 24 Aug 23 01:21:06 PM UTC 24 10889514082 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1665697351 Aug 23 01:20:48 PM UTC 24 Aug 23 01:21:16 PM UTC 24 1051611102 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.1464336842 Aug 23 01:21:03 PM UTC 24 Aug 23 01:21:18 PM UTC 24 1637779567 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.418586393 Aug 23 01:01:56 PM UTC 24 Aug 23 01:21:19 PM UTC 24 60081299724 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.663723601 Aug 23 01:20:15 PM UTC 24 Aug 23 01:21:20 PM UTC 24 1398938132 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1301461364 Aug 23 01:17:25 PM UTC 24 Aug 23 01:21:32 PM UTC 24 9351054520 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.401914703 Aug 23 01:21:20 PM UTC 24 Aug 23 01:21:33 PM UTC 24 3633948310 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2790572968 Aug 23 01:19:44 PM UTC 24 Aug 23 01:22:07 PM UTC 24 32916157124 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.177631229 Aug 23 01:14:28 PM UTC 24 Aug 23 01:22:10 PM UTC 24 23115471589 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.1932023909 Aug 23 01:15:35 PM UTC 24 Aug 23 01:22:11 PM UTC 24 11396609004 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3898385341 Aug 23 01:21:34 PM UTC 24 Aug 23 01:22:16 PM UTC 24 814966056 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.272803445 Aug 23 01:21:32 PM UTC 24 Aug 23 01:22:29 PM UTC 24 3059349015 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1556056422 Aug 23 01:22:30 PM UTC 24 Aug 23 01:22:35 PM UTC 24 1554589968 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2154069572 Aug 23 01:22:08 PM UTC 24 Aug 23 01:23:08 PM UTC 24 31076280531 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2187728126 Aug 23 01:12:06 PM UTC 24 Aug 23 01:23:13 PM UTC 24 27259894204 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2668074544 Aug 23 01:21:19 PM UTC 24 Aug 23 01:23:36 PM UTC 24 3686397098 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.958644949 Aug 23 01:23:15 PM UTC 24 Aug 23 01:24:02 PM UTC 24 24059694231 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3443626637 Aug 23 01:24:03 PM UTC 24 Aug 23 01:24:04 PM UTC 24 24383915 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1255781997 Aug 23 01:23:10 PM UTC 24 Aug 23 01:24:20 PM UTC 24 3087044450 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2031056717 Aug 23 01:24:05 PM UTC 24 Aug 23 01:24:39 PM UTC 24 1211655720 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.4294136680 Aug 23 01:18:32 PM UTC 24 Aug 23 01:25:03 PM UTC 24 24654994266 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1536190855 Aug 23 01:22:12 PM UTC 24 Aug 23 01:26:34 PM UTC 24 86091282085 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.2042661559 Aug 23 01:26:36 PM UTC 24 Aug 23 01:26:48 PM UTC 24 511729323 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.4067878884 Aug 23 01:22:35 PM UTC 24 Aug 23 01:26:58 PM UTC 24 5416561540 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2421908517 Aug 23 01:26:59 PM UTC 24 Aug 23 01:27:19 PM UTC 24 737355058 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1893022680 Aug 23 01:17:44 PM UTC 24 Aug 23 01:27:40 PM UTC 24 98590150991 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3552142525 Aug 23 01:27:20 PM UTC 24 Aug 23 01:27:44 PM UTC 24 2924693565 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3781899311 Aug 23 01:09:36 PM UTC 24 Aug 23 01:27:45 PM UTC 24 120640879224 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2790054139 Aug 23 01:22:17 PM UTC 24 Aug 23 01:28:19 PM UTC 24 6771992715 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.808750464 Aug 23 01:27:41 PM UTC 24 Aug 23 01:28:33 PM UTC 24 15106081610 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.188894391 Aug 23 01:28:34 PM UTC 24 Aug 23 01:28:38 PM UTC 24 1363296426 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1482079753 Aug 23 01:18:27 PM UTC 24 Aug 23 01:28:43 PM UTC 24 12731733157 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1748316378 Aug 23 01:25:04 PM UTC 24 Aug 23 01:28:52 PM UTC 24 23920529504 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1978640793 Aug 23 01:24:20 PM UTC 24 Aug 23 01:28:56 PM UTC 24 6725289249 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3189079220 Aug 23 01:28:52 PM UTC 24 Aug 23 01:29:19 PM UTC 24 1556390857 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.711261870 Aug 23 01:21:21 PM UTC 24 Aug 23 01:29:21 PM UTC 24 11878176684 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3669590666 Aug 23 01:22:11 PM UTC 24 Aug 23 01:29:22 PM UTC 24 52809939428 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3088187660 Aug 23 01:29:20 PM UTC 24 Aug 23 01:29:22 PM UTC 24 63220517 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.661710857 Aug 23 01:29:23 PM UTC 24 Aug 23 01:29:33 PM UTC 24 689466329 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1031351776 Aug 23 01:16:52 PM UTC 24 Aug 23 01:29:45 PM UTC 24 19789727162 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2043930597 Aug 23 01:28:43 PM UTC 24 Aug 23 01:29:49 PM UTC 24 2708418678 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3262364546 Aug 23 01:08:25 PM UTC 24 Aug 23 01:29:52 PM UTC 24 155753552322 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3232078969 Aug 23 01:29:46 PM UTC 24 Aug 23 01:29:53 PM UTC 24 1343310897 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2263031209 Aug 23 01:29:54 PM UTC 24 Aug 23 01:30:24 PM UTC 24 776029748 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1761056725 Aug 23 01:29:53 PM UTC 24 Aug 23 01:30:33 PM UTC 24 772514047 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3775961451 Aug 23 01:28:39 PM UTC 24 Aug 23 01:30:52 PM UTC 24 10109890939 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.58741685 Aug 23 01:30:25 PM UTC 24 Aug 23 01:31:04 PM UTC 24 6447976429 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.272597777 Aug 23 01:29:34 PM UTC 24 Aug 23 01:31:50 PM UTC 24 4131373459 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2689972810 Aug 23 01:15:09 PM UTC 24 Aug 23 01:31:51 PM UTC 24 21214914977 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.674170396 Aug 23 01:31:51 PM UTC 24 Aug 23 01:31:55 PM UTC 24 1410149045 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2824997864 Aug 23 01:21:07 PM UTC 24 Aug 23 01:32:43 PM UTC 24 54121980176 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.4039951673 Aug 23 01:32:44 PM UTC 24 Aug 23 01:32:54 PM UTC 24 1003531363 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.1101727863 Aug 23 01:27:46 PM UTC 24 Aug 23 01:33:08 PM UTC 24 11881915549 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4131082658 Aug 23 01:26:50 PM UTC 24 Aug 23 01:33:08 PM UTC 24 27280575434 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.197996163 Aug 23 01:33:08 PM UTC 24 Aug 23 01:33:11 PM UTC 24 21712985 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.2415995700 Aug 23 12:53:18 PM UTC 24 Aug 23 01:33:20 PM UTC 24 194828467651 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.3272768670 Aug 23 01:33:09 PM UTC 24 Aug 23 01:33:26 PM UTC 24 953219997 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2762388542 Aug 23 01:31:52 PM UTC 24 Aug 23 01:34:02 PM UTC 24 2771788485 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.82901939 Aug 23 01:31:57 PM UTC 24 Aug 23 01:34:25 PM UTC 24 21756433332 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3336037499 Aug 23 01:34:02 PM UTC 24 Aug 23 01:34:25 PM UTC 24 8788668517 ps