Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	313024600	1			T3	2068		T4	19038		T5	1938
instr_valid_dis	279487279	1			T3	2068		T4	19038		T5	1938
instr_en	20921514	1			T24	15767		T37	11400		T16	21948

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12480891	1			T17	1602		T18	14990		T42	17212
sram_ifetch_valid_disable	267779542	1			T3	2068		T4	19038		T5	1938
sram_ifetch_enable	32764167	1			T24	15763		T17	17488		T18	38942

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	313024600	1			T3	2068		T4	19038		T5	1938
hw_debug_en_valid_off	270698188	1			T3	2068		T4	19038		T5	1938
hw_debug_en_on	27558775	1			T16	21948		T17	30112		T18	89950

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	267779542	1			T3	2068		T4	19038		T5	1938
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	255061532	1			T3	2068		T4	19038		T5	1938
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7684489	1			T24	4		T37	11400		T16	21948
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4672048	1			T17	488		T156	19808		T153	5096
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1442216	1			T17	488		T156	19808		T150	8840
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2433772	1			T153	5096		T150	29728		T151	3062
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4464546	1			T17	1114		T18	14990		T42	17212
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2067936	1			T17	1114		T156	24236		T150	16396
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1384494	1			T18	14990		T42	17212		T151	63904
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9194521	1			T16	21948		T17	11510		T18	74960
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4180126	1			T156	22488		T129	5206		T150	65940
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2850580	1			T16	21948		T17	11510		T18	74960

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8383363	1			T24	15763		T18	38942		T42	16336
lc_exec_en	13899708	1			T17	17488		T42	16336		T153	97382
valid_exec_dis	270962005	1			T3	2068		T4	19038		T5	1938
invalid_exec_dis	45245058	1			T24	15763		T17	19090		T18	53932