Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1037
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.18 62.18 90.60 90.60 61.14 61.14 51.72 51.72 23.81 23.81 77.25 77.25 92.69 92.69 38.03 38.03 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.4212332001
82.47 20.30 95.42 4.82 77.61 16.47 79.30 27.58 66.67 42.86 87.44 10.19 95.18 2.49 75.69 37.66 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3918900597
88.27 5.80 96.81 1.39 83.53 5.92 96.28 16.98 76.19 9.52 90.76 3.32 96.05 0.88 78.24 2.56 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.4085954028
92.38 4.12 98.12 1.31 84.36 0.83 96.28 0.00 100.00 23.81 92.42 1.66 97.08 1.02 78.43 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2206004706
93.56 1.17 98.69 0.57 86.97 2.61 97.69 1.41 100.00 0.00 94.55 2.13 97.66 0.58 79.34 0.91 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1146424232
94.66 1.10 98.86 0.16 88.74 1.78 98.48 0.79 100.00 0.00 95.50 0.95 97.66 0.00 83.36 4.02 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1488664569
95.45 0.79 98.86 0.00 89.34 0.59 98.48 0.00 100.00 0.00 95.50 0.00 97.66 0.00 88.30 4.94 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.234196505
96.06 0.61 99.10 0.25 89.34 0.00 98.48 0.00 100.00 0.00 95.73 0.24 97.81 0.15 91.96 3.66 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.4196715684
96.40 0.34 99.10 0.00 89.34 0.00 98.48 0.00 100.00 0.00 95.73 0.00 97.81 0.00 94.33 2.38 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.63521667
96.62 0.22 99.10 0.00 90.52 1.18 98.66 0.17 100.00 0.00 95.73 0.00 97.81 0.00 94.52 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2233420578
96.79 0.17 99.10 0.00 90.52 0.00 98.66 0.00 100.00 0.00 95.73 0.00 98.98 1.17 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2271743857
96.93 0.14 99.18 0.08 90.52 0.00 99.55 0.90 100.00 0.00 95.73 0.00 98.98 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3429611186
97.03 0.10 99.18 0.00 90.52 0.00 99.55 0.00 100.00 0.00 95.73 0.00 98.98 0.00 95.25 0.73 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.540527683
97.13 0.10 99.18 0.00 90.88 0.36 99.55 0.00 100.00 0.00 95.73 0.00 98.98 0.00 95.61 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.594879092
97.22 0.08 99.18 0.00 91.00 0.12 99.55 0.00 100.00 0.00 96.21 0.47 98.98 0.00 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.166307865
97.30 0.08 99.18 0.00 91.00 0.00 99.55 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.16 0.55 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.497261516
97.36 0.07 99.18 0.00 91.00 0.00 99.66 0.10 100.00 0.00 96.21 0.00 98.98 0.00 96.53 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3316895841
97.42 0.05 99.18 0.00 91.00 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1505227712
97.45 0.03 99.18 0.00 91.00 0.00 99.72 0.07 100.00 0.00 96.21 0.00 99.12 0.15 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.249986667
97.47 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.719412114
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2111960030
97.52 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2790055754

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.791653301
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.534989055
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2385662623
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4202042158
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.685006265
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3064302185
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1716614419
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3383691824
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.450320871
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2047931845
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.766921613
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3816123284
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2738752619
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1882141200
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1778383205
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2368261001
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.841191976
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.118835240
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3052301817
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3354851871
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2219471908
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.402295444
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1215013407
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1718357875
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4021540090
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.662969094
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.104705369
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1285881133
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.133549197
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2151827504
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1633563538
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2743332881
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2171465062
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2947035280
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2711751204
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.348571995
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4144417115
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.567575695
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3312639370
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2216336479
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2588976776
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1216922952
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3710636885
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3395073342
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1802617160
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3580326499
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3456697895
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3939290237
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3276382696
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3821630333
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3636895175
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3734363874
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.66193180
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1158488667
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2723595683
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3634645883
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2211332267
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.453277637
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3059275945
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1968085897
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.62431886
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.340806445
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4096485714
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.833846303
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2084936305
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2730901172
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3291616866
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2974230854
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.960654320
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3474914862
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.351217811
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2455905483
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.10058347
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2754860474
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2020379319
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.196641476
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2278219344
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2424610316
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.773850859
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3270842687
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3249381051
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2291844424
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2339230242
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2344374064
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.793702277
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2809902489
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.575118664
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1175119755
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3436896494
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1684972811
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1005987661
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2429069360
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1790334347
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1575674226
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1802320311
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2854626297
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.4162358241
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.172190499
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2831765066
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2759334476
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.338491589
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.4027209879
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1903473946
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1552592675
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.965057166
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3832512930
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.219112212
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3742713319
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4086561910
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2063932
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1024008649
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3933721796
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.1978663899
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.623937066
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.672920673
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.708400746
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2925433515
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3967101625
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3616425659
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.874725379
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1117484187
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.302803626
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4272685387
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.4040629930
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.4147235185
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2275122827
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1655688709
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2724544501
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3251735409
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2142856018
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.229024286
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.363443922
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1250707521
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2235033437
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1037810108
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2028020169
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.1567200293
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2557977708
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.815263382
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3511638915
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3859414973



Total test records in report: 1037
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2233420578 Aug 25 04:17:12 AM UTC 24 Aug 25 04:17:13 AM UTC 24 39750584 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3429611186 Aug 25 04:17:09 AM UTC 24 Aug 25 04:17:17 AM UTC 24 1503604191 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1146424232 Aug 25 04:17:11 AM UTC 24 Aug 25 04:17:18 AM UTC 24 791424152 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2309195471 Aug 25 04:17:18 AM UTC 24 Aug 25 04:17:25 AM UTC 24 354060431 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.451023123 Aug 25 04:17:26 AM UTC 24 Aug 25 04:17:28 AM UTC 24 106230233 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3240642102 Aug 25 04:17:03 AM UTC 24 Aug 25 04:17:28 AM UTC 24 1074614268 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.3254986902 Aug 25 04:17:24 AM UTC 24 Aug 25 04:17:29 AM UTC 24 561383470 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.4212332001 Aug 25 04:17:08 AM UTC 24 Aug 25 04:17:33 AM UTC 24 2712069460 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3395158788 Aug 25 04:17:16 AM UTC 24 Aug 25 04:17:33 AM UTC 24 744942342 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1414847706 Aug 25 04:17:12 AM UTC 24 Aug 25 04:17:38 AM UTC 24 917393434 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2495948106 Aug 25 04:17:22 AM UTC 24 Aug 25 04:17:42 AM UTC 24 512952932 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2361625446 Aug 25 04:17:15 AM UTC 24 Aug 25 04:17:50 AM UTC 24 2815292963 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.4085954028 Aug 25 04:17:08 AM UTC 24 Aug 25 04:17:51 AM UTC 24 11267660129 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3070498380 Aug 25 04:17:47 AM UTC 24 Aug 25 04:17:52 AM UTC 24 462829675 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1580386110 Aug 25 04:17:29 AM UTC 24 Aug 25 04:17:52 AM UTC 24 597281695 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2760637483 Aug 25 04:17:44 AM UTC 24 Aug 25 04:17:52 AM UTC 24 2602339466 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1961880441 Aug 25 04:17:50 AM UTC 24 Aug 25 04:17:53 AM UTC 24 15439132 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3948007151 Aug 25 04:17:07 AM UTC 24 Aug 25 04:17:55 AM UTC 24 3096218637 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3233909803 Aug 25 04:17:34 AM UTC 24 Aug 25 04:18:08 AM UTC 24 2544076529 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2497352214 Aug 25 04:17:16 AM UTC 24 Aug 25 04:18:11 AM UTC 24 3034120964 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1390084580 Aug 25 04:18:02 AM UTC 24 Aug 25 04:18:16 AM UTC 24 2811871673 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2595336535 Aug 25 04:18:13 AM UTC 24 Aug 25 04:18:20 AM UTC 24 389117618 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3131063128 Aug 25 04:17:32 AM UTC 24 Aug 25 04:18:20 AM UTC 24 1649818342 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.891644170 Aug 25 04:18:21 AM UTC 24 Aug 25 04:18:23 AM UTC 24 66595933 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.284928080 Aug 25 04:18:20 AM UTC 24 Aug 25 04:18:26 AM UTC 24 214432370 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.3447543544 Aug 25 04:17:52 AM UTC 24 Aug 25 04:18:39 AM UTC 24 749113380 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.3525963892 Aug 25 04:18:21 AM UTC 24 Aug 25 04:18:40 AM UTC 24 746600952 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1087277109 Aug 25 04:17:16 AM UTC 24 Aug 25 04:18:43 AM UTC 24 24086019465 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1323474703 Aug 25 04:18:17 AM UTC 24 Aug 25 04:18:44 AM UTC 24 2758750855 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1840356113 Aug 25 04:18:30 AM UTC 24 Aug 25 04:18:44 AM UTC 24 2677529509 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3209014447 Aug 25 04:18:41 AM UTC 24 Aug 25 04:18:49 AM UTC 24 1123033430 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.820833889 Aug 25 04:18:47 AM UTC 24 Aug 25 04:18:51 AM UTC 24 185057411 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.1291557142 Aug 25 04:18:51 AM UTC 24 Aug 25 04:18:53 AM UTC 24 14763873 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3316895841 Aug 25 04:17:10 AM UTC 24 Aug 25 04:19:01 AM UTC 24 1332800308 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.537695278 Aug 25 04:18:26 AM UTC 24 Aug 25 04:19:03 AM UTC 24 2945815217 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2790055754 Aug 25 04:17:05 AM UTC 24 Aug 25 04:19:04 AM UTC 24 5908109631 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2963224471 Aug 25 04:17:21 AM UTC 24 Aug 25 04:19:06 AM UTC 24 2451410917 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.1077252622 Aug 25 04:18:53 AM UTC 24 Aug 25 04:19:08 AM UTC 24 1256015656 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3918900597 Aug 25 04:17:45 AM UTC 24 Aug 25 04:19:17 AM UTC 24 8882081118 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1154999864 Aug 25 04:18:29 AM UTC 24 Aug 25 04:19:23 AM UTC 24 807164995 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3657287682 Aug 25 04:17:38 AM UTC 24 Aug 25 04:19:24 AM UTC 24 16513542266 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3049321234 Aug 25 04:17:38 AM UTC 24 Aug 25 04:19:27 AM UTC 24 1570534704 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1490562775 Aug 25 04:18:31 AM UTC 24 Aug 25 04:19:27 AM UTC 24 21147990606 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2464760823 Aug 25 04:19:27 AM UTC 24 Aug 25 04:19:35 AM UTC 24 356608754 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2252165298 Aug 25 04:17:53 AM UTC 24 Aug 25 04:19:36 AM UTC 24 951177030 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1828026037 Aug 25 04:17:41 AM UTC 24 Aug 25 04:19:37 AM UTC 24 14695438234 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2206004706 Aug 25 04:17:45 AM UTC 24 Aug 25 04:19:37 AM UTC 24 3369018464 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1834694462 Aug 25 04:19:38 AM UTC 24 Aug 25 04:19:40 AM UTC 24 16586683 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.382879940 Aug 25 04:17:56 AM UTC 24 Aug 25 04:19:42 AM UTC 24 798628147 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2831955087 Aug 25 04:19:07 AM UTC 24 Aug 25 04:19:43 AM UTC 24 1421419851 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.752100262 Aug 25 04:18:45 AM UTC 24 Aug 25 04:19:49 AM UTC 24 8969870321 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.38416504 Aug 25 04:18:02 AM UTC 24 Aug 25 04:20:00 AM UTC 24 10116445847 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3536219636 Aug 25 04:19:37 AM UTC 24 Aug 25 04:20:09 AM UTC 24 1505163143 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.604984502 Aug 25 04:19:46 AM UTC 24 Aug 25 04:20:15 AM UTC 24 941459304 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1005987661 Aug 25 04:19:41 AM UTC 24 Aug 25 04:20:16 AM UTC 24 4290825732 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3436896494 Aug 25 04:20:15 AM UTC 24 Aug 25 04:20:22 AM UTC 24 358622781 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1175119755 Aug 25 04:19:09 AM UTC 24 Aug 25 04:20:38 AM UTC 24 790339924 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2956970081 Aug 25 04:20:41 AM UTC 24 Aug 25 04:20:43 AM UTC 24 40370089 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.968983326 Aug 25 04:19:04 AM UTC 24 Aug 25 04:20:58 AM UTC 24 1308990546 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1790334347 Aug 25 04:20:24 AM UTC 24 Aug 25 04:21:00 AM UTC 24 1278333971 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.219112212 Aug 25 04:20:44 AM UTC 24 Aug 25 04:21:09 AM UTC 24 2004756889 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2348741135 Aug 25 04:17:03 AM UTC 24 Aug 25 04:21:11 AM UTC 24 2563347780 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3268008474 Aug 25 04:20:01 AM UTC 24 Aug 25 04:21:16 AM UTC 24 1997440433 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1529301462 Aug 25 04:19:35 AM UTC 24 Aug 25 04:21:19 AM UTC 24 2413152652 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2759334476 Aug 25 04:21:10 AM UTC 24 Aug 25 04:21:27 AM UTC 24 2702388594 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3785281767 Aug 25 04:18:17 AM UTC 24 Aug 25 04:21:36 AM UTC 24 10005223813 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.965057166 Aug 25 04:21:30 AM UTC 24 Aug 25 04:21:37 AM UTC 24 1343836000 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1802320311 Aug 25 04:20:04 AM UTC 24 Aug 25 04:21:42 AM UTC 24 794929784 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.4162358241 Aug 25 04:21:43 AM UTC 24 Aug 25 04:21:45 AM UTC 24 36844862 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2936028550 Aug 25 04:19:16 AM UTC 24 Aug 25 04:21:50 AM UTC 24 13525118953 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1024008649 Aug 25 04:21:10 AM UTC 24 Aug 25 04:21:56 AM UTC 24 770666038 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.594879092 Aug 25 04:21:12 AM UTC 24 Aug 25 04:21:57 AM UTC 24 8854571832 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.992977465 Aug 25 04:17:10 AM UTC 24 Aug 25 04:21:58 AM UTC 24 64549751251 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2342180580 Aug 25 04:21:46 AM UTC 24 Aug 25 04:22:04 AM UTC 24 1850360043 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1903473946 Aug 25 04:21:00 AM UTC 24 Aug 25 04:22:07 AM UTC 24 1061871596 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3832512930 Aug 25 04:21:27 AM UTC 24 Aug 25 04:22:10 AM UTC 24 7562929966 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3933894218 Aug 25 04:20:11 AM UTC 24 Aug 25 04:22:13 AM UTC 24 37753738321 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1850674151 Aug 25 04:18:45 AM UTC 24 Aug 25 04:22:10 AM UTC 24 4598780105 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.94430762 Aug 25 04:20:17 AM UTC 24 Aug 25 04:22:11 AM UTC 24 2736122416 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1488664569 Aug 25 04:19:25 AM UTC 24 Aug 25 04:22:14 AM UTC 24 10232151732 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.326356999 Aug 25 04:22:14 AM UTC 24 Aug 25 04:22:21 AM UTC 24 485626333 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1498518085 Aug 25 04:17:43 AM UTC 24 Aug 25 04:22:24 AM UTC 24 3010355731 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4272685387 Aug 25 04:22:05 AM UTC 24 Aug 25 04:22:26 AM UTC 24 2904097346 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.1978663899 Aug 25 04:22:27 AM UTC 24 Aug 25 04:22:29 AM UTC 24 11889689 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.2024487495 Aug 25 04:18:37 AM UTC 24 Aug 25 04:22:29 AM UTC 24 4473671035 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3576624938 Aug 25 04:18:44 AM UTC 24 Aug 25 04:22:33 AM UTC 24 38513346814 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4086561910 Aug 25 04:21:38 AM UTC 24 Aug 25 04:22:36 AM UTC 24 3043645975 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.708400746 Aug 25 04:21:59 AM UTC 24 Aug 25 04:22:42 AM UTC 24 734079544 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.1567200293 Aug 25 04:22:30 AM UTC 24 Aug 25 04:22:45 AM UTC 24 856578509 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.104139737 Aug 25 04:22:24 AM UTC 24 Aug 25 04:22:46 AM UTC 24 340160398 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2598082304 Aug 25 04:18:37 AM UTC 24 Aug 25 04:22:59 AM UTC 24 11631238820 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2873391678 Aug 25 04:18:16 AM UTC 24 Aug 25 04:23:06 AM UTC 24 86280804045 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1250707521 Aug 25 04:22:36 AM UTC 24 Aug 25 04:23:12 AM UTC 24 8366297223 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.615288577 Aug 25 04:17:06 AM UTC 24 Aug 25 04:23:14 AM UTC 24 9559721667 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.146098603 Aug 25 04:19:28 AM UTC 24 Aug 25 04:23:20 AM UTC 24 7004436625 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1037810108 Aug 25 04:23:14 AM UTC 24 Aug 25 04:23:22 AM UTC 24 365320655 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.4270352271 Aug 25 04:18:54 AM UTC 24 Aug 25 04:23:27 AM UTC 24 25777612370 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.2202267524 Aug 25 04:17:44 AM UTC 24 Aug 25 04:23:49 AM UTC 24 30316262347 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3616425659 Aug 25 04:21:58 AM UTC 24 Aug 25 04:23:53 AM UTC 24 4021564899 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.4147235185 Aug 25 04:23:54 AM UTC 24 Aug 25 04:23:56 AM UTC 24 13213997 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1877438944 Aug 25 04:17:33 AM UTC 24 Aug 25 04:23:58 AM UTC 24 18113273847 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.2774071653 Aug 25 04:23:57 AM UTC 24 Aug 25 04:24:13 AM UTC 24 742330537 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2925433515 Aug 25 04:22:22 AM UTC 24 Aug 25 04:24:13 AM UTC 24 5786084630 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.4196715684 Aug 25 04:17:54 AM UTC 24 Aug 25 04:24:14 AM UTC 24 41504750685 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.13904243 Aug 25 04:17:29 AM UTC 24 Aug 25 04:24:15 AM UTC 24 8565548405 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.578473613 Aug 25 04:17:21 AM UTC 24 Aug 25 04:24:16 AM UTC 24 21009014179 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.672920673 Aug 25 04:22:08 AM UTC 24 Aug 25 04:24:19 AM UTC 24 36712280585 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1575674226 Aug 25 04:19:44 AM UTC 24 Aug 25 04:24:23 AM UTC 24 3407406991 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3251735409 Aug 25 04:22:43 AM UTC 24 Aug 25 04:24:25 AM UTC 24 3050769728 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2340839594 Aug 25 04:17:15 AM UTC 24 Aug 25 04:24:32 AM UTC 24 16850923366 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1370366784 Aug 25 04:19:02 AM UTC 24 Aug 25 04:24:35 AM UTC 24 3814776998 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.935790889 Aug 25 04:17:09 AM UTC 24 Aug 25 04:24:39 AM UTC 24 37493253294 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.338491589 Aug 25 04:21:34 AM UTC 24 Aug 25 04:24:40 AM UTC 24 3452766560 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.4046663755 Aug 25 04:24:40 AM UTC 24 Aug 25 04:24:46 AM UTC 24 827115501 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.815263382 Aug 25 04:23:28 AM UTC 24 Aug 25 04:24:46 AM UTC 24 2774833320 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.779458039 Aug 25 04:21:32 AM UTC 24 Aug 25 04:24:56 AM UTC 24 13153722065 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3859414973 Aug 25 04:22:47 AM UTC 24 Aug 25 04:25:02 AM UTC 24 3559654733 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.436992371 Aug 25 04:25:03 AM UTC 24 Aug 25 04:25:05 AM UTC 24 172297525 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.3214293059 Aug 25 04:24:15 AM UTC 24 Aug 25 04:25:11 AM UTC 24 2892202880 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2142856018 Aug 25 04:23:22 AM UTC 24 Aug 25 04:25:15 AM UTC 24 2765928937 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.594969653 Aug 25 04:17:17 AM UTC 24 Aug 25 04:25:23 AM UTC 24 9121950946 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3511638915 Aug 25 04:22:34 AM UTC 24 Aug 25 04:25:27 AM UTC 24 11614866258 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1828859643 Aug 25 04:25:24 AM UTC 24 Aug 25 04:25:35 AM UTC 24 417270412 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3973418083 Aug 25 04:17:15 AM UTC 24 Aug 25 04:25:44 AM UTC 24 53483107173 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1218235208 Aug 25 04:18:24 AM UTC 24 Aug 25 04:25:46 AM UTC 24 18967701982 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.252649214 Aug 25 04:19:05 AM UTC 24 Aug 25 04:25:47 AM UTC 24 18802398592 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2724544501 Aug 25 04:22:47 AM UTC 24 Aug 25 04:25:52 AM UTC 24 54729110419 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.166307865 Aug 25 04:24:47 AM UTC 24 Aug 25 04:25:59 AM UTC 24 8721930611 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1495704519 Aug 25 04:17:52 AM UTC 24 Aug 25 04:26:01 AM UTC 24 7044165163 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2684486241 Aug 25 04:24:24 AM UTC 24 Aug 25 04:26:02 AM UTC 24 15579708202 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.403072091 Aug 25 04:25:36 AM UTC 24 Aug 25 04:26:07 AM UTC 24 1469478825 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3554572340 Aug 25 04:26:02 AM UTC 24 Aug 25 04:26:08 AM UTC 24 345980029 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2508852046 Aug 25 04:25:06 AM UTC 24 Aug 25 04:26:10 AM UTC 24 879424080 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3682622135 Aug 25 04:24:19 AM UTC 24 Aug 25 04:26:15 AM UTC 24 3000427335 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2267924108 Aug 25 04:26:16 AM UTC 24 Aug 25 04:26:18 AM UTC 24 88591598 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.450101058 Aug 25 04:24:16 AM UTC 24 Aug 25 04:26:22 AM UTC 24 3044566101 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3611006602 Aug 25 04:26:09 AM UTC 24 Aug 25 04:26:28 AM UTC 24 417622868 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.302803626 Aug 25 04:21:51 AM UTC 24 Aug 25 04:26:30 AM UTC 24 18908536796 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.2138242754 Aug 25 04:17:17 AM UTC 24 Aug 25 04:26:40 AM UTC 24 11214555256 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.402549860 Aug 25 04:17:53 AM UTC 24 Aug 25 04:26:44 AM UTC 24 19865056944 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2073009531 Aug 25 04:19:49 AM UTC 24 Aug 25 04:26:44 AM UTC 24 29088702858 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.856231517 Aug 25 04:24:47 AM UTC 24 Aug 25 04:26:44 AM UTC 24 2910420646 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2078236709 Aug 25 04:18:27 AM UTC 24 Aug 25 04:27:22 AM UTC 24 219602488453 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.1143195260 Aug 25 04:26:19 AM UTC 24 Aug 25 04:27:35 AM UTC 24 1153441120 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1552592675 Aug 25 04:21:00 AM UTC 24 Aug 25 04:27:36 AM UTC 24 47891281726 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2289536748 Aug 25 04:26:41 AM UTC 24 Aug 25 04:27:38 AM UTC 24 1098666194 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.406577545 Aug 25 04:26:45 AM UTC 24 Aug 25 04:27:45 AM UTC 24 1480980172 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.603551458 Aug 25 04:27:39 AM UTC 24 Aug 25 04:27:47 AM UTC 24 1976486365 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.229024286 Aug 25 04:23:21 AM UTC 24 Aug 25 04:27:48 AM UTC 24 28800251974 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.545499015 Aug 25 04:22:14 AM UTC 24 Aug 25 04:27:51 AM UTC 24 16424191515 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1496127815 Aug 25 04:27:55 AM UTC 24 Aug 25 04:27:57 AM UTC 24 15479218 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3825644205 Aug 25 04:20:16 AM UTC 24 Aug 25 04:27:58 AM UTC 24 18150367258 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1517957200 Aug 25 04:27:58 AM UTC 24 Aug 25 04:28:05 AM UTC 24 361837506 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2379424004 Aug 25 04:25:44 AM UTC 24 Aug 25 04:28:02 AM UTC 24 810212503 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3202463742 Aug 25 04:27:14 AM UTC 24 Aug 25 04:28:10 AM UTC 24 21999545202 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.1975261429 Aug 25 04:17:08 AM UTC 24 Aug 25 04:28:16 AM UTC 24 68398157637 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.2391169784 Aug 25 04:25:46 AM UTC 24 Aug 25 04:28:19 AM UTC 24 34411819900 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2235033437 Aug 25 04:22:39 AM UTC 24 Aug 25 04:28:27 AM UTC 24 53598343187 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3353085565 Aug 25 04:27:49 AM UTC 24 Aug 25 04:28:28 AM UTC 24 1688772029 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1953357442 Aug 25 04:26:45 AM UTC 24 Aug 25 04:28:38 AM UTC 24 4348001007 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.597292878 Aug 25 04:28:12 AM UTC 24 Aug 25 04:28:40 AM UTC 24 1310000073 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2063932 Aug 25 04:20:59 AM UTC 24 Aug 25 04:28:41 AM UTC 24 20025974463 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.3821645749 Aug 25 04:17:14 AM UTC 24 Aug 25 04:28:47 AM UTC 24 49560915287 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1740441251 Aug 25 04:28:29 AM UTC 24 Aug 25 04:28:49 AM UTC 24 5029481304 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.413163526 Aug 25 04:28:48 AM UTC 24 Aug 25 04:28:55 AM UTC 24 365535484 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3966712747 Aug 25 04:17:43 AM UTC 24 Aug 25 04:28:56 AM UTC 24 22222777897 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1096528887 Aug 25 04:26:03 AM UTC 24 Aug 25 04:28:56 AM UTC 24 1998735620 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1091922266 Aug 25 04:28:57 AM UTC 24 Aug 25 04:29:12 AM UTC 24 636481415 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.623937066 Aug 25 04:22:11 AM UTC 24 Aug 25 04:29:14 AM UTC 24 54375355747 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2186323663 Aug 25 04:29:13 AM UTC 24 Aug 25 04:29:15 AM UTC 24 52489012 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3758737954 Aug 25 04:24:27 AM UTC 24 Aug 25 04:29:17 AM UTC 24 16191703750 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3202071174 Aug 25 04:27:49 AM UTC 24 Aug 25 04:29:26 AM UTC 24 2860073885 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.4249640193 Aug 25 04:29:15 AM UTC 24 Aug 25 04:29:43 AM UTC 24 907330710 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1458020354 Aug 25 04:28:28 AM UTC 24 Aug 25 04:29:48 AM UTC 24 4720044032 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3713697213 Aug 25 04:26:08 AM UTC 24 Aug 25 04:29:52 AM UTC 24 4382586862 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.2100152315 Aug 25 04:29:43 AM UTC 24 Aug 25 04:29:58 AM UTC 24 4455620554 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3715190930 Aug 25 04:28:20 AM UTC 24 Aug 25 04:30:06 AM UTC 24 3196677824 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.363443922 Aug 25 04:22:31 AM UTC 24 Aug 25 04:30:10 AM UTC 24 4535466519 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.639061507 Aug 25 04:24:41 AM UTC 24 Aug 25 04:30:11 AM UTC 24 16419966540 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3829609807 Aug 25 04:29:53 AM UTC 24 Aug 25 04:30:40 AM UTC 24 3497144773 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1613979230 Aug 25 04:30:41 AM UTC 24 Aug 25 04:30:47 AM UTC 24 2583009496 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1124819189 Aug 25 04:18:09 AM UTC 24 Aug 25 04:30:59 AM UTC 24 10545330225 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.2343715646 Aug 25 04:30:01 AM UTC 24 Aug 25 04:31:00 AM UTC 24 26384465164 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1624536892 Aug 25 04:17:29 AM UTC 24 Aug 25 04:31:07 AM UTC 24 47240293215 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1010463185 Aug 25 04:31:01 AM UTC 24 Aug 25 04:31:18 AM UTC 24 262374397 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2636362827 Aug 25 04:31:19 AM UTC 24 Aug 25 04:31:21 AM UTC 24 24409769 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.3060944524 Aug 25 04:29:58 AM UTC 24 Aug 25 04:31:29 AM UTC 24 1425111125 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3209099047 Aug 25 04:20:13 AM UTC 24 Aug 25 04:31:31 AM UTC 24 75681998375 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.356457568 Aug 25 04:21:58 AM UTC 24 Aug 25 04:31:38 AM UTC 24 12928718749 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.75042562 Aug 25 04:28:49 AM UTC 24 Aug 25 04:31:45 AM UTC 24 4032297317 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1036850517 Aug 25 04:24:16 AM UTC 24 Aug 25 04:31:49 AM UTC 24 5961428114 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.1696023911 Aug 25 04:31:22 AM UTC 24 Aug 25 04:31:54 AM UTC 24 8243361772 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3006349732 Aug 25 04:31:46 AM UTC 24 Aug 25 04:31:57 AM UTC 24 1055263423 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1730171531 Aug 25 04:26:30 AM UTC 24 Aug 25 04:32:04 AM UTC 24 4480823714 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.876039720 Aug 25 04:25:16 AM UTC 24 Aug 25 04:32:05 AM UTC 24 4762188351 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.2256654957 Aug 25 04:24:14 AM UTC 24 Aug 25 04:32:07 AM UTC 24 19384507574 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3094011250 Aug 25 04:31:56 AM UTC 24 Aug 25 04:32:24 AM UTC 24 5874896227 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1652398461 Aug 25 04:32:25 AM UTC 24 Aug 25 04:32:32 AM UTC 24 694993387 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.63521667 Aug 25 04:18:11 AM UTC 24 Aug 25 04:32:46 AM UTC 24 55021215414 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1733756515 Aug 25 04:31:58 AM UTC 24 Aug 25 04:33:06 AM UTC 24 809089592 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1667670577 Aug 25 04:28:55 AM UTC 24 Aug 25 04:33:16 AM UTC 24 20924274873 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3255221877 Aug 25 04:33:07 AM UTC 24 Aug 25 04:33:53 AM UTC 24 1161479776 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.548426945 Aug 25 04:18:21 AM UTC 24 Aug 25 04:33:55 AM UTC 24 44817642141 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.877904622 Aug 25 04:33:54 AM UTC 24 Aug 25 04:33:56 AM UTC 24 38974171 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1655128759 Aug 25 04:32:04 AM UTC 24 Aug 25 04:34:04 AM UTC 24 48335395570 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.1152901837 Aug 25 04:33:56 AM UTC 24 Aug 25 04:34:04 AM UTC 24 1119308814 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.677262756 Aug 25 04:25:28 AM UTC 24 Aug 25 04:34:11 AM UTC 24 54677206846 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1912372471 Aug 25 04:34:12 AM UTC 24 Aug 25 04:34:20 AM UTC 24 735050009 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1958780201 Aug 25 04:27:47 AM UTC 24 Aug 25 04:34:27 AM UTC 24 98588578618 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2947588435 Aug 25 04:18:06 AM UTC 24 Aug 25 04:34:34 AM UTC 24 32545840824 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1599353313 Aug 25 04:32:46 AM UTC 24 Aug 25 04:34:37 AM UTC 24 2656697465 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.935181072 Aug 25 04:30:59 AM UTC 24 Aug 25 04:34:42 AM UTC 24 18945265161 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3113470280 Aug 25 04:34:35 AM UTC 24 Aug 25 04:35:02 AM UTC 24 744228550 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2546555067 Aug 25 04:34:28 AM UTC 24 Aug 25 04:35:04 AM UTC 24 1451838017 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1436593727 Aug 25 04:17:09 AM UTC 24 Aug 25 04:35:07 AM UTC 24 10319692205 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.172981408 Aug 25 04:35:08 AM UTC 24 Aug 25 04:35:13 AM UTC 24 681354886 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1062480705 Aug 25 04:17:08 AM UTC 24 Aug 25 04:35:25 AM UTC 24 39680657265 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2275862435 Aug 25 04:32:07 AM UTC 24 Aug 25 04:35:37 AM UTC 24 5062510015 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3441246566 Aug 25 04:25:12 AM UTC 24 Aug 25 04:35:41 AM UTC 24 100435172667 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.84440280 Aug 25 04:32:33 AM UTC 24 Aug 25 04:35:43 AM UTC 24 10963592141 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.158932442 Aug 25 04:30:12 AM UTC 24 Aug 25 04:35:43 AM UTC 24 11613418931 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.225927595 Aug 25 04:36:49 AM UTC 24 Aug 25 04:36:56 AM UTC 24 1352572889 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.4094721660 Aug 25 04:34:38 AM UTC 24 Aug 25 04:35:44 AM UTC 24 7166750420 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3087910466 Aug 25 04:35:44 AM UTC 24 Aug 25 04:35:46 AM UTC 24 24031534 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.2723942126 Aug 25 04:35:44 AM UTC 24 Aug 25 04:36:03 AM UTC 24 1591563153 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.953160204 Aug 25 04:29:27 AM UTC 24 Aug 25 04:36:03 AM UTC 24 4308478337 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1095101373 Aug 25 04:26:44 AM UTC 24 Aug 25 04:36:06 AM UTC 24 44532755795 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.4027209879 Aug 25 04:20:57 AM UTC 24 Aug 25 04:37:06 AM UTC 24 46459365474 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2950772284 Aug 25 04:35:38 AM UTC 24 Aug 25 04:36:08 AM UTC 24 722958875 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2134891447 Aug 25 04:36:04 AM UTC 24 Aug 25 04:36:18 AM UTC 24 488336925 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2854626297 Aug 25 04:21:17 AM UTC 24 Aug 25 04:36:20 AM UTC 24 13077878387 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.4040629930 Aug 25 04:23:00 AM UTC 24 Aug 25 04:36:36 AM UTC 24 28773790572 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.3562938168 Aug 25 04:36:10 AM UTC 24 Aug 25 04:36:38 AM UTC 24 3511710926 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1077598910 Aug 25 04:36:19 AM UTC 24 Aug 25 04:36:41 AM UTC 24 748910459 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1777091695 Aug 25 04:36:21 AM UTC 24 Aug 25 04:36:48 AM UTC 24 8316380251 ps
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T298 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1357621312 Aug 25 04:28:05 AM UTC 24 Aug 25 04:36:59 AM UTC 24 13063765374 ps
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T300 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3117906169 Aug 25 04:37:07 AM UTC 24 Aug 25 04:37:09 AM UTC 24 17305761 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.4095898543 Aug 25 04:30:48 AM UTC 24 Aug 25 04:37:15 AM UTC 24 39393766608 ps
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T305 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2358128834 Aug 25 04:39:17 AM UTC 24 Aug 25 04:39:35 AM UTC 24 721352749 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3867049730 Aug 25 04:35:26 AM UTC 24 Aug 25 04:39:36 AM UTC 24 5182541188 ps
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T309 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3967101625 Aug 25 04:21:50 AM UTC 24 Aug 25 04:39:48 AM UTC 24 20609890230 ps
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