Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	353275838	1			T1	1976		T4	1022		T5	1368
instr_valid_dis	314745673	1			T1	1976		T4	1022		T5	1368
instr_en	30037866	1			T26	203580		T19	211752		T20	52178

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11942079	1			T19	96936		T20	31728		T132	54964
sram_ifetch_valid_disable	310942938	1			T1	1976		T4	1022		T5	1368
sram_ifetch_enable	30390821	1			T26	107346		T19	27214		T20	168202

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	353275838	1			T1	1976		T4	1022		T5	1368
hw_debug_en_valid_off	318627188	1			T1	1976		T4	1022		T5	1368
hw_debug_en_on	22283734	1			T26	42052		T19	50434		T20	183730

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	310942938	1			T1	1976		T4	1022		T5	1368
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	293320787	1			T1	1976		T4	1022		T5	1368
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13642510	1			T26	111482		T19	87602		T133	22744
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5507332	1			T19	51784		T20	31728		T132	54964
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3422174	1			T20	31728		T136	12428		T143	2610
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1595466	1			T19	51784		T132	54964		T134	17128
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4556467	1			T19	45152		T133	42188		T134	130886
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2163141	1			T133	22188		T21	67170		T143	32578
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1656286	1			T19	45152		T134	130886		T135	42558
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8524824	1			T19	5282		T20	37762		T134	42472
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3446268	1			T20	37762		T134	6364		T147	112200
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3400114	1			T19	5282		T134	3406		T136	16230

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12349892	1			T26	92098		T19	27214		T20	52178
lc_exec_en	9202443	1			T26	42052		T20	145968		T39	1988
valid_exec_dis	312840541	1			T1	1976		T4	1022		T5	1368
invalid_exec_dis	42332900	1			T26	107346		T19	124150		T20	199930