Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1036
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
68.75 68.75 86.75 86.75 66.23 66.23 87.57 87.57 9.52 9.52 72.04 72.04 92.98 92.98 66.18 66.18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.809541380
80.86 12.11 91.50 4.74 69.79 3.55 88.40 0.83 76.19 66.67 79.86 7.82 93.57 0.58 66.73 0.55 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3453944806
91.23 10.37 98.28 6.79 82.70 12.91 96.87 8.47 100.00 23.81 91.47 11.61 96.20 2.63 73.13 6.40 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3060649528
92.81 1.58 98.53 0.25 85.55 2.84 97.07 0.21 100.00 0.00 93.36 1.90 96.20 0.00 78.98 5.85 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3850478350
93.94 1.13 98.86 0.33 88.51 2.96 98.04 0.96 100.00 0.00 95.50 2.13 96.78 0.58 79.89 0.91 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2976232735
94.80 0.87 99.10 0.25 89.81 1.30 98.04 0.00 100.00 0.00 96.21 0.71 96.93 0.15 83.55 3.66 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.348749038
95.62 0.82 99.10 0.00 90.40 0.59 98.04 0.00 100.00 0.00 96.21 0.00 96.93 0.00 88.67 5.12 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.34894016
96.06 0.44 99.10 0.00 90.40 0.00 98.73 0.69 100.00 0.00 96.21 0.00 96.93 0.00 91.04 2.38 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3651800691
96.37 0.31 99.10 0.00 90.40 0.00 98.73 0.00 100.00 0.00 96.21 0.00 96.93 0.00 93.24 2.19 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.99522684
96.62 0.25 99.10 0.00 90.52 0.12 98.73 0.00 100.00 0.00 96.21 0.00 97.81 0.88 93.97 0.73 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.60364901
96.82 0.20 99.10 0.00 90.64 0.12 98.73 0.00 100.00 0.00 96.21 0.00 97.81 0.00 95.25 1.28 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.4246921372
96.95 0.14 99.10 0.00 90.64 0.00 98.79 0.07 100.00 0.00 96.21 0.00 98.68 0.88 95.25 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4068693441
97.09 0.13 99.18 0.08 90.64 0.00 99.66 0.86 100.00 0.00 96.21 0.00 98.68 0.00 95.25 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4020235310
97.19 0.10 99.18 0.00 90.64 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.68 0.00 95.98 0.73 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4253126571
97.27 0.08 99.18 0.00 90.64 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.68 0.00 96.53 0.55 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.981480895
97.35 0.08 99.18 0.00 90.64 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.68 0.00 97.07 0.55 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.44317683
97.41 0.06 99.18 0.00 90.64 0.00 99.66 0.00 100.00 0.00 96.21 0.00 99.12 0.44 97.07 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2981476784
97.47 0.06 99.18 0.00 91.00 0.36 99.72 0.07 100.00 0.00 96.21 0.00 99.12 0.00 97.07 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.4020757151
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.132736413
97.52 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.3104391943

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3716361470
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.702638983
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1226283345
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3752227975
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.892124477
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.172406157
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3031291771
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1343950765
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4049189694
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.977873247
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1776813077
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.169449794
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1504774727
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2659653469
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.654096026
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.976463127
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2062031042
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2193362628
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3752155631
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1809292892
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1054699198
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2119052522
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.903628793
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3187837628
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3816851481
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3300632684
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.576722772
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1593781621
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2850362126
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1902567185
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2239128285
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.72588142
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3903200354
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1826570987
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.229369782
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.568322927
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3828572357
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2178564129
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2441681637
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1990679409
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.342818615
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1738840872
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1788006234
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3145757636
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1533899808
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.113850220
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2625886888
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1826711260
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.736921295
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1907500762
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.233048986
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1715750608
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4056400112
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1883226515
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1917912130
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1524564288
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1520029682
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4157372442
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.984396136
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.167869489
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2941366143
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1881724213
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1320820185
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3335165318
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3866804630
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2114376464
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3681454282
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2367585365
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3471049895
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2177622371
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2012627842
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.926030965
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.890562792
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.713399068
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.530682585
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3123284475
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1885950402
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.141893467
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3514024191
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3299412675
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1966666389
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.713662752
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2923191555
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1351018520
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1726200731
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4016925184
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.201021723
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3585153715
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.743636129
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3360647702
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3494113378
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/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.4102940417
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/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1996497270
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1628342877
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.3315622674
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.401520384
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.605699543
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2890150704
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3816999863
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3111638074
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3223909849
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1524013445
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2451184021
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1793910079
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2489605666
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.4159896199
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1389464225
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.178162618
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.777890033
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.335570919
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2238439207
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3863179216
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.862670098
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3716161811
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.739250126
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3999617061
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2288395139
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2083842485
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.767811342
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2389649620
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1683812167
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1906602590
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.77346993
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2104419772
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2961511271
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2943986135
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3964437365
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3332191716
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2741632406
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2878178083
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.672227956
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2729861241
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.242568802
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.4172317299
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3688433504
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1500901137
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1175625183
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1520566936
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2109418018
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.791416671
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3426953654
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.974116950
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.92345457
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3106488459
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3587988635
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2596323350
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3030579434
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2964738202
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.4206610689
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.4047692460
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.799751603
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2644352617
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1363958258



Total test records in report: 1036
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2811791043 Aug 27 09:19:16 AM UTC 24 Aug 27 09:19:21 AM UTC 24 969721984 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.4020757151 Aug 27 09:19:20 AM UTC 24 Aug 27 09:19:22 AM UTC 24 14375125 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4020235310 Aug 27 09:19:16 AM UTC 24 Aug 27 09:19:24 AM UTC 24 1537151530 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.2262525827 Aug 27 09:19:14 AM UTC 24 Aug 27 09:19:25 AM UTC 24 4662233765 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2941677850 Aug 27 09:19:14 AM UTC 24 Aug 27 09:19:25 AM UTC 24 9585365649 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.636632588 Aug 27 09:19:14 AM UTC 24 Aug 27 09:19:27 AM UTC 24 808027472 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.809541380 Aug 27 09:19:16 AM UTC 24 Aug 27 09:19:29 AM UTC 24 373726364 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.125076536 Aug 27 09:19:22 AM UTC 24 Aug 27 09:19:47 AM UTC 24 995441679 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2401288894 Aug 27 09:19:30 AM UTC 24 Aug 27 09:19:57 AM UTC 24 716783271 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2783928521 Aug 27 09:19:28 AM UTC 24 Aug 27 09:20:00 AM UTC 24 739229164 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3060649528 Aug 27 09:19:33 AM UTC 24 Aug 27 09:20:06 AM UTC 24 6683004241 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1105889502 Aug 27 09:19:26 AM UTC 24 Aug 27 09:20:08 AM UTC 24 4635032490 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.979265955 Aug 27 09:20:07 AM UTC 24 Aug 27 09:20:14 AM UTC 24 1531772934 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.4227460620 Aug 27 09:19:14 AM UTC 24 Aug 27 09:20:41 AM UTC 24 798659155 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2976232735 Aug 27 09:20:42 AM UTC 24 Aug 27 09:20:48 AM UTC 24 488461073 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2442055819 Aug 27 09:20:48 AM UTC 24 Aug 27 09:20:50 AM UTC 24 74362128 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2002766943 Aug 27 09:20:49 AM UTC 24 Aug 27 09:20:55 AM UTC 24 370296124 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1626901457 Aug 27 09:19:14 AM UTC 24 Aug 27 09:21:04 AM UTC 24 21026154259 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.60364901 Aug 27 09:19:16 AM UTC 24 Aug 27 09:21:41 AM UTC 24 3428915240 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1620869505 Aug 27 09:21:26 AM UTC 24 Aug 27 09:21:45 AM UTC 24 871276392 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2842177779 Aug 27 09:19:14 AM UTC 24 Aug 27 09:21:57 AM UTC 24 11327782401 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3651800691 Aug 27 09:20:15 AM UTC 24 Aug 27 09:22:56 AM UTC 24 12114919031 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2305097557 Aug 27 09:20:51 AM UTC 24 Aug 27 09:23:01 AM UTC 24 10472419584 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1022628815 Aug 27 09:20:09 AM UTC 24 Aug 27 09:23:14 AM UTC 24 5056894267 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.1492522244 Aug 27 09:19:16 AM UTC 24 Aug 27 09:23:14 AM UTC 24 4535715989 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3095143270 Aug 27 09:23:09 AM UTC 24 Aug 27 09:23:15 AM UTC 24 675854971 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.127801419 Aug 27 09:19:14 AM UTC 24 Aug 27 09:23:17 AM UTC 24 3530229729 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1631928411 Aug 27 09:23:21 AM UTC 24 Aug 27 09:23:25 AM UTC 24 397934721 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1872751520 Aug 27 09:23:26 AM UTC 24 Aug 27 09:23:28 AM UTC 24 13382655 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2903429825 Aug 27 09:23:15 AM UTC 24 Aug 27 09:23:34 AM UTC 24 763423895 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.121776804 Aug 27 09:21:58 AM UTC 24 Aug 27 09:23:37 AM UTC 24 810895871 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2934133854 Aug 27 09:23:26 AM UTC 24 Aug 27 09:23:44 AM UTC 24 4499151231 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.3533527247 Aug 27 09:20:09 AM UTC 24 Aug 27 09:23:46 AM UTC 24 2634388762 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.4070944932 Aug 27 09:21:46 AM UTC 24 Aug 27 09:23:56 AM UTC 24 1666128624 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1952346403 Aug 27 09:21:04 AM UTC 24 Aug 27 09:24:08 AM UTC 24 13462169470 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.1759458441 Aug 27 09:19:26 AM UTC 24 Aug 27 09:24:41 AM UTC 24 20719879587 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2049001564 Aug 27 09:22:18 AM UTC 24 Aug 27 09:24:49 AM UTC 24 77676022032 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3042370524 Aug 27 09:23:15 AM UTC 24 Aug 27 09:24:50 AM UTC 24 961738143 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.2398656609 Aug 27 09:24:09 AM UTC 24 Aug 27 09:25:10 AM UTC 24 1530902453 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.779374832 Aug 27 09:19:27 AM UTC 24 Aug 27 09:25:29 AM UTC 24 24890548474 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3678469177 Aug 27 09:23:57 AM UTC 24 Aug 27 09:25:30 AM UTC 24 2725265155 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.924144350 Aug 27 09:25:29 AM UTC 24 Aug 27 09:25:38 AM UTC 24 1123499847 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1119199975 Aug 27 09:23:45 AM UTC 24 Aug 27 09:25:44 AM UTC 24 1294690641 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3539542312 Aug 27 09:25:44 AM UTC 24 Aug 27 09:26:08 AM UTC 24 470909457 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2308582477 Aug 27 09:26:19 AM UTC 24 Aug 27 09:26:24 AM UTC 24 845338684 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1367854097 Aug 27 09:26:25 AM UTC 24 Aug 27 09:26:27 AM UTC 24 13730052 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.3186858413 Aug 27 09:19:14 AM UTC 24 Aug 27 09:26:57 AM UTC 24 12492954905 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1858793828 Aug 27 09:24:43 AM UTC 24 Aug 27 09:26:59 AM UTC 24 64421591634 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.3258671513 Aug 27 09:26:28 AM UTC 24 Aug 27 09:27:06 AM UTC 24 2327222107 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1693108904 Aug 27 09:27:01 AM UTC 24 Aug 27 09:27:11 AM UTC 24 1342708856 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.333558390 Aug 27 09:25:39 AM UTC 24 Aug 27 09:27:25 AM UTC 24 4041740227 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3645921672 Aug 27 09:27:19 AM UTC 24 Aug 27 09:27:32 AM UTC 24 2799139710 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.4064882265 Aug 27 09:19:16 AM UTC 24 Aug 27 09:28:03 AM UTC 24 7488402930 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3937459900 Aug 27 09:27:12 AM UTC 24 Aug 27 09:28:10 AM UTC 24 3314565855 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3040207955 Aug 27 09:23:38 AM UTC 24 Aug 27 09:28:12 AM UTC 24 9422100879 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3240706034 Aug 27 09:28:13 AM UTC 24 Aug 27 09:28:20 AM UTC 24 611775156 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.348749038 Aug 27 09:19:14 AM UTC 24 Aug 27 09:28:27 AM UTC 24 69029665598 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1334098756 Aug 27 09:28:54 AM UTC 24 Aug 27 09:29:02 AM UTC 24 591488782 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.4246921372 Aug 27 09:27:26 AM UTC 24 Aug 27 09:29:21 AM UTC 24 11046289926 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1317886523 Aug 27 09:21:42 AM UTC 24 Aug 27 09:29:26 AM UTC 24 32328570445 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.2506052358 Aug 27 09:29:22 AM UTC 24 Aug 27 09:29:27 AM UTC 24 964810713 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.404041122 Aug 27 09:29:27 AM UTC 24 Aug 27 09:29:29 AM UTC 24 13950029 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1543680016 Aug 27 09:23:14 AM UTC 24 Aug 27 09:29:35 AM UTC 24 71735325416 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.4191100561 Aug 27 09:29:28 AM UTC 24 Aug 27 09:29:40 AM UTC 24 1369233433 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3850478350 Aug 27 09:20:01 AM UTC 24 Aug 27 09:29:45 AM UTC 24 41830303414 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.770146776 Aug 27 09:29:46 AM UTC 24 Aug 27 09:30:09 AM UTC 24 1758309458 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2660850884 Aug 27 09:30:19 AM UTC 24 Aug 27 09:30:36 AM UTC 24 2784827156 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1097065571 Aug 27 09:28:12 AM UTC 24 Aug 27 09:30:56 AM UTC 24 8718254894 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.3975567874 Aug 27 09:19:14 AM UTC 24 Aug 27 09:31:01 AM UTC 24 7573400242 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2662322735 Aug 27 09:30:29 AM UTC 24 Aug 27 09:31:04 AM UTC 24 2717418469 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.630846068 Aug 27 09:28:28 AM UTC 24 Aug 27 09:31:09 AM UTC 24 5167948343 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.784911170 Aug 27 09:31:10 AM UTC 24 Aug 27 09:31:17 AM UTC 24 1862148305 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3994880437 Aug 27 09:29:30 AM UTC 24 Aug 27 09:31:34 AM UTC 24 5881205175 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.4010085115 Aug 27 09:23:46 AM UTC 24 Aug 27 09:31:54 AM UTC 24 64163402761 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2435255794 Aug 27 09:30:36 AM UTC 24 Aug 27 09:31:55 AM UTC 24 32538106872 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3453944806 Aug 27 09:31:55 AM UTC 24 Aug 27 09:32:23 AM UTC 24 2423069051 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.919381540 Aug 27 09:28:21 AM UTC 24 Aug 27 09:32:24 AM UTC 24 3946647049 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2198808021 Aug 27 09:32:24 AM UTC 24 Aug 27 09:32:26 AM UTC 24 15052358 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3935393371 Aug 27 09:27:32 AM UTC 24 Aug 27 09:32:38 AM UTC 24 6721298262 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.4005801016 Aug 27 09:26:58 AM UTC 24 Aug 27 09:33:13 AM UTC 24 64590082660 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.4104406547 Aug 27 09:28:04 AM UTC 24 Aug 27 09:33:15 AM UTC 24 40855289259 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3309504777 Aug 27 09:33:16 AM UTC 24 Aug 27 09:33:33 AM UTC 24 1008921486 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.4276685895 Aug 27 09:22:52 AM UTC 24 Aug 27 09:33:45 AM UTC 24 10815162207 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.3315622674 Aug 27 09:32:25 AM UTC 24 Aug 27 09:34:05 AM UTC 24 3736517879 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2538145348 Aug 27 09:25:31 AM UTC 24 Aug 27 09:34:08 AM UTC 24 55302235993 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1976953782 Aug 27 09:23:29 AM UTC 24 Aug 27 09:34:33 AM UTC 24 11527524082 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.535896960 Aug 27 09:31:35 AM UTC 24 Aug 27 09:34:34 AM UTC 24 11184455277 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3816999863 Aug 27 09:34:06 AM UTC 24 Aug 27 09:34:45 AM UTC 24 747123469 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1151091899 Aug 27 09:24:50 AM UTC 24 Aug 27 09:35:04 AM UTC 24 23538150092 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.518278694 Aug 27 09:31:19 AM UTC 24 Aug 27 09:35:07 AM UTC 24 14150583969 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1996497270 Aug 27 09:35:05 AM UTC 24 Aug 27 09:35:13 AM UTC 24 705561661 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.4102940417 Aug 27 09:33:46 AM UTC 24 Aug 27 09:35:19 AM UTC 24 3594478394 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.2432959245 Aug 27 09:22:57 AM UTC 24 Aug 27 09:35:30 AM UTC 24 35195516343 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.837429397 Aug 27 09:35:33 AM UTC 24 Aug 27 09:35:35 AM UTC 24 32717571 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.862670098 Aug 27 09:35:36 AM UTC 24 Aug 27 09:35:46 AM UTC 24 521761659 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.74654059 Aug 27 09:29:41 AM UTC 24 Aug 27 09:35:59 AM UTC 24 10943626107 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.605699543 Aug 27 09:35:20 AM UTC 24 Aug 27 09:36:10 AM UTC 24 1179632000 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.99522684 Aug 27 09:24:51 AM UTC 24 Aug 27 09:36:40 AM UTC 24 56832698365 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.721413803 Aug 27 09:30:09 AM UTC 24 Aug 27 09:36:48 AM UTC 24 14731254968 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2394232380 Aug 27 09:34:09 AM UTC 24 Aug 27 09:36:53 AM UTC 24 13570616365 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.777890033 Aug 27 09:36:41 AM UTC 24 Aug 27 09:37:02 AM UTC 24 611079881 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2356797515 Aug 27 09:19:23 AM UTC 24 Aug 27 09:37:13 AM UTC 24 70620027287 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.1785863792 Aug 27 09:31:01 AM UTC 24 Aug 27 09:37:37 AM UTC 24 10136156944 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1793910079 Aug 27 09:37:13 AM UTC 24 Aug 27 09:37:38 AM UTC 24 2883419857 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4253126571 Aug 27 09:25:10 AM UTC 24 Aug 27 09:37:41 AM UTC 24 59605818190 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2288395139 Aug 27 09:37:02 AM UTC 24 Aug 27 09:37:57 AM UTC 24 4391765714 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2238439207 Aug 27 09:37:58 AM UTC 24 Aug 27 09:38:04 AM UTC 24 1344187307 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2489605666 Aug 27 09:36:54 AM UTC 24 Aug 27 09:38:19 AM UTC 24 3199847927 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2525547957 Aug 27 09:35:14 AM UTC 24 Aug 27 09:38:23 AM UTC 24 42724366976 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.739250126 Aug 27 09:38:23 AM UTC 24 Aug 27 09:38:38 AM UTC 24 442339763 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2890150704 Aug 27 09:33:13 AM UTC 24 Aug 27 09:38:41 AM UTC 24 18046379031 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3223909849 Aug 27 09:38:41 AM UTC 24 Aug 27 09:38:43 AM UTC 24 34658714 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.672227956 Aug 27 09:38:44 AM UTC 24 Aug 27 09:38:53 AM UTC 24 1694251846 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.1179477453 Aug 27 09:19:58 AM UTC 24 Aug 27 09:39:22 AM UTC 24 20345604805 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1466713011 Aug 27 09:19:48 AM UTC 24 Aug 27 09:39:25 AM UTC 24 19014507450 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2576010412 Aug 27 09:26:42 AM UTC 24 Aug 27 09:39:34 AM UTC 24 8460637882 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.810159406 Aug 27 09:27:07 AM UTC 24 Aug 27 09:40:00 AM UTC 24 103297334475 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3964437365 Aug 27 09:39:35 AM UTC 24 Aug 27 09:40:12 AM UTC 24 1607691811 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.77346993 Aug 27 09:40:01 AM UTC 24 Aug 27 09:40:35 AM UTC 24 2962632343 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3015287330 Aug 27 09:30:57 AM UTC 24 Aug 27 09:40:41 AM UTC 24 26406815340 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.4160074972 Aug 27 09:26:57 AM UTC 24 Aug 27 09:40:43 AM UTC 24 42937796037 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.4159896199 Aug 27 09:38:20 AM UTC 24 Aug 27 09:40:54 AM UTC 24 10865248274 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.52495370 Aug 27 09:23:02 AM UTC 24 Aug 27 09:41:09 AM UTC 24 70088763487 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3688433504 Aug 27 09:40:12 AM UTC 24 Aug 27 09:41:12 AM UTC 24 5369996282 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.335570919 Aug 27 09:36:48 AM UTC 24 Aug 27 09:41:17 AM UTC 24 4957191731 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2741632406 Aug 27 09:41:11 AM UTC 24 Aug 27 09:41:17 AM UTC 24 1409629638 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.242568802 Aug 27 09:41:18 AM UTC 24 Aug 27 09:41:52 AM UTC 24 1679000070 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3999617061 Aug 27 09:36:11 AM UTC 24 Aug 27 09:42:19 AM UTC 24 58278410388 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.767811342 Aug 27 09:42:20 AM UTC 24 Aug 27 09:42:22 AM UTC 24 61740027 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.4206610689 Aug 27 09:42:23 AM UTC 24 Aug 27 09:42:35 AM UTC 24 2810784908 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2878178083 Aug 27 09:40:54 AM UTC 24 Aug 27 09:42:35 AM UTC 24 9628349214 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2104419772 Aug 27 09:41:18 AM UTC 24 Aug 27 09:42:53 AM UTC 24 4010301251 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2943986135 Aug 27 09:38:53 AM UTC 24 Aug 27 09:42:59 AM UTC 24 50932175935 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3587988635 Aug 27 09:42:53 AM UTC 24 Aug 27 09:43:16 AM UTC 24 1292391198 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1906602590 Aug 27 09:40:35 AM UTC 24 Aug 27 09:43:18 AM UTC 24 58821385786 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.4026657894 Aug 27 09:19:14 AM UTC 24 Aug 27 09:43:23 AM UTC 24 86433982950 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1363958258 Aug 27 09:43:19 AM UTC 24 Aug 27 09:43:33 AM UTC 24 2832503005 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.2776458878 Aug 27 09:32:39 AM UTC 24 Aug 27 09:43:41 AM UTC 24 23304232807 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.791416671 Aug 27 09:43:24 AM UTC 24 Aug 27 09:43:53 AM UTC 24 1869485838 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.4080145115 Aug 27 09:35:08 AM UTC 24 Aug 27 09:43:54 AM UTC 24 21336353148 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3426953654 Aug 27 09:43:17 AM UTC 24 Aug 27 09:43:57 AM UTC 24 756752482 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3030579434 Aug 27 09:43:54 AM UTC 24 Aug 27 09:43:59 AM UTC 24 1405790999 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1023294574 Aug 27 09:34:35 AM UTC 24 Aug 27 09:44:09 AM UTC 24 63014908022 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.2034959747 Aug 27 09:23:34 AM UTC 24 Aug 27 09:44:30 AM UTC 24 304543852679 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1389464225 Aug 27 09:38:05 AM UTC 24 Aug 27 09:44:30 AM UTC 24 28789888735 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1175625183 Aug 27 09:44:31 AM UTC 24 Aug 27 09:44:33 AM UTC 24 76925401 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.799751603 Aug 27 09:44:11 AM UTC 24 Aug 27 09:45:00 AM UTC 24 1728616395 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1247526416 Aug 27 09:44:34 AM UTC 24 Aug 27 09:45:01 AM UTC 24 887501682 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.974116950 Aug 27 09:44:00 AM UTC 24 Aug 27 09:45:18 AM UTC 24 3615907209 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2353045637 Aug 27 09:33:34 AM UTC 24 Aug 27 09:45:26 AM UTC 24 22880697463 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1628342877 Aug 27 09:34:45 AM UTC 24 Aug 27 09:45:31 AM UTC 24 3556827505 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.528703931 Aug 27 09:45:27 AM UTC 24 Aug 27 09:45:47 AM UTC 24 6785108218 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.4172317299 Aug 27 09:39:26 AM UTC 24 Aug 27 09:45:56 AM UTC 24 10336324534 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3295445299 Aug 27 09:46:45 AM UTC 24 Aug 27 09:46:53 AM UTC 24 1400753918 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2579133632 Aug 27 09:45:40 AM UTC 24 Aug 27 09:46:02 AM UTC 24 1395541158 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2644352617 Aug 27 09:42:35 AM UTC 24 Aug 27 09:46:12 AM UTC 24 12543771306 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.429024353 Aug 27 09:45:48 AM UTC 24 Aug 27 09:46:43 AM UTC 24 801351892 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2408316181 Aug 27 09:45:58 AM UTC 24 Aug 27 09:46:44 AM UTC 24 6527589102 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1287728683 Aug 27 09:46:12 AM UTC 24 Aug 27 09:47:01 AM UTC 24 3783944080 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2596323350 Aug 27 09:43:01 AM UTC 24 Aug 27 09:47:16 AM UTC 24 7986562516 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2961511271 Aug 27 09:41:13 AM UTC 24 Aug 27 09:47:30 AM UTC 24 230244819050 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.2893000686 Aug 27 09:19:24 AM UTC 24 Aug 27 09:47:40 AM UTC 24 276705442801 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3203114928 Aug 27 09:47:41 AM UTC 24 Aug 27 09:47:43 AM UTC 24 77596162 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2078623273 Aug 27 09:34:33 AM UTC 24 Aug 27 09:47:44 AM UTC 24 13940345722 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.92345457 Aug 27 09:43:57 AM UTC 24 Aug 27 09:47:55 AM UTC 24 7237362453 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2666543605 Aug 27 09:47:44 AM UTC 24 Aug 27 09:48:04 AM UTC 24 2848513570 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3183667824 Aug 27 09:31:05 AM UTC 24 Aug 27 09:48:56 AM UTC 24 29459332208 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4248431628 Aug 27 09:45:31 AM UTC 24 Aug 27 09:49:13 AM UTC 24 42965780618 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4001449479 Aug 27 09:47:17 AM UTC 24 Aug 27 09:49:13 AM UTC 24 1015145109 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3332191716 Aug 27 09:39:49 AM UTC 24 Aug 27 09:49:14 AM UTC 24 7286315322 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3111638074 Aug 27 09:37:38 AM UTC 24 Aug 27 09:59:50 AM UTC 24 37803018779 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1222682969 Aug 27 09:48:58 AM UTC 24 Aug 27 09:49:17 AM UTC 24 2150507273 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1303372054 Aug 27 09:49:14 AM UTC 24 Aug 27 09:49:28 AM UTC 24 769691474 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1236759688 Aug 27 09:49:15 AM UTC 24 Aug 27 09:49:29 AM UTC 24 708186785 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2451184021 Aug 27 09:37:40 AM UTC 24 Aug 27 09:49:30 AM UTC 24 16367432066 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.1332205246 Aug 27 09:32:27 AM UTC 24 Aug 27 09:49:34 AM UTC 24 80171013257 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3978526612 Aug 27 09:49:34 AM UTC 24 Aug 27 09:49:42 AM UTC 24 357173702 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.4109264379 Aug 27 09:47:01 AM UTC 24 Aug 27 09:49:59 AM UTC 24 9423783377 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3863179216 Aug 27 09:37:42 AM UTC 24 Aug 27 09:50:13 AM UTC 24 41122736102 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.2656590625 Aug 27 09:49:17 AM UTC 24 Aug 27 09:50:53 AM UTC 24 38333622224 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3110811672 Aug 27 09:50:53 AM UTC 24 Aug 27 09:50:55 AM UTC 24 34060761 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2974076818 Aug 27 09:50:15 AM UTC 24 Aug 27 09:50:56 AM UTC 24 7716938247 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3998018991 Aug 27 09:46:53 AM UTC 24 Aug 27 09:50:58 AM UTC 24 15759615504 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2004428459 Aug 27 09:50:56 AM UTC 24 Aug 27 09:51:07 AM UTC 24 1582009921 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3350353788 Aug 27 09:20:39 AM UTC 24 Aug 27 09:51:10 AM UTC 24 16787108246 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1683812167 Aug 27 09:40:44 AM UTC 24 Aug 27 09:51:20 AM UTC 24 8987040011 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2233429577 Aug 27 09:50:01 AM UTC 24 Aug 27 09:51:23 AM UTC 24 10932634446 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.682697261 Aug 27 09:45:19 AM UTC 24 Aug 27 09:51:24 AM UTC 24 8022438623 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.562576707 Aug 27 09:51:12 AM UTC 24 Aug 27 09:51:37 AM UTC 24 6859475614 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1608665914 Aug 27 09:51:24 AM UTC 24 Aug 27 09:51:38 AM UTC 24 2233728939 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.552779319 Aug 27 09:51:25 AM UTC 24 Aug 27 09:51:39 AM UTC 24 690262240 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.2439493364 Aug 27 09:29:36 AM UTC 24 Aug 27 09:51:44 AM UTC 24 69195506592 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3363247359 Aug 27 09:51:38 AM UTC 24 Aug 27 09:52:04 AM UTC 24 1737836335 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2357568761 Aug 27 09:52:04 AM UTC 24 Aug 27 09:52:12 AM UTC 24 1349317755 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2916493578 Aug 27 09:49:42 AM UTC 24 Aug 27 09:52:43 AM UTC 24 41438825250 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1500901137 Aug 27 09:43:34 AM UTC 24 Aug 27 09:52:51 AM UTC 24 11406518328 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2975400108 Aug 27 09:52:52 AM UTC 24 Aug 27 09:53:16 AM UTC 24 400575847 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2109418018 Aug 27 09:43:42 AM UTC 24 Aug 27 09:53:22 AM UTC 24 67960576025 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1328301723 Aug 27 09:53:23 AM UTC 24 Aug 27 09:53:25 AM UTC 24 11821623 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1305941692 Aug 27 09:53:26 AM UTC 24 Aug 27 09:53:49 AM UTC 24 8646566025 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1361788042 Aug 27 09:52:12 AM UTC 24 Aug 27 09:54:51 AM UTC 24 6928156701 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.92849459 Aug 27 09:49:14 AM UTC 24 Aug 27 09:55:27 AM UTC 24 53990738234 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2600304329 Aug 27 09:46:03 AM UTC 24 Aug 27 09:55:44 AM UTC 24 123690052475 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3106488459 Aug 27 09:42:30 AM UTC 24 Aug 27 09:56:20 AM UTC 24 42606458230 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.621378687 Aug 27 09:55:45 AM UTC 24 Aug 27 09:56:22 AM UTC 24 1738475621 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2292907954 Aug 27 09:52:44 AM UTC 24 Aug 27 09:56:30 AM UTC 24 50253350475 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.460035132 Aug 27 09:56:22 AM UTC 24 Aug 27 09:56:35 AM UTC 24 668430522 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3009999320 Aug 27 09:56:31 AM UTC 24 Aug 27 09:57:02 AM UTC 24 3172646358 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2964738202 Aug 27 09:43:54 AM UTC 24 Aug 27 09:57:08 AM UTC 24 19172431706 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.4153472555 Aug 27 09:49:30 AM UTC 24 Aug 27 09:57:27 AM UTC 24 6672458784 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.158237261 Aug 27 09:46:44 AM UTC 24 Aug 27 09:57:49 AM UTC 24 61455396990 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3948391710 Aug 27 09:57:49 AM UTC 24 Aug 27 09:57:56 AM UTC 24 359070543 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1501650705 Aug 27 09:56:36 AM UTC 24 Aug 27 09:57:58 AM UTC 24 17959680145 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.4173010844 Aug 27 09:49:30 AM UTC 24 Aug 27 09:58:00 AM UTC 24 12000123398 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2428584273 Aug 27 09:57:59 AM UTC 24 Aug 27 09:58:08 AM UTC 24 326094102 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.3104391943 Aug 27 09:51:40 AM UTC 24 Aug 27 09:58:11 AM UTC 24 11057456941 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3838680410 Aug 27 09:58:09 AM UTC 24 Aug 27 09:58:11 AM UTC 24 32664870 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2174090120 Aug 27 09:48:05 AM UTC 24 Aug 27 09:58:16 AM UTC 24 6495479276 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1933961856 Aug 27 09:51:21 AM UTC 24 Aug 27 09:58:22 AM UTC 24 17233416811 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.3737001917 Aug 27 09:57:28 AM UTC 24 Aug 27 09:58:29 AM UTC 24 2292601713 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1296827339 Aug 27 09:58:11 AM UTC 24 Aug 27 09:58:42 AM UTC 24 896949209 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1403350818 Aug 27 09:58:30 AM UTC 24 Aug 27 09:58:51 AM UTC 24 873361240 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.178162618 Aug 27 09:35:47 AM UTC 24 Aug 27 09:58:58 AM UTC 24 21115305574 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2154298163 Aug 27 09:45:01 AM UTC 24 Aug 27 09:59:09 AM UTC 24 57811863527 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1676799136 Aug 27 09:51:39 AM UTC 24 Aug 27 09:59:13 AM UTC 24 26637372697 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.390744317 Aug 27 09:51:07 AM UTC 24 Aug 27 09:59:18 AM UTC 24 26499450253 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.110918981 Aug 27 09:58:59 AM UTC 24 Aug 27 09:59:24 AM UTC 24 1471080566 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3976025464 Aug 27 09:58:51 AM UTC 24 Aug 27 09:59:42 AM UTC 24 5977509705 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3298020030 Aug 27 09:59:43 AM UTC 24 Aug 27 09:59:49 AM UTC 24 344418046 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3716161811 Aug 27 09:38:39 AM UTC 24 Aug 27 10:00:20 AM UTC 24 11490028817 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1897369246 Aug 27 09:59:09 AM UTC 24 Aug 27 10:00:39 AM UTC 24 20912823620 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1264103581 Aug 27 09:58:12 AM UTC 24 Aug 27 10:00:49 AM UTC 24 5178040593 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.1674217616 Aug 27 10:00:50 AM UTC 24 Aug 27 10:00:53 AM UTC 24 36136053 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2041396713 Aug 27 10:00:53 AM UTC 24 Aug 27 10:01:10 AM UTC 24 805581238 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.1838413688 Aug 27 09:20:56 AM UTC 24 Aug 27 10:01:12 AM UTC 24 435545417524 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.3290790402 Aug 27 09:57:57 AM UTC 24 Aug 27 10:01:13 AM UTC 24 2562074389 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.731484994 Aug 27 09:51:45 AM UTC 24 Aug 27 10:01:18 AM UTC 24 13645642177 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1524013445 Aug 27 09:36:00 AM UTC 24 Aug 27 10:01:28 AM UTC 24 85553217461 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2914838666 Aug 27 09:59:18 AM UTC 24 Aug 27 10:01:32 AM UTC 24 21438320583 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.44808678 Aug 27 10:01:20 AM UTC 24 Aug 27 10:01:41 AM UTC 24 413082289 ps
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T298 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3762970645 Aug 27 10:01:33 AM UTC 24 Aug 27 10:01:58 AM UTC 24 6264189958 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2091563612 Aug 27 09:59:51 AM UTC 24 Aug 27 10:02:27 AM UTC 24 17660925704 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2934604792 Aug 27 09:59:50 AM UTC 24 Aug 27 10:02:53 AM UTC 24 7458424074 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2083842485 Aug 27 09:40:42 AM UTC 24 Aug 27 10:03:06 AM UTC 24 278253958433 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3334979159 Aug 27 10:00:21 AM UTC 24 Aug 27 10:03:09 AM UTC 24 3708207064 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2115057829 Aug 27 10:03:07 AM UTC 24 Aug 27 10:03:14 AM UTC 24 1306805256 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2225142606 Aug 27 10:01:42 AM UTC 24 Aug 27 10:03:28 AM UTC 24 828947178 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3844030938 Aug 27 10:01:59 AM UTC 24 Aug 27 10:03:46 AM UTC 24 11139223265 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.3570601650 Aug 27 10:04:01 AM UTC 24 Aug 27 10:04:03 AM UTC 24 22308569 ps