Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	352399536	1			T2	976		T4	2134		T5	3128
instr_valid_dis	308750917	1			T2	976		T4	2134		T5	3128
instr_en	27639484	1			T30	24458		T28	20000		T29	61228

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14006268	1			T30	8474		T27	31740		T28	35300
sram_ifetch_valid_disable	310360936	1			T2	976		T4	2134		T5	3128
sram_ifetch_enable	28032332	1			T30	24458		T27	103788		T28	12432

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	352399536	1			T2	976		T4	2134		T5	3128
hw_debug_en_valid_off	315945014	1			T2	976		T4	2134		T5	3128
hw_debug_en_on	23795172	1			T27	86414		T28	15814		T29	90858

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	310360936	1			T2	976		T4	2134		T5	3128
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	293533937	1			T2	976		T4	2134		T5	3128
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10472552	1			T41	162744		T17	28316		T136	27762
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6204670	1			T30	8474		T28	20000		T29	67284
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2186948	1			T30	8474		T29	26714		T70	22700
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3412080	1			T28	20000		T29	40570		T41	32404
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5631664	1			T27	31740		T28	15300		T29	19278
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3669426	1			T27	31740		T28	15300		T70	43498
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1575578	1			T29	19278		T17	18734		T139	23392
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9714434	1			T27	14262		T29	29976		T41	70994
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4591806	1			T27	14262		T29	29976		T70	8268
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3671182	1			T41	70950		T17	16132		T136	20782

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11234834	1			T30	24458		T29	1380		T41	72642
lc_exec_en	8449074	1			T27	40412		T28	514		T29	41604
valid_exec_dis	303927492	1			T2	976		T4	2134		T5	3128
invalid_exec_dis	42038600	1			T30	32932		T27	135528		T28	47732