Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.19 94.27 99.72 100.00 96.03 99.12 97.26


Total tests in report: 1032
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.46 60.46 89.21 89.21 65.76 65.76 56.10 56.10 23.81 23.81 76.07 76.07 92.69 92.69 19.56 19.56 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1438963175
79.74 19.29 93.62 4.42 81.28 15.52 87.36 31.27 61.90 38.10 83.18 7.11 94.74 2.05 56.12 36.56 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3747266194
85.99 6.25 95.18 1.55 84.12 2.84 93.18 5.82 71.43 9.52 86.49 3.32 95.32 0.58 76.23 20.11 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3479611313
90.88 4.89 96.81 1.64 84.24 0.12 93.18 0.00 100.00 28.57 89.34 2.84 96.20 0.88 76.42 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1794646721
92.54 1.66 98.61 1.80 86.85 2.61 94.70 1.52 100.00 0.00 93.36 4.03 96.93 0.73 77.33 0.91 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2882871926
94.08 1.54 98.86 0.25 89.57 2.73 95.52 0.83 100.00 0.00 95.26 1.90 96.93 0.00 82.45 5.12 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2512147935
94.84 0.76 98.86 0.00 89.93 0.36 95.52 0.00 100.00 0.00 95.26 0.00 96.93 0.00 87.39 4.94 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1439938289
95.47 0.63 99.10 0.25 89.93 0.00 97.49 1.96 100.00 0.00 95.50 0.24 97.08 0.15 89.21 1.83 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.4235075395
95.86 0.39 99.10 0.00 90.05 0.12 97.69 0.21 100.00 0.00 95.50 0.00 97.08 0.00 91.59 2.38 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1412083063
96.15 0.29 99.10 0.00 90.05 0.00 97.69 0.00 100.00 0.00 95.50 0.00 97.08 0.00 93.60 2.01 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3451611442
96.36 0.21 99.10 0.00 90.05 0.00 98.45 0.76 100.00 0.00 95.50 0.00 97.81 0.73 93.60 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3374805820
96.56 0.20 99.18 0.08 90.05 0.00 99.55 1.10 100.00 0.00 95.73 0.24 97.81 0.00 93.60 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.147943987
96.76 0.20 99.18 0.00 90.28 0.24 99.55 0.00 100.00 0.00 95.73 0.00 98.98 1.17 93.60 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3719618276
96.94 0.18 99.18 0.00 90.28 0.00 99.55 0.00 100.00 0.00 95.73 0.00 98.98 0.00 94.88 1.28 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1780802016
97.08 0.14 99.18 0.00 90.52 0.24 99.55 0.00 100.00 0.00 95.73 0.00 98.98 0.00 95.61 0.73 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2877988927
97.17 0.08 99.18 0.00 90.64 0.12 99.55 0.00 100.00 0.00 96.21 0.47 98.98 0.00 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.86520054
97.25 0.08 99.18 0.00 90.64 0.00 99.55 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.16 0.55 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2119704165
97.31 0.06 99.18 0.00 91.00 0.36 99.62 0.07 100.00 0.00 96.21 0.00 98.98 0.00 96.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.514518111
97.36 0.05 99.18 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.53 0.37 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1636077276
97.41 0.05 99.18 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.4020476277
97.44 0.03 99.18 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3701707979
97.46 0.03 99.18 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1509972270
97.48 0.02 99.18 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.21 0.00 99.12 0.15 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2350057702
97.49 0.01 99.18 0.00 91.00 0.00 99.69 0.07 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2916835051
97.50 0.01 99.18 0.00 91.00 0.00 99.72 0.03 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3175522408

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1916193891
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.72714082
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1572860883
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3342383663
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2859955934
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.431951382
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3532622116
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2781350068
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1430947785
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1366932411
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3108392480
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1884379272
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1752304790
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2538592462
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.920836552
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4272442565
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.234635961
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2580861228
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4181810602
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.436013383
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1690016066
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1165562968
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2152362598
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.252362955
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2256714241
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1467487671
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2445316119
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1623423652
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1104928621
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2728427973
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3377340032
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4096310769
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2856285245
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.444863085
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1165574130
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2212632272
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3920086132
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2266854404
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2231101448
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1647939629
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4011025656
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3006854650
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.32763511
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1222219417
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2421701012
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2558126069
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3044251223
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2738415765
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.863337311
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1391077973
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2496165830
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4126070081
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2084321515
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3755711098
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3084682859
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3676707467
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3699704452
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3399780697
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2748149793
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1574283226
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.182030809
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1147486261
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.214886317
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2246884137
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3973329639
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1108027760
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3120229325
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1285159763
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2635284891
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2340192905
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1259451696
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2515869833
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1974508338
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1092556084
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3866245991
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3082164175
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3109901174
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3072004176
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.82590455
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3870845823
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1491830324
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2475217828
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/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1298447311
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.499728060
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1567991021
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.648347958
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2508739335
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.512817099
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.4044037483
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2639142349
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.414243033
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.1682039924
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.605997498
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1840300701
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1008665487
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/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1016359473
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2701627303
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1289776557
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3465760275
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.2479033427
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.2664369846
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1317757029
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.928950630
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1792083633
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.266009322
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1571356082
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3319639445
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.471323189
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3204948360
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.700402393
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3514655410
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.4280624686
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3439228697
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2710501703
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3428491558
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3435570104
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3513279293
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.1917603313
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2569363250
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1248368618
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4249767220
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.4069181685
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2218986242
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1169108563
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.979618451
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3959690683
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2567583351
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.777364218
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2957254431
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.246769192
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3245176217
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.377707962
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.555294468
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3251544313
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2954295598
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.3915465566
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.2707039506
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2550373552
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1049641375
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.511385721
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1269578745



Total test records in report: 1032
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.514518111 Aug 29 12:27:24 AM UTC 24 Aug 29 12:27:27 AM UTC 24 13572616 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1879708668 Aug 29 12:27:23 AM UTC 24 Aug 29 12:27:29 AM UTC 24 234419391 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2843480536 Aug 29 12:27:30 AM UTC 24 Aug 29 12:27:32 AM UTC 24 27985182 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3753727129 Aug 29 12:27:23 AM UTC 24 Aug 29 12:27:34 AM UTC 24 5582957919 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2882871926 Aug 29 12:27:29 AM UTC 24 Aug 29 12:27:35 AM UTC 24 357317942 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1438963175 Aug 29 12:27:22 AM UTC 24 Aug 29 12:27:36 AM UTC 24 2200786256 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.371804301 Aug 29 12:27:25 AM UTC 24 Aug 29 12:27:36 AM UTC 24 2700259092 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.10698123 Aug 29 12:27:22 AM UTC 24 Aug 29 12:27:36 AM UTC 24 971531567 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2983351609 Aug 29 12:27:24 AM UTC 24 Aug 29 12:27:36 AM UTC 24 2797258384 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.147943987 Aug 29 12:27:28 AM UTC 24 Aug 29 12:27:36 AM UTC 24 1458297453 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2443935680 Aug 29 12:27:25 AM UTC 24 Aug 29 12:27:37 AM UTC 24 2818592567 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3175522408 Aug 29 12:27:22 AM UTC 24 Aug 29 12:27:45 AM UTC 24 717261317 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2010734472 Aug 29 12:27:31 AM UTC 24 Aug 29 12:27:46 AM UTC 24 1993250530 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2901853284 Aug 29 12:27:45 AM UTC 24 Aug 29 12:27:51 AM UTC 24 705806900 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3136402762 Aug 29 12:27:35 AM UTC 24 Aug 29 12:27:53 AM UTC 24 10246470158 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.49742310 Aug 29 12:27:24 AM UTC 24 Aug 29 12:28:07 AM UTC 24 1073706013 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3479611313 Aug 29 12:27:25 AM UTC 24 Aug 29 12:28:16 AM UTC 24 16892426011 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.696400636 Aug 29 12:27:22 AM UTC 24 Aug 29 12:28:18 AM UTC 24 802422893 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2200370199 Aug 29 12:28:14 AM UTC 24 Aug 29 12:28:18 AM UTC 24 1100565581 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3350248534 Aug 29 12:28:17 AM UTC 24 Aug 29 12:28:19 AM UTC 24 29397636 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.1321454910 Aug 29 12:27:37 AM UTC 24 Aug 29 12:28:24 AM UTC 24 2690746812 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.866700977 Aug 29 12:27:54 AM UTC 24 Aug 29 12:28:35 AM UTC 24 3566822881 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.4210729352 Aug 29 12:27:23 AM UTC 24 Aug 29 12:28:38 AM UTC 24 6268293376 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.954073648 Aug 29 12:28:18 AM UTC 24 Aug 29 12:28:41 AM UTC 24 497625755 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2207258320 Aug 29 12:27:37 AM UTC 24 Aug 29 12:28:56 AM UTC 24 3060922934 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3747266194 Aug 29 12:27:29 AM UTC 24 Aug 29 12:29:07 AM UTC 24 2052143166 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.4235075395 Aug 29 12:27:33 AM UTC 24 Aug 29 12:29:08 AM UTC 24 1936351814 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2877988927 Aug 29 12:27:22 AM UTC 24 Aug 29 12:29:11 AM UTC 24 10146614151 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.722873866 Aug 29 12:28:57 AM UTC 24 Aug 29 12:29:13 AM UTC 24 4255921166 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3401828674 Aug 29 12:28:36 AM UTC 24 Aug 29 12:29:16 AM UTC 24 587033060 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2460089181 Aug 29 12:29:17 AM UTC 24 Aug 29 12:29:24 AM UTC 24 5589886730 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3399281521 Aug 29 12:28:42 AM UTC 24 Aug 29 12:29:38 AM UTC 24 767350395 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2727053902 Aug 29 12:27:23 AM UTC 24 Aug 29 12:30:07 AM UTC 24 10961506933 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3759564025 Aug 29 12:30:04 AM UTC 24 Aug 29 12:30:22 AM UTC 24 1563385198 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2594213237 Aug 29 12:27:28 AM UTC 24 Aug 29 12:30:25 AM UTC 24 6624640139 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3113966188 Aug 29 12:30:23 AM UTC 24 Aug 29 12:30:27 AM UTC 24 250260572 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.4289400238 Aug 29 12:30:26 AM UTC 24 Aug 29 12:30:28 AM UTC 24 18624708 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.4020476277 Aug 29 12:29:08 AM UTC 24 Aug 29 12:30:42 AM UTC 24 45595413049 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.2570154085 Aug 29 12:27:47 AM UTC 24 Aug 29 12:30:48 AM UTC 24 9406500327 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.762596387 Aug 29 12:27:52 AM UTC 24 Aug 29 12:31:00 AM UTC 24 2445641266 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.900493780 Aug 29 12:27:37 AM UTC 24 Aug 29 12:31:02 AM UTC 24 143258763037 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.2664823004 Aug 29 12:30:28 AM UTC 24 Aug 29 12:31:08 AM UTC 24 1199823115 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2187140757 Aug 29 12:31:02 AM UTC 24 Aug 29 12:31:15 AM UTC 24 4216975848 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.278142390 Aug 29 12:27:22 AM UTC 24 Aug 29 12:31:18 AM UTC 24 5618845223 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2901097147 Aug 29 12:31:19 AM UTC 24 Aug 29 12:31:26 AM UTC 24 497469310 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3736818108 Aug 29 12:30:45 AM UTC 24 Aug 29 12:31:34 AM UTC 24 1775378063 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2427199899 Aug 29 12:27:28 AM UTC 24 Aug 29 12:31:39 AM UTC 24 37436403201 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.50698890 Aug 29 12:31:01 AM UTC 24 Aug 29 12:31:41 AM UTC 24 1491463302 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3005752759 Aug 29 12:27:24 AM UTC 24 Aug 29 12:31:50 AM UTC 24 10212969437 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3374805820 Aug 29 12:31:39 AM UTC 24 Aug 29 12:31:53 AM UTC 24 530483040 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.2652305000 Aug 29 12:31:51 AM UTC 24 Aug 29 12:31:55 AM UTC 24 176914576 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.476281394 Aug 29 12:31:53 AM UTC 24 Aug 29 12:31:55 AM UTC 24 22039370 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1236355393 Aug 29 12:31:03 AM UTC 24 Aug 29 12:32:03 AM UTC 24 6154126999 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.1935874309 Aug 29 12:31:13 AM UTC 24 Aug 29 12:32:28 AM UTC 24 7603536764 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.3983235389 Aug 29 12:31:56 AM UTC 24 Aug 29 12:32:39 AM UTC 24 677255092 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2933052989 Aug 29 12:29:26 AM UTC 24 Aug 29 12:33:06 AM UTC 24 10686050186 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.729636802 Aug 29 12:27:22 AM UTC 24 Aug 29 12:33:10 AM UTC 24 26086721200 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.4121646195 Aug 29 12:29:39 AM UTC 24 Aug 29 12:33:12 AM UTC 24 10029737277 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3154675713 Aug 29 12:32:34 AM UTC 24 Aug 29 12:33:15 AM UTC 24 794509832 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.681899089 Aug 29 12:27:24 AM UTC 24 Aug 29 12:33:20 AM UTC 24 7016259151 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3880283438 Aug 29 12:28:39 AM UTC 24 Aug 29 12:33:30 AM UTC 24 8737852378 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.126101397 Aug 29 12:33:07 AM UTC 24 Aug 29 12:33:44 AM UTC 24 754931576 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1548226398 Aug 29 12:33:44 AM UTC 24 Aug 29 12:33:53 AM UTC 24 1403255141 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.1260740764 Aug 29 12:27:28 AM UTC 24 Aug 29 12:34:02 AM UTC 24 2750741312 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.4292088659 Aug 29 12:31:27 AM UTC 24 Aug 29 12:34:03 AM UTC 24 2687938703 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3129255627 Aug 29 12:33:11 AM UTC 24 Aug 29 12:34:05 AM UTC 24 776359800 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3341206613 Aug 29 12:28:25 AM UTC 24 Aug 29 12:34:06 AM UTC 24 33994295466 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.3155987641 Aug 29 12:29:11 AM UTC 24 Aug 29 12:34:07 AM UTC 24 26723877381 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1473260400 Aug 29 12:34:07 AM UTC 24 Aug 29 12:34:08 AM UTC 24 15406670 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2348180501 Aug 29 12:34:04 AM UTC 24 Aug 29 12:34:26 AM UTC 24 1012566493 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.499728060 Aug 29 12:34:08 AM UTC 24 Aug 29 12:34:34 AM UTC 24 4316906123 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.831840534 Aug 29 12:27:22 AM UTC 24 Aug 29 12:34:42 AM UTC 24 12747494163 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2467007401 Aug 29 12:27:22 AM UTC 24 Aug 29 12:34:56 AM UTC 24 6720391501 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.795765417 Aug 29 12:27:36 AM UTC 24 Aug 29 12:34:59 AM UTC 24 5597484361 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.283861156 Aug 29 12:34:43 AM UTC 24 Aug 29 12:35:11 AM UTC 24 591437755 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3908563625 Aug 29 12:33:13 AM UTC 24 Aug 29 12:35:23 AM UTC 24 126655657820 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1012075501 Aug 29 12:30:43 AM UTC 24 Aug 29 12:35:24 AM UTC 24 5054410718 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1794646721 Aug 29 12:31:35 AM UTC 24 Aug 29 12:35:35 AM UTC 24 24976202111 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.512817099 Aug 29 12:35:11 AM UTC 24 Aug 29 12:36:31 AM UTC 24 818653403 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.874943596 Aug 29 12:36:32 AM UTC 24 Aug 29 12:36:40 AM UTC 24 364955375 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.4178552337 Aug 29 12:35:36 AM UTC 24 Aug 29 12:49:30 AM UTC 24 7287202083 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3714100106 Aug 29 12:34:59 AM UTC 24 Aug 29 12:36:42 AM UTC 24 758329564 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1095398456 Aug 29 12:35:24 AM UTC 24 Aug 29 12:36:46 AM UTC 24 5684887008 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.648347958 Aug 29 12:36:47 AM UTC 24 Aug 29 12:37:33 AM UTC 24 1980125624 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1844714712 Aug 29 12:37:34 AM UTC 24 Aug 29 12:37:36 AM UTC 24 14598449 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3451611442 Aug 29 12:27:25 AM UTC 24 Aug 29 12:37:51 AM UTC 24 21766181213 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.2664369846 Aug 29 12:37:37 AM UTC 24 Aug 29 12:37:51 AM UTC 24 614129315 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2512147935 Aug 29 12:27:38 AM UTC 24 Aug 29 12:37:57 AM UTC 24 70524116136 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2033607179 Aug 29 12:33:53 AM UTC 24 Aug 29 12:38:23 AM UTC 24 15768747492 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2869938038 Aug 29 12:34:56 AM UTC 24 Aug 29 12:38:27 AM UTC 24 13190805400 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2701627303 Aug 29 12:38:24 AM UTC 24 Aug 29 12:38:31 AM UTC 24 392492650 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1840300701 Aug 29 12:38:32 AM UTC 24 Aug 29 12:38:59 AM UTC 24 755031378 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1890802062 Aug 29 12:34:02 AM UTC 24 Aug 29 12:39:08 AM UTC 24 45779178986 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1319165483 Aug 29 12:27:23 AM UTC 24 Aug 29 12:39:09 AM UTC 24 7107440334 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1901713579 Aug 29 12:32:29 AM UTC 24 Aug 29 12:39:12 AM UTC 24 17357475142 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.2982052664 Aug 29 12:29:13 AM UTC 24 Aug 29 12:39:39 AM UTC 24 2782251518 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3465760275 Aug 29 12:39:40 AM UTC 24 Aug 29 12:39:46 AM UTC 24 1406019156 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.4125104661 Aug 29 12:27:23 AM UTC 24 Aug 29 12:39:49 AM UTC 24 12097305736 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2830032928 Aug 29 12:33:16 AM UTC 24 Aug 29 12:40:08 AM UTC 24 14157553005 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.266009322 Aug 29 12:39:00 AM UTC 24 Aug 29 12:40:19 AM UTC 24 10904199060 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2639142349 Aug 29 12:40:20 AM UTC 24 Aug 29 12:40:22 AM UTC 24 41691990 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2362576564 Aug 29 12:36:43 AM UTC 24 Aug 29 12:40:33 AM UTC 24 17351119319 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.928950630 Aug 29 12:39:51 AM UTC 24 Aug 29 12:40:35 AM UTC 24 2932391649 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2569363250 Aug 29 12:40:23 AM UTC 24 Aug 29 12:40:46 AM UTC 24 3951337896 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.273209225 Aug 29 12:28:20 AM UTC 24 Aug 29 12:40:58 AM UTC 24 17172140422 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2508739335 Aug 29 12:34:35 AM UTC 24 Aug 29 12:41:07 AM UTC 24 23072093154 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1792083633 Aug 29 12:37:58 AM UTC 24 Aug 29 12:41:12 AM UTC 24 5158382522 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.1838339795 Aug 29 12:30:29 AM UTC 24 Aug 29 12:41:20 AM UTC 24 25473709948 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2841818330 Aug 29 12:32:41 AM UTC 24 Aug 29 12:41:20 AM UTC 24 78821187793 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3428491558 Aug 29 12:40:59 AM UTC 24 Aug 29 12:41:23 AM UTC 24 6340364129 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2218986242 Aug 29 12:41:21 AM UTC 24 Aug 29 12:41:52 AM UTC 24 767322911 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2431259725 Aug 29 12:31:09 AM UTC 24 Aug 29 12:41:55 AM UTC 24 11087505164 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.387548519 Aug 29 12:27:37 AM UTC 24 Aug 29 12:42:09 AM UTC 24 11283661190 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2184198871 Aug 29 12:34:09 AM UTC 24 Aug 29 12:42:15 AM UTC 24 18661010258 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3513279293 Aug 29 12:42:10 AM UTC 24 Aug 29 12:42:17 AM UTC 24 364077220 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3514655410 Aug 29 12:41:13 AM UTC 24 Aug 29 12:42:21 AM UTC 24 849838186 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1008665487 Aug 29 12:39:47 AM UTC 24 Aug 29 12:42:27 AM UTC 24 8781554369 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3059474378 Aug 29 12:39:47 AM UTC 24 Aug 29 12:42:41 AM UTC 24 6989937848 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3319639445 Aug 29 12:42:43 AM UTC 24 Aug 29 12:42:45 AM UTC 24 19866079 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.605997498 Aug 29 12:39:09 AM UTC 24 Aug 29 12:43:05 AM UTC 24 19718665081 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4249767220 Aug 29 12:42:21 AM UTC 24 Aug 29 12:43:07 AM UTC 24 1157711770 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.700402393 Aug 29 12:41:21 AM UTC 24 Aug 29 12:43:18 AM UTC 24 7831964382 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.2707039506 Aug 29 12:42:46 AM UTC 24 Aug 29 12:43:20 AM UTC 24 1600264484 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.555294468 Aug 29 12:43:20 AM UTC 24 Aug 29 12:43:35 AM UTC 24 1238866417 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2043055443 Aug 29 12:30:32 AM UTC 24 Aug 29 12:43:40 AM UTC 24 22558359688 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.4280624686 Aug 29 12:42:17 AM UTC 24 Aug 29 12:43:46 AM UTC 24 2918135508 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2957254431 Aug 29 12:43:40 AM UTC 24 Aug 29 12:43:58 AM UTC 24 1520722081 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.4069181685 Aug 29 12:40:47 AM UTC 24 Aug 29 12:43:59 AM UTC 24 4989431083 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1571356082 Aug 29 12:41:24 AM UTC 24 Aug 29 12:44:00 AM UTC 24 3154928227 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3948491581 Aug 29 12:30:49 AM UTC 24 Aug 29 12:44:06 AM UTC 24 91894822706 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3646496631 Aug 29 12:36:40 AM UTC 24 Aug 29 12:44:07 AM UTC 24 47047648533 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2954295598 Aug 29 12:44:08 AM UTC 24 Aug 29 12:44:15 AM UTC 24 350391360 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1269578745 Aug 29 12:43:46 AM UTC 24 Aug 29 12:44:31 AM UTC 24 3050380342 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.777364218 Aug 29 12:43:58 AM UTC 24 Aug 29 12:45:15 AM UTC 24 6334477675 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3544576371 Aug 29 12:27:26 AM UTC 24 Aug 29 12:45:19 AM UTC 24 437759389000 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.979618451 Aug 29 12:45:31 AM UTC 24 Aug 29 12:45:34 AM UTC 24 28484844 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.3774956582 Aug 29 12:45:35 AM UTC 24 Aug 29 12:45:48 AM UTC 24 788368774 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.246769192 Aug 29 12:44:32 AM UTC 24 Aug 29 12:46:07 AM UTC 24 9567743732 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.3118171240 Aug 29 12:27:26 AM UTC 24 Aug 29 12:46:52 AM UTC 24 104131526988 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1049641375 Aug 29 12:45:16 AM UTC 24 Aug 29 12:46:59 AM UTC 24 10415951814 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3582692017 Aug 29 12:27:37 AM UTC 24 Aug 29 12:47:13 AM UTC 24 42235966701 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.511385721 Aug 29 12:43:19 AM UTC 24 Aug 29 12:47:16 AM UTC 24 3591303907 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3439228697 Aug 29 12:42:15 AM UTC 24 Aug 29 12:47:53 AM UTC 24 43779720205 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1289776557 Aug 29 12:38:28 AM UTC 24 Aug 29 12:47:54 AM UTC 24 77600649881 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.4037804919 Aug 29 12:46:53 AM UTC 24 Aug 29 12:48:11 AM UTC 24 2235266422 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1169108563 Aug 29 12:44:00 AM UTC 24 Aug 29 12:48:14 AM UTC 24 9801850507 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3315998894 Aug 29 12:47:13 AM UTC 24 Aug 29 12:48:24 AM UTC 24 770156974 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.1917603313 Aug 29 12:41:56 AM UTC 24 Aug 29 12:48:30 AM UTC 24 14898076000 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2070116182 Aug 29 12:48:25 AM UTC 24 Aug 29 12:48:31 AM UTC 24 370043955 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.870520788 Aug 29 12:31:56 AM UTC 24 Aug 29 12:48:53 AM UTC 24 16440813792 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2567583351 Aug 29 12:44:01 AM UTC 24 Aug 29 12:49:03 AM UTC 24 14481838861 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1473430710 Aug 29 12:47:16 AM UTC 24 Aug 29 12:49:15 AM UTC 24 2903794043 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1887373306 Aug 29 12:49:15 AM UTC 24 Aug 29 12:49:17 AM UTC 24 42508710 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.853923691 Aug 29 12:49:19 AM UTC 24 Aug 29 12:49:35 AM UTC 24 1905614919 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.564919844 Aug 29 12:35:26 AM UTC 24 Aug 29 12:49:46 AM UTC 24 63940549178 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1143612416 Aug 29 12:29:09 AM UTC 24 Aug 29 12:49:56 AM UTC 24 16337437699 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.377707962 Aug 29 12:43:07 AM UTC 24 Aug 29 12:50:03 AM UTC 24 5987085779 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2645935465 Aug 29 12:49:57 AM UTC 24 Aug 29 12:50:10 AM UTC 24 538911215 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1742192322 Aug 29 12:48:31 AM UTC 24 Aug 29 12:50:12 AM UTC 24 1386355748 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3245176217 Aug 29 12:44:16 AM UTC 24 Aug 29 12:50:13 AM UTC 24 55354007045 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3285571036 Aug 29 12:47:54 AM UTC 24 Aug 29 12:50:40 AM UTC 24 36243828575 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3297828233 Aug 29 12:50:14 AM UTC 24 Aug 29 12:50:52 AM UTC 24 24897409710 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.471323189 Aug 29 12:40:35 AM UTC 24 Aug 29 12:50:52 AM UTC 24 45607806853 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.49655625 Aug 29 12:50:12 AM UTC 24 Aug 29 12:51:12 AM UTC 24 3109248389 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3120300398 Aug 29 12:46:08 AM UTC 24 Aug 29 12:51:22 AM UTC 24 3211359423 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1508410784 Aug 29 12:51:11 AM UTC 24 Aug 29 12:51:22 AM UTC 24 5599377762 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1752333343 Aug 29 12:48:53 AM UTC 24 Aug 29 12:51:30 AM UTC 24 1792613754 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1761143395 Aug 29 12:51:24 AM UTC 24 Aug 29 12:51:38 AM UTC 24 330841313 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.219015963 Aug 29 12:50:10 AM UTC 24 Aug 29 12:51:39 AM UTC 24 2254248488 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3685473938 Aug 29 12:51:40 AM UTC 24 Aug 29 12:51:42 AM UTC 24 12921784 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3251544313 Aug 29 12:43:36 AM UTC 24 Aug 29 12:51:45 AM UTC 24 31737017427 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.1682039924 Aug 29 12:39:13 AM UTC 24 Aug 29 12:51:55 AM UTC 24 17870064574 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1780802016 Aug 29 12:27:23 AM UTC 24 Aug 29 12:52:31 AM UTC 24 151196685340 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2220764828 Aug 29 12:51:40 AM UTC 24 Aug 29 12:52:54 AM UTC 24 867137525 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1163406869 Aug 29 12:31:17 AM UTC 24 Aug 29 12:52:58 AM UTC 24 237248547570 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1412083063 Aug 29 12:33:31 AM UTC 24 Aug 29 12:53:07 AM UTC 24 75717507733 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.4171069620 Aug 29 12:51:22 AM UTC 24 Aug 29 12:53:17 AM UTC 24 12778424182 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3280452282 Aug 29 12:52:59 AM UTC 24 Aug 29 12:53:18 AM UTC 24 1413773956 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3212094629 Aug 29 12:53:08 AM UTC 24 Aug 29 12:53:19 AM UTC 24 695998357 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.113168648 Aug 29 12:48:31 AM UTC 24 Aug 29 12:53:49 AM UTC 24 15759000539 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.3915465566 Aug 29 12:44:07 AM UTC 24 Aug 29 12:54:18 AM UTC 24 13980154217 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.596170578 Aug 29 12:54:19 AM UTC 24 Aug 29 12:54:27 AM UTC 24 677989334 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3572546291 Aug 29 12:52:32 AM UTC 24 Aug 29 12:54:36 AM UTC 24 548976927 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1298447311 Aug 29 12:35:52 AM UTC 24 Aug 29 12:55:04 AM UTC 24 58859047807 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3098243365 Aug 29 12:33:21 AM UTC 24 Aug 29 12:55:06 AM UTC 24 9458249602 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.4044037483 Aug 29 12:39:10 AM UTC 24 Aug 29 12:55:08 AM UTC 24 33179225805 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3392265482 Aug 29 12:55:09 AM UTC 24 Aug 29 12:55:11 AM UTC 24 19897326 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.4003735765 Aug 29 12:47:55 AM UTC 24 Aug 29 12:55:11 AM UTC 24 11237867678 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.245647827 Aug 29 12:51:12 AM UTC 24 Aug 29 12:55:11 AM UTC 24 14787640685 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3435570104 Aug 29 12:41:07 AM UTC 24 Aug 29 12:55:13 AM UTC 24 48266186929 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3959690683 Aug 29 12:43:08 AM UTC 24 Aug 29 12:55:20 AM UTC 24 10947278119 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1083298642 Aug 29 12:53:18 AM UTC 24 Aug 29 12:55:30 AM UTC 24 19187471984 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2340438868 Aug 29 12:55:12 AM UTC 24 Aug 29 12:55:47 AM UTC 24 2844473528 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2083865749 Aug 29 12:49:47 AM UTC 24 Aug 29 12:55:53 AM UTC 24 12670275631 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1016359473 Aug 29 12:37:52 AM UTC 24 Aug 29 12:55:55 AM UTC 24 72443549346 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.904669594 Aug 29 12:50:53 AM UTC 24 Aug 29 12:55:59 AM UTC 24 7507931395 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.2479033427 Aug 29 12:39:39 AM UTC 24 Aug 29 12:56:02 AM UTC 24 78401514798 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2230753255 Aug 29 12:54:37 AM UTC 24 Aug 29 12:56:09 AM UTC 24 10706193926 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1695266258 Aug 29 12:50:03 AM UTC 24 Aug 29 12:56:21 AM UTC 24 45681877246 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.42225183 Aug 29 12:56:22 AM UTC 24 Aug 29 12:56:29 AM UTC 24 365617175 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1425439167 Aug 29 12:55:57 AM UTC 24 Aug 29 12:57:06 AM UTC 24 29526500093 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3685502028 Aug 29 12:55:21 AM UTC 24 Aug 29 12:57:10 AM UTC 24 3087273351 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1609846673 Aug 29 12:55:54 AM UTC 24 Aug 29 12:57:11 AM UTC 24 1473458420 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2390900506 Aug 29 12:55:47 AM UTC 24 Aug 29 12:57:14 AM UTC 24 2965593590 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1242061293 Aug 29 12:57:15 AM UTC 24 Aug 29 12:57:16 AM UTC 24 40201173 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1574249379 Aug 29 12:55:05 AM UTC 24 Aug 29 12:57:20 AM UTC 24 5719302287 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3019132457 Aug 29 12:57:11 AM UTC 24 Aug 29 12:57:33 AM UTC 24 1027402741 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1701246031 Aug 29 12:57:18 AM UTC 24 Aug 29 12:57:49 AM UTC 24 1686696051 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2618470489 Aug 29 12:54:27 AM UTC 24 Aug 29 12:58:01 AM UTC 24 32851052121 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1398495826 Aug 29 12:46:59 AM UTC 24 Aug 29 12:58:04 AM UTC 24 21050867905 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3704497006 Aug 29 12:51:56 AM UTC 24 Aug 29 12:58:24 AM UTC 24 10727803830 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.625332947 Aug 29 12:58:02 AM UTC 24 Aug 29 12:58:30 AM UTC 24 7245348338 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.3031748208 Aug 29 12:50:53 AM UTC 24 Aug 29 12:59:00 AM UTC 24 11015156878 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.611180661 Aug 29 12:56:30 AM UTC 24 Aug 29 12:59:08 AM UTC 24 2156305270 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.172225200 Aug 29 12:58:25 AM UTC 24 Aug 29 12:59:23 AM UTC 24 2961765039 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.813497514 Aug 29 12:58:30 AM UTC 24 Aug 29 12:59:35 AM UTC 24 946500543 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2243539906 Aug 29 12:57:07 AM UTC 24 Aug 29 12:59:51 AM UTC 24 10002343865 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1395524145 Aug 29 12:59:52 AM UTC 24 Aug 29 12:59:58 AM UTC 24 1972916009 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2710501703 Aug 29 12:40:34 AM UTC 24 Aug 29 01:00:01 AM UTC 24 73200985166 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.2884349984 Aug 29 12:48:15 AM UTC 24 Aug 29 01:00:36 AM UTC 24 13095122931 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.359176224 Aug 29 12:59:02 AM UTC 24 Aug 29 01:00:39 AM UTC 24 24983850418 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2434548678 Aug 29 12:48:12 AM UTC 24 Aug 29 01:00:50 AM UTC 24 15974678099 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.1451499226 Aug 29 01:00:51 AM UTC 24 Aug 29 01:00:53 AM UTC 24 39908173 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2453982989 Aug 29 01:00:36 AM UTC 24 Aug 29 01:00:58 AM UTC 24 1043743724 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.760848653 Aug 29 12:55:12 AM UTC 24 Aug 29 01:00:58 AM UTC 24 35289923481 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2005968199 Aug 29 01:00:54 AM UTC 24 Aug 29 01:01:02 AM UTC 24 356064892 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2755041878 Aug 29 12:55:14 AM UTC 24 Aug 29 01:01:08 AM UTC 24 4341380158 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.4241454595 Aug 29 12:52:55 AM UTC 24 Aug 29 01:01:28 AM UTC 24 35667096635 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.664507627 Aug 29 12:55:30 AM UTC 24 Aug 29 01:01:41 AM UTC 24 31060658373 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3276580914 Aug 29 01:00:02 AM UTC 24 Aug 29 01:01:53 AM UTC 24 9809601436 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.2311675991 Aug 29 01:01:09 AM UTC 24 Aug 29 01:01:58 AM UTC 24 1818374400 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3204948360 Aug 29 12:41:53 AM UTC 24 Aug 29 01:02:00 AM UTC 24 108416588897 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1362339521 Aug 29 01:01:42 AM UTC 24 Aug 29 01:02:24 AM UTC 24 1945087403 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2687176627 Aug 29 12:59:24 AM UTC 24 Aug 29 01:02:54 AM UTC 24 4197569274 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.23298459 Aug 29 01:01:53 AM UTC 24 Aug 29 01:02:59 AM UTC 24 780597843 ps
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