Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	347065016	1			T2	5194		T3	14418		T4	1002
instr_valid_dis	302842526	1			T2	5194		T3	14418		T4	1002
instr_en	27582729	1			T27	39552		T25	77962		T38	46876

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15295594	1			T25	70978		T26	100694		T66	135114
sram_ifetch_valid_disable	301914408	1			T2	5194		T3	14418		T4	1002
sram_ifetch_enable	29855014	1			T27	39470		T25	85588		T66	116196

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	347065016	1			T2	5194		T3	14418		T4	1002
hw_debug_en_valid_off	304257634	1			T2	5194		T3	14418		T4	1002
hw_debug_en_on	27663216	1			T25	104660		T26	46750		T66	77942

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	301914408	1			T2	5194		T3	14418		T4	1002
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	283400406	1			T2	5194		T3	14418		T4	1002
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11880969	1			T27	82		T38	35906		T39	54618
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5046876	1			T25	70886		T26	100694		T66	47306
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2224632	1			T25	70886		T26	100694		T66	47306
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1590302	1			T38	10894		T141	11222		T147	13094
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5174298	1			T25	92		T66	18470		T38	9500
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2259204	1			T25	92		T66	18470		T38	9500
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1573700	1			T141	49150		T142	2734		T147	10924
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11613674	1			T25	26606		T26	46750		T66	56802
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3914314	1			T25	26606		T26	46750		T66	56802
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3736234	1			T38	33766		T39	19830		T145	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8584074	1			T27	39470		T25	77962		T38	76
lc_exec_en	10875244	1			T25	77962		T66	2670		T39	111104
valid_exec_dis	298528298	1			T2	5194		T3	14418		T4	1002
invalid_exec_dis	45150608	1			T27	39470		T25	156566		T26	100694