Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1033
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
75.51 75.51 92.23 92.23 79.27 79.27 89.63 89.63 23.81 23.81 81.75 81.75 93.86 93.86 68.01 68.01 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2823277789
87.58 12.07 96.97 4.74 82.23 2.96 90.74 1.10 90.48 66.67 89.10 7.35 95.32 1.46 68.19 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2458614752
90.97 3.40 98.28 1.31 84.36 2.13 96.21 5.48 100.00 9.52 92.18 3.08 95.76 0.44 70.02 1.83 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1640706525
92.46 1.49 98.53 0.25 87.32 2.96 96.76 0.55 100.00 0.00 94.08 1.90 95.76 0.00 74.77 4.75 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.3156381995
93.84 1.38 98.53 0.00 87.44 0.12 97.31 0.55 100.00 0.00 94.31 0.24 95.76 0.00 83.55 8.78 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3849232212
94.81 0.97 98.69 0.16 88.03 0.59 97.52 0.21 100.00 0.00 95.02 0.71 95.76 0.00 88.67 5.12 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2370070109
95.59 0.78 98.86 0.16 89.93 1.90 98.28 0.76 100.00 0.00 95.73 0.71 96.78 1.02 89.58 0.91 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1533088855
96.21 0.61 99.10 0.25 89.93 0.00 98.28 0.00 100.00 0.00 95.97 0.24 96.93 0.15 93.24 3.66 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.642643018
96.49 0.29 99.10 0.00 89.93 0.00 98.28 0.00 100.00 0.00 95.97 0.00 96.93 0.00 95.25 2.01 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.916615573
96.70 0.21 99.10 0.00 90.17 0.24 98.35 0.07 100.00 0.00 95.97 0.00 98.10 1.17 95.25 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3113989373
96.86 0.16 99.10 0.00 90.52 0.36 98.35 0.00 100.00 0.00 95.97 0.00 98.10 0.00 95.98 0.73 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2925067638
97.00 0.14 99.10 0.00 90.52 0.00 98.35 0.00 100.00 0.00 96.21 0.24 98.83 0.73 95.98 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3410344736
97.13 0.13 99.18 0.08 90.52 0.00 99.17 0.83 100.00 0.00 96.21 0.00 98.83 0.00 95.98 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.711454101
97.23 0.10 99.18 0.00 90.52 0.00 99.17 0.00 100.00 0.00 96.21 0.00 98.83 0.00 96.71 0.73 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1371020563
97.30 0.07 99.18 0.00 90.64 0.12 99.38 0.21 100.00 0.00 96.21 0.00 98.83 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2891282228
97.37 0.06 99.18 0.00 91.00 0.36 99.45 0.07 100.00 0.00 96.21 0.00 98.83 0.00 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1430750459
97.40 0.04 99.18 0.00 91.00 0.00 99.55 0.10 100.00 0.00 96.21 0.00 98.98 0.15 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2784959934
97.43 0.03 99.18 0.00 91.00 0.00 99.55 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3846908693
97.45 0.03 99.18 0.00 91.00 0.00 99.55 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2245269479
97.48 0.03 99.18 0.00 91.00 0.00 99.55 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3420505063
97.50 0.02 99.18 0.00 91.00 0.00 99.55 0.00 100.00 0.00 96.21 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3673028405
97.52 0.02 99.18 0.00 91.00 0.00 99.69 0.14 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.357694144
97.52 0.01 99.18 0.00 91.00 0.00 99.72 0.03 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1035218627

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1463849617
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3385296915
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2970460583
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2716412284
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2035473628
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3301085959
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1044961290
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3343531394
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3182207385
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3228477481
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3652152800
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.441115037
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4217169628
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2208568861
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2321039675
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.199611941
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1110543125
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1651159390
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.236461970
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1428863941
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.670556890
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2458123204
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3029560743
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1583312419
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3690075044
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2509424353
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2187170258
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.909408661
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1491287655
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.218992510
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3925727077
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.828354153
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2917788919
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.60878555
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.506580462
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4287090235
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.71837286
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2695708892
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2713352701
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.123062559
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1571815499
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.196971973
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.826600353
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.807735508
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3347639936
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3936653569
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.955072556
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.644639879
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2061068943
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1301356963
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.808615277
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3318732088
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1426103997
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2040355610
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.151480716
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1204165992
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3736186116
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3284954582
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2930337955
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1241334205
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4170780044
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2105249544
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.165187636
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2136989118
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.670488716
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.860569835
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.638715203
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1743441337
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3721050549
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.872380097
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.610104133
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.802481910
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4041105053
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2434698059
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1125572702
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3142612406
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2478529927
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1199719778
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.383856658
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1951275646
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3745709588
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1854719843
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4269757223
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4247283723
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1645685027
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/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1814533956
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.2243679913
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3929297136
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.940218958
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1606366910
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3938670957
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3940181232
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3245612700
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2901375358
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.65289534
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1857999239
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.657293286
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.3802966795
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2620510130
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4018311245
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2507904538
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.379872119
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2936158373
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1523254222
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.3532749473
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.1771560271
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1614454728
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3289687498
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2822679745
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.914148028
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1732814185
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3582177307
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.663920859
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.288050666
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.231931513
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.695172783
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.41146273
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.587744123
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1203218376
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2407966315
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2445395423
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3570521074
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1673898799
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.2345690798
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1167877081
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3018890113
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3405448552
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2388498680
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2993772646
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3479906001
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1283209725
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2914849485
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2388504557
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.3523146638
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3897192618
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1694743340
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.4201205049
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.676237111
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2137011740
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.579066004
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3009503869
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.535896386
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1167082875
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3175202161
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.956686384
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1548085326
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.44811859
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.794022101
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.935290166
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.1889817857
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.2419552167
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3767864200
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.927245055
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1055495
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3525836493



Total test records in report: 1033
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.711454101 Sep 01 09:50:58 AM UTC 24 Sep 01 09:51:05 AM UTC 24 1411654679 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2965845727 Sep 01 09:50:57 AM UTC 24 Sep 01 09:51:10 AM UTC 24 2874301727 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3170886112 Sep 01 09:50:56 AM UTC 24 Sep 01 09:51:18 AM UTC 24 887794740 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1533088855 Sep 01 09:51:19 AM UTC 24 Sep 01 09:51:24 AM UTC 24 394055108 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1430750459 Sep 01 09:51:24 AM UTC 24 Sep 01 09:51:26 AM UTC 24 39544660 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.1076662165 Sep 01 09:50:55 AM UTC 24 Sep 01 09:51:39 AM UTC 24 2569550882 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.831586633 Sep 01 09:51:27 AM UTC 24 Sep 01 09:51:43 AM UTC 24 1751542247 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1889598121 Sep 01 09:50:57 AM UTC 24 Sep 01 09:51:58 AM UTC 24 774144303 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2823277789 Sep 01 09:51:06 AM UTC 24 Sep 01 09:52:03 AM UTC 24 7770838312 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3542691367 Sep 01 09:50:58 AM UTC 24 Sep 01 09:52:09 AM UTC 24 22078997609 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.483026473 Sep 01 09:52:11 AM UTC 24 Sep 01 09:52:45 AM UTC 24 738539372 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2803604082 Sep 01 09:52:46 AM UTC 24 Sep 01 09:53:52 AM UTC 24 3437958654 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.4158912021 Sep 01 09:50:59 AM UTC 24 Sep 01 09:54:00 AM UTC 24 1631383280 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2755701643 Sep 01 09:52:05 AM UTC 24 Sep 01 09:54:16 AM UTC 24 3847575895 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2408519122 Sep 01 09:54:18 AM UTC 24 Sep 01 09:54:24 AM UTC 24 653317366 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1640706525 Sep 01 09:53:23 AM UTC 24 Sep 01 09:54:42 AM UTC 24 5908073617 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.2228244437 Sep 01 09:54:00 AM UTC 24 Sep 01 09:54:42 AM UTC 24 786290775 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3849232212 Sep 01 09:54:43 AM UTC 24 Sep 01 09:55:53 AM UTC 24 1654620911 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2337877518 Sep 01 09:55:53 AM UTC 24 Sep 01 09:55:55 AM UTC 24 40397383 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.357694144 Sep 01 09:55:53 AM UTC 24 Sep 01 09:55:57 AM UTC 24 118611301 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.143793991 Sep 01 09:55:54 AM UTC 24 Sep 01 09:56:11 AM UTC 24 2839894628 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.56952594 Sep 01 09:51:59 AM UTC 24 Sep 01 09:56:32 AM UTC 24 4539799562 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1212354011 Sep 01 09:54:43 AM UTC 24 Sep 01 09:56:47 AM UTC 24 43761679497 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2361949640 Sep 01 09:56:32 AM UTC 24 Sep 01 09:57:04 AM UTC 24 9109147449 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2784959934 Sep 01 09:54:25 AM UTC 24 Sep 01 09:57:17 AM UTC 24 62815613907 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1035218627 Sep 01 09:56:55 AM UTC 24 Sep 01 09:57:37 AM UTC 24 2952789769 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1166805399 Sep 01 09:50:56 AM UTC 24 Sep 01 09:57:54 AM UTC 24 4197535161 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1855670059 Sep 01 09:57:49 AM UTC 24 Sep 01 09:57:55 AM UTC 24 366680722 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.1163428325 Sep 01 09:56:48 AM UTC 24 Sep 01 09:58:03 AM UTC 24 8416134543 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2122837963 Sep 01 09:56:32 AM UTC 24 Sep 01 09:58:14 AM UTC 24 6391630941 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2844004259 Sep 01 09:58:09 AM UTC 24 Sep 01 09:58:14 AM UTC 24 746732062 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1759400515 Sep 01 09:58:14 AM UTC 24 Sep 01 09:58:16 AM UTC 24 14234336 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.869205397 Sep 01 09:57:56 AM UTC 24 Sep 01 09:58:19 AM UTC 24 382027561 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.4256823946 Sep 01 09:50:58 AM UTC 24 Sep 01 09:58:20 AM UTC 24 14569978545 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.4060910710 Sep 01 09:50:55 AM UTC 24 Sep 01 09:58:22 AM UTC 24 51837303310 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2487971608 Sep 01 09:58:15 AM UTC 24 Sep 01 09:58:29 AM UTC 24 407944131 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3899102251 Sep 01 09:52:10 AM UTC 24 Sep 01 09:58:39 AM UTC 24 13711564159 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3264017878 Sep 01 09:58:23 AM UTC 24 Sep 01 09:58:39 AM UTC 24 1968310693 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3221999874 Sep 01 09:58:40 AM UTC 24 Sep 01 09:58:59 AM UTC 24 1409176237 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1698667071 Sep 01 09:58:30 AM UTC 24 Sep 01 09:59:09 AM UTC 24 2860022073 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.642643018 Sep 01 09:50:56 AM UTC 24 Sep 01 09:59:11 AM UTC 24 19461452239 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.516522320 Sep 01 09:56:32 AM UTC 24 Sep 01 09:59:24 AM UTC 24 6780685530 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.106237332 Sep 01 09:59:25 AM UTC 24 Sep 01 09:59:32 AM UTC 24 2806416488 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.444067289 Sep 01 09:56:12 AM UTC 24 Sep 01 09:59:35 AM UTC 24 21962104687 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2237530381 Sep 01 09:55:56 AM UTC 24 Sep 01 09:59:52 AM UTC 24 4321721146 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2458614752 Sep 01 09:57:55 AM UTC 24 Sep 01 09:59:53 AM UTC 24 2986468580 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1102711843 Sep 01 09:59:54 AM UTC 24 Sep 01 09:59:56 AM UTC 24 12282269 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.4144336667 Sep 01 09:59:33 AM UTC 24 Sep 01 09:59:59 AM UTC 24 346101079 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.537142079 Sep 01 09:59:53 AM UTC 24 Sep 01 10:00:00 AM UTC 24 735864723 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1543881713 Sep 01 09:58:40 AM UTC 24 Sep 01 10:00:09 AM UTC 24 53910321717 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3591806061 Sep 01 09:57:49 AM UTC 24 Sep 01 10:00:33 AM UTC 24 11957668302 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.341842639 Sep 01 10:00:22 AM UTC 24 Sep 01 10:00:50 AM UTC 24 948376704 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1164627104 Sep 01 09:59:57 AM UTC 24 Sep 01 10:00:53 AM UTC 24 1770837546 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2204148047 Sep 01 10:01:07 AM UTC 24 Sep 01 10:01:42 AM UTC 24 2579716966 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1641193769 Sep 01 09:59:26 AM UTC 24 Sep 01 10:01:51 AM UTC 24 10734593940 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3997589392 Sep 01 10:00:54 AM UTC 24 Sep 01 10:01:59 AM UTC 24 3570842067 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1138380348 Sep 01 10:02:09 AM UTC 24 Sep 01 10:02:15 AM UTC 24 359400431 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.779472262 Sep 01 09:50:58 AM UTC 24 Sep 01 10:02:25 AM UTC 24 21725733102 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2354701399 Sep 01 10:00:51 AM UTC 24 Sep 01 10:02:37 AM UTC 24 9547615544 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.1434720242 Sep 01 09:51:45 AM UTC 24 Sep 01 10:02:43 AM UTC 24 7256351773 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.930924612 Sep 01 09:51:41 AM UTC 24 Sep 01 10:02:48 AM UTC 24 12555124509 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1447810590 Sep 01 10:02:49 AM UTC 24 Sep 01 10:02:53 AM UTC 24 281873384 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.496574673 Sep 01 10:02:54 AM UTC 24 Sep 01 10:02:56 AM UTC 24 34047470 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.843807821 Sep 01 10:02:39 AM UTC 24 Sep 01 10:02:56 AM UTC 24 300869977 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.304335067 Sep 01 10:02:57 AM UTC 24 Sep 01 10:03:20 AM UTC 24 1058026282 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3985978495 Sep 01 09:58:21 AM UTC 24 Sep 01 10:03:45 AM UTC 24 29977232650 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3248064781 Sep 01 09:53:39 AM UTC 24 Sep 01 10:03:48 AM UTC 24 47839758501 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.3262387323 Sep 01 09:57:44 AM UTC 24 Sep 01 10:04:13 AM UTC 24 2967678792 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2964857179 Sep 01 09:50:58 AM UTC 24 Sep 01 10:04:25 AM UTC 24 7122659453 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2278845078 Sep 01 10:02:26 AM UTC 24 Sep 01 10:04:26 AM UTC 24 13922461208 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.62777832 Sep 01 10:01:52 AM UTC 24 Sep 01 10:05:13 AM UTC 24 30554077643 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3079461351 Sep 01 10:03:49 AM UTC 24 Sep 01 10:05:13 AM UTC 24 3457063365 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3419456441 Sep 01 09:50:56 AM UTC 24 Sep 01 10:05:25 AM UTC 24 45095793541 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.67520288 Sep 01 10:02:15 AM UTC 24 Sep 01 10:05:28 AM UTC 24 27664166315 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2613122368 Sep 01 10:05:26 AM UTC 24 Sep 01 10:05:32 AM UTC 24 348398743 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2821598847 Sep 01 10:04:26 AM UTC 24 Sep 01 10:05:47 AM UTC 24 796915400 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3656133962 Sep 01 10:04:22 AM UTC 24 Sep 01 10:05:52 AM UTC 24 790441116 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2334115633 Sep 01 10:04:27 AM UTC 24 Sep 01 10:06:16 AM UTC 24 23288867729 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.225146337 Sep 01 10:06:16 AM UTC 24 Sep 01 10:06:18 AM UTC 24 20628837 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3335528979 Sep 01 10:01:43 AM UTC 24 Sep 01 10:06:28 AM UTC 24 26229041473 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.430251436 Sep 01 09:59:00 AM UTC 24 Sep 01 10:06:31 AM UTC 24 32246561267 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2132314126 Sep 01 10:05:48 AM UTC 24 Sep 01 10:07:29 AM UTC 24 27999982859 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.3802966795 Sep 01 10:06:19 AM UTC 24 Sep 01 10:07:30 AM UTC 24 1144800322 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2459415830 Sep 01 10:00:09 AM UTC 24 Sep 01 10:07:35 AM UTC 24 19235269783 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2901375358 Sep 01 10:07:12 AM UTC 24 Sep 01 10:07:43 AM UTC 24 10447003642 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1606366910 Sep 01 10:07:30 AM UTC 24 Sep 01 10:08:10 AM UTC 24 744012921 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2214600070 Sep 01 10:05:30 AM UTC 24 Sep 01 10:08:14 AM UTC 24 2002062093 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.343589176 Sep 01 10:00:34 AM UTC 24 Sep 01 10:08:21 AM UTC 24 59595172627 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2103495272 Sep 01 09:59:25 AM UTC 24 Sep 01 10:08:23 AM UTC 24 128299560013 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1857999239 Sep 01 10:08:26 AM UTC 24 Sep 01 10:08:32 AM UTC 24 1772126881 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.3078371464 Sep 01 10:05:34 AM UTC 24 Sep 01 10:08:42 AM UTC 24 19059330442 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1814533956 Sep 01 10:08:43 AM UTC 24 Sep 01 10:08:45 AM UTC 24 15018660 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.379872119 Sep 01 10:07:31 AM UTC 24 Sep 01 10:08:53 AM UTC 24 775461113 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.2773408045 Sep 01 09:53:53 AM UTC 24 Sep 01 10:08:53 AM UTC 24 17333361730 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.940218958 Sep 01 10:07:36 AM UTC 24 Sep 01 10:09:13 AM UTC 24 34800274714 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3582177307 Sep 01 10:09:13 AM UTC 24 Sep 01 10:09:30 AM UTC 24 526298238 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4018311245 Sep 01 10:08:26 AM UTC 24 Sep 01 10:09:31 AM UTC 24 3681204405 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3073243254 Sep 01 09:57:04 AM UTC 24 Sep 01 10:09:33 AM UTC 24 51006525426 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.695172783 Sep 01 10:08:46 AM UTC 24 Sep 01 10:09:33 AM UTC 24 1084875787 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3938670957 Sep 01 10:08:26 AM UTC 24 Sep 01 10:10:07 AM UTC 24 2805396376 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3289687498 Sep 01 10:09:33 AM UTC 24 Sep 01 10:10:09 AM UTC 24 757304320 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2265962325 Sep 01 10:04:14 AM UTC 24 Sep 01 10:10:14 AM UTC 24 5220395569 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2407966315 Sep 01 10:09:34 AM UTC 24 Sep 01 10:10:45 AM UTC 24 777138726 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.288050666 Sep 01 10:10:44 AM UTC 24 Sep 01 10:10:50 AM UTC 24 1408528914 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1886223256 Sep 01 09:50:58 AM UTC 24 Sep 01 10:10:50 AM UTC 24 71078411578 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2016180256 Sep 01 09:58:30 AM UTC 24 Sep 01 10:10:56 AM UTC 24 290976337965 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1523254222 Sep 01 10:11:02 AM UTC 24 Sep 01 10:11:04 AM UTC 24 41025266 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.3523146638 Sep 01 10:11:04 AM UTC 24 Sep 01 10:11:18 AM UTC 24 2824923053 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1614454728 Sep 01 10:09:34 AM UTC 24 Sep 01 10:11:29 AM UTC 24 55372802135 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.3156381995 Sep 01 09:59:25 AM UTC 24 Sep 01 10:11:38 AM UTC 24 10413772532 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2936158373 Sep 01 10:10:08 AM UTC 24 Sep 01 10:11:50 AM UTC 24 9231308031 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2507904538 Sep 01 10:06:49 AM UTC 24 Sep 01 10:11:59 AM UTC 24 3123932730 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2822679745 Sep 01 10:10:52 AM UTC 24 Sep 01 10:12:03 AM UTC 24 6592913995 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.96508620 Sep 01 10:05:15 AM UTC 24 Sep 01 10:12:12 AM UTC 24 28539715768 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3989711819 Sep 01 10:03:46 AM UTC 24 Sep 01 10:12:40 AM UTC 24 6357766379 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.676237111 Sep 01 10:12:04 AM UTC 24 Sep 01 10:12:47 AM UTC 24 6203009749 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3479906001 Sep 01 10:11:39 AM UTC 24 Sep 01 10:12:55 AM UTC 24 499815808 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3940181232 Sep 01 10:08:26 AM UTC 24 Sep 01 10:12:58 AM UTC 24 3958039840 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2914849485 Sep 01 10:12:58 AM UTC 24 Sep 01 10:13:05 AM UTC 24 698266261 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1203218376 Sep 01 10:09:04 AM UTC 24 Sep 01 10:13:07 AM UTC 24 3548355382 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3245612700 Sep 01 10:06:29 AM UTC 24 Sep 01 10:13:20 AM UTC 24 3952981634 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3018890113 Sep 01 10:12:00 AM UTC 24 Sep 01 10:13:33 AM UTC 24 791988152 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3570521074 Sep 01 10:13:34 AM UTC 24 Sep 01 10:13:36 AM UTC 24 28262741 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3843289947 Sep 01 10:02:08 AM UTC 24 Sep 01 10:13:41 AM UTC 24 45852875601 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1167877081 Sep 01 10:12:13 AM UTC 24 Sep 01 10:13:44 AM UTC 24 10620478654 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3912535126 Sep 01 10:00:00 AM UTC 24 Sep 01 10:13:46 AM UTC 24 15942384066 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2281661514 Sep 01 09:58:16 AM UTC 24 Sep 01 10:13:50 AM UTC 24 14653786031 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3929297136 Sep 01 10:08:15 AM UTC 24 Sep 01 10:13:56 AM UTC 24 11311621239 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.44811859 Sep 01 10:13:51 AM UTC 24 Sep 01 10:14:02 AM UTC 24 704499204 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.587744123 Sep 01 10:10:52 AM UTC 24 Sep 01 10:14:05 AM UTC 24 16655803706 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.2419552167 Sep 01 10:13:37 AM UTC 24 Sep 01 10:14:09 AM UTC 24 2706320413 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1167082875 Sep 01 10:14:03 AM UTC 24 Sep 01 10:14:36 AM UTC 24 1433952126 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1775980076 Sep 01 09:59:13 AM UTC 24 Sep 01 10:15:06 AM UTC 24 9241903506 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3525836493 Sep 01 10:14:05 AM UTC 24 Sep 01 10:15:18 AM UTC 24 814591894 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.663920859 Sep 01 10:09:30 AM UTC 24 Sep 01 10:15:21 AM UTC 24 44317493353 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2891282228 Sep 01 10:14:09 AM UTC 24 Sep 01 10:15:28 AM UTC 24 46409573705 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.935290166 Sep 01 10:15:22 AM UTC 24 Sep 01 10:15:30 AM UTC 24 1303620987 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.4201205049 Sep 01 10:11:34 AM UTC 24 Sep 01 10:16:24 AM UTC 24 5422780953 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3405448552 Sep 01 10:13:13 AM UTC 24 Sep 01 10:16:40 AM UTC 24 5117939248 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.908529958 Sep 01 10:05:16 AM UTC 24 Sep 01 10:16:47 AM UTC 24 17719477068 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.579066004 Sep 01 10:16:48 AM UTC 24 Sep 01 10:16:50 AM UTC 24 35308941 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1694743340 Sep 01 10:13:13 AM UTC 24 Sep 01 10:17:02 AM UTC 24 8050428035 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1248523749 Sep 01 10:16:51 AM UTC 24 Sep 01 10:17:21 AM UTC 24 1441883969 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3175202161 Sep 01 10:15:31 AM UTC 24 Sep 01 10:17:34 AM UTC 24 9467820311 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.927245055 Sep 01 10:16:25 AM UTC 24 Sep 01 10:17:40 AM UTC 24 1959478411 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.916615573 Sep 01 09:57:17 AM UTC 24 Sep 01 10:17:46 AM UTC 24 85209105649 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.914148028 Sep 01 10:10:46 AM UTC 24 Sep 01 10:17:50 AM UTC 24 27733544581 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.3271950372 Sep 01 10:17:41 AM UTC 24 Sep 01 10:18:15 AM UTC 24 2054254044 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.65289534 Sep 01 10:07:29 AM UTC 24 Sep 01 10:18:16 AM UTC 24 57698638840 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1283209725 Sep 01 10:11:51 AM UTC 24 Sep 01 10:18:33 AM UTC 24 13061263488 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1665280215 Sep 01 10:02:57 AM UTC 24 Sep 01 10:18:37 AM UTC 24 54820930194 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3795899502 Sep 01 10:17:51 AM UTC 24 Sep 01 10:18:53 AM UTC 24 6764814098 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.4153228839 Sep 01 10:18:16 AM UTC 24 Sep 01 10:19:03 AM UTC 24 759187279 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2325626326 Sep 01 10:19:03 AM UTC 24 Sep 01 10:19:10 AM UTC 24 343693967 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1055495 Sep 01 10:13:47 AM UTC 24 Sep 01 10:19:11 AM UTC 24 15196410289 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2388498680 Sep 01 10:13:12 AM UTC 24 Sep 01 10:19:18 AM UTC 24 13825010586 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.956686384 Sep 01 10:15:29 AM UTC 24 Sep 01 10:19:28 AM UTC 24 15762462387 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1565469962 Sep 01 10:19:20 AM UTC 24 Sep 01 10:19:31 AM UTC 24 457270143 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.1681689610 Sep 01 10:18:17 AM UTC 24 Sep 01 10:19:34 AM UTC 24 5758655797 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.182900947 Sep 01 10:19:32 AM UTC 24 Sep 01 10:19:34 AM UTC 24 31403815 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.2243679913 Sep 01 10:06:32 AM UTC 24 Sep 01 10:19:53 AM UTC 24 55990174277 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.1187439701 Sep 01 10:19:35 AM UTC 24 Sep 01 10:20:08 AM UTC 24 7315286406 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3047371739 Sep 01 10:07:43 AM UTC 24 Sep 01 10:20:23 AM UTC 24 8521151098 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1410413895 Sep 01 10:19:11 AM UTC 24 Sep 01 10:20:27 AM UTC 24 1012319220 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2812644447 Sep 01 10:20:24 AM UTC 24 Sep 01 10:20:41 AM UTC 24 1546615137 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.64241617 Sep 01 10:20:40 AM UTC 24 Sep 01 10:21:26 AM UTC 24 1345758377 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.1771560271 Sep 01 10:10:10 AM UTC 24 Sep 01 10:21:27 AM UTC 24 75925989384 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1965226430 Sep 01 10:20:43 AM UTC 24 Sep 01 10:21:35 AM UTC 24 738289924 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1957078464 Sep 01 10:19:10 AM UTC 24 Sep 01 10:22:01 AM UTC 24 26272542336 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.794022101 Sep 01 10:13:57 AM UTC 24 Sep 01 10:22:04 AM UTC 24 64451993744 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3742143880 Sep 01 10:22:04 AM UTC 24 Sep 01 10:22:11 AM UTC 24 361271015 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3066875052 Sep 01 10:05:16 AM UTC 24 Sep 01 10:22:24 AM UTC 24 5147118290 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3850237488 Sep 01 10:17:34 AM UTC 24 Sep 01 10:22:27 AM UTC 24 17491485974 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1382009721 Sep 01 10:21:27 AM UTC 24 Sep 01 10:22:31 AM UTC 24 40214933573 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1953960303 Sep 01 10:22:28 AM UTC 24 Sep 01 10:22:39 AM UTC 24 363777273 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3002357335 Sep 01 10:22:40 AM UTC 24 Sep 01 10:22:42 AM UTC 24 15964183 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1548085326 Sep 01 10:13:41 AM UTC 24 Sep 01 10:23:10 AM UTC 24 7330107492 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2247347439 Sep 01 10:00:01 AM UTC 24 Sep 01 10:23:10 AM UTC 24 304258302226 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.3349008519 Sep 01 10:22:43 AM UTC 24 Sep 01 10:23:19 AM UTC 24 4294692517 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2925067638 Sep 01 10:02:44 AM UTC 24 Sep 01 10:23:38 AM UTC 24 44270714419 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2333746841 Sep 01 10:23:40 AM UTC 24 Sep 01 10:24:13 AM UTC 24 625174368 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.231931513 Sep 01 10:10:14 AM UTC 24 Sep 01 10:24:30 AM UTC 24 3381352278 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.657293286 Sep 01 10:08:25 AM UTC 24 Sep 01 10:24:31 AM UTC 24 34985083238 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.535896386 Sep 01 10:15:07 AM UTC 24 Sep 01 10:24:36 AM UTC 24 47506558165 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1607492452 Sep 01 10:24:32 AM UTC 24 Sep 01 10:24:43 AM UTC 24 1393212881 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.4134471839 Sep 01 10:20:09 AM UTC 24 Sep 01 10:24:47 AM UTC 24 15183031363 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2993772646 Sep 01 10:11:19 AM UTC 24 Sep 01 10:24:53 AM UTC 24 27669725227 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3008920318 Sep 01 10:22:12 AM UTC 24 Sep 01 10:25:11 AM UTC 24 1986939275 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1852031869 Sep 01 10:25:12 AM UTC 24 Sep 01 10:25:19 AM UTC 24 342909728 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.2345690798 Sep 01 10:12:47 AM UTC 24 Sep 01 10:25:29 AM UTC 24 96045146539 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.121493289 Sep 01 10:22:25 AM UTC 24 Sep 01 10:26:00 AM UTC 24 4855343285 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.918514704 Sep 01 10:24:30 AM UTC 24 Sep 01 10:26:08 AM UTC 24 3813954080 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.4169982478 Sep 01 10:26:10 AM UTC 24 Sep 01 10:26:12 AM UTC 24 20258397 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3980086335 Sep 01 10:26:09 AM UTC 24 Sep 01 10:26:21 AM UTC 24 427801471 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1442649112 Sep 01 09:59:36 AM UTC 24 Sep 01 10:26:27 AM UTC 24 57286030785 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.3323531069 Sep 01 10:18:53 AM UTC 24 Sep 01 10:26:38 AM UTC 24 3091382731 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1209555223 Sep 01 10:26:13 AM UTC 24 Sep 01 10:26:38 AM UTC 24 799758457 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3269150858 Sep 01 10:23:20 AM UTC 24 Sep 01 10:27:02 AM UTC 24 29335829916 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2388504557 Sep 01 10:12:56 AM UTC 24 Sep 01 10:27:22 AM UTC 24 67347943795 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.4123266890 Sep 01 10:17:03 AM UTC 24 Sep 01 10:27:24 AM UTC 24 106827915683 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.4030908684 Sep 01 10:26:39 AM UTC 24 Sep 01 10:27:28 AM UTC 24 1604414925 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1086140706 Sep 01 10:24:37 AM UTC 24 Sep 01 10:27:58 AM UTC 24 90377268088 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3982555134 Sep 01 10:27:03 AM UTC 24 Sep 01 10:28:09 AM UTC 24 840048641 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1439374543 Sep 01 10:25:20 AM UTC 24 Sep 01 10:28:36 AM UTC 24 8226940060 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2137011740 Sep 01 10:14:37 AM UTC 24 Sep 01 10:28:43 AM UTC 24 51689034260 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2729142227 Sep 01 10:28:38 AM UTC 24 Sep 01 10:28:45 AM UTC 24 1347157931 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1665849398 Sep 01 10:25:30 AM UTC 24 Sep 01 10:29:05 AM UTC 24 36409059540 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2739938005 Sep 01 10:20:27 AM UTC 24 Sep 01 10:29:07 AM UTC 24 30792102309 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2157395462 Sep 01 10:27:24 AM UTC 24 Sep 01 10:29:16 AM UTC 24 21512202662 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1305890537 Sep 01 10:29:17 AM UTC 24 Sep 01 10:29:19 AM UTC 24 34696760 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1869986833 Sep 01 10:27:23 AM UTC 24 Sep 01 10:29:25 AM UTC 24 3133796843 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.3328977562 Sep 01 10:22:01 AM UTC 24 Sep 01 10:29:42 AM UTC 24 12672779877 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1655264901 Sep 01 10:29:06 AM UTC 24 Sep 01 10:29:42 AM UTC 24 675004296 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.857540973 Sep 01 10:29:20 AM UTC 24 Sep 01 10:29:47 AM UTC 24 8002267376 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.3532749473 Sep 01 10:08:54 AM UTC 24 Sep 01 10:30:02 AM UTC 24 159329215167 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.288122157 Sep 01 10:30:03 AM UTC 24 Sep 01 10:30:20 AM UTC 24 704508950 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3025295802 Sep 01 10:29:36 AM UTC 24 Sep 01 10:30:24 AM UTC 24 2655366242 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.3263409665 Sep 01 10:30:21 AM UTC 24 Sep 01 10:30:30 AM UTC 24 691765371 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.2090540370 Sep 01 10:29:44 AM UTC 24 Sep 01 10:30:43 AM UTC 24 489369890 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2445395423 Sep 01 10:12:41 AM UTC 24 Sep 01 10:30:49 AM UTC 24 22275167602 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.3609802095 Sep 01 10:18:38 AM UTC 24 Sep 01 10:30:55 AM UTC 24 90232934375 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3228372744 Sep 01 10:30:56 AM UTC 24 Sep 01 10:31:02 AM UTC 24 398832006 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.782647605 Sep 01 10:17:47 AM UTC 24 Sep 01 10:31:05 AM UTC 24 99177725336 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2053950293 Sep 01 10:26:39 AM UTC 24 Sep 01 10:31:06 AM UTC 24 3972665939 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.934486088 Sep 01 10:24:48 AM UTC 24 Sep 01 10:31:09 AM UTC 24 3948316966 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.3518674827 Sep 01 10:30:44 AM UTC 24 Sep 01 10:31:13 AM UTC 24 5401285694 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.1900141329 Sep 01 10:31:13 AM UTC 24 Sep 01 10:31:15 AM UTC 24 15963322 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.469167399 Sep 01 10:31:16 AM UTC 24 Sep 01 10:31:27 AM UTC 24 2905766934 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.1882603673 Sep 01 10:18:34 AM UTC 24 Sep 01 10:31:42 AM UTC 24 14237081407 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1726244825 Sep 01 10:30:25 AM UTC 24 Sep 01 10:31:49 AM UTC 24 11606467441 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1150321008 Sep 01 10:28:46 AM UTC 24 Sep 01 10:31:56 AM UTC 24 5256795926 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3078553865 Sep 01 10:29:43 AM UTC 24 Sep 01 10:32:14 AM UTC 24 4303238182 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3566556247 Sep 01 10:31:07 AM UTC 24 Sep 01 10:32:48 AM UTC 24 2416643746 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1119692054 Sep 01 10:28:44 AM UTC 24 Sep 01 10:32:56 AM UTC 24 11891546239 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1416989338 Sep 01 10:26:34 AM UTC 24 Sep 01 10:33:07 AM UTC 24 4140186802 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.1828015795 Sep 01 10:31:56 AM UTC 24 Sep 01 10:33:31 AM UTC 24 1040134832 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2839846184 Sep 01 10:27:29 AM UTC 24 Sep 01 10:33:36 AM UTC 24 11245986273 ps
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